WO2008023437A1 - Dispositif semi-conducteur - Google Patents

Dispositif semi-conducteur Download PDF

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Publication number
WO2008023437A1
WO2008023437A1 PCT/JP2006/316750 JP2006316750W WO2008023437A1 WO 2008023437 A1 WO2008023437 A1 WO 2008023437A1 JP 2006316750 W JP2006316750 W JP 2006316750W WO 2008023437 A1 WO2008023437 A1 WO 2008023437A1
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Prior art keywords
cell
circuit
semiconductor device
input signal
input
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PCT/JP2006/316750
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English (en)
Japanese (ja)
Inventor
Motoyasu Terao
Yoshitaka Sasago
Kenzo Kurotsuchi
Koichi Tsuzuki
Satoru Hanzawa
Osamu Tonomura
Norikatsu Takaura
Nozomu Matsuzaki
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Hitachi, Ltd.
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Priority to PCT/JP2006/316750 priority Critical patent/WO2008023437A1/fr
Priority to JP2008530789A priority patent/JPWO2008023437A1/ja
Publication of WO2008023437A1 publication Critical patent/WO2008023437A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a semiconductor device having memory and logic judgment capabilities close to humans. For example, it can be used for autonomous and autonomous robots that can act independently and have creativity, or autonomous driving vehicles that have excellent pattern recognition and comprehensive judgment capabilities, and can respond to sudden dangers instantly.
  • the present invention relates to a technology effective when applied to a semiconductor device having suitable characteristics.
  • the human cerebral neocortex can recognize patterns in several tens of steps. Compared with memory, even fragmented input information can be interpolated to make correct decisions. They have the ability to easily accomplish things that are impossible or difficult with computers, such as being able to demonstrate “inspiration”, a visionary insight.
  • Non-Patent Document 1 Tomoharu Nagao, “Optimization Algorithm (Chapter 8)”, Shosodo Co., Ltd., May 2000, P.104
  • Non-Patent Literature 2 Shunichi Amari, Yoshifumi Sekine, et al. “Toward the realization of a brain-type computer”, Extra Volume Mathematical Science, SGC Library 26, Science Co., Ltd., September 2003, p.54-p. 60
  • Non-Patent Document 3 Supervised by Kazuya Nagago, Taketo Onose, “Brain and Kokoro Co., Ltd.”, Kanki Publishing, July 2003, p.64
  • Non-Patent Document 4 Masaya Toyama, Koichi Takatsuki et al., “Molecular Brain, Neural Function Anatomy”, Kinyoshido Co., Ltd., June 2004, p.208
  • Non-Patent Document 5 Michiichi Matsumura “Invitation to Brain Science (Library Brain Century: Exploring the Mechanism of Mind)” No.l, Science Co., Ltd., September 2002, P.102
  • the conventional artificial intelligence device has a face that is not far from human ability while aiming at ability close to human being.
  • the above-mentioned software and hardware neural network can perform pattern recognition of a force-fixed two-dimensional pattern that is intended to solve the disadvantages of Neumann computers, but the pattern moves greatly.
  • it has very limited ability compared to the ability of the human cerebral neocortex to be able to recognize accurately, to interpolate based on memory, and to cope with it by prediction.
  • This is due to the restriction of the combination of existing semiconductor devices and the brain function has been changed and simplified, and the parallel processing information of the neural network is recorded and reproduced as it is in parallel processing. This is thought to be due to the absence of the “memory” device, the lack of a means of associating memory with the necessary flexibility for association and recognition universalization.
  • Non-Patent Document 4 in the field of anatomy, in the case of the human cerebral neocortex, the nerve cell power in the newborn has not yet stretched, and the newborn Axon generation and branching between 2-year-olds is known to increase by increasing synapses and learning by increasing wiring. This difference is also thought to be the reason why the learning efficiency of conventional hardware-Ural network devices is low and has limited ability and inability. Also, looking at Figure 4-7 in Non-Patent Document 5, in the visual cortex, axons are branched into several tens in the cross section of the 4A layer.
  • an object of the present invention is to provide a semiconductor device that has a configuration and function closer to those of the cerebral neocortex than before, has high learning ability, and can think independently and determine by connection with a memory system. It is to provide.
  • the above meaning of independence indicates that it is possible to grow so that advanced and creative logical thinking can be achieved by combining the memories by giving basic logical thinking information from visual and auditory senses, as in education for human infants.
  • growth refers to growth of device functions corresponding to cerebral functions.
  • Main means for achieving the above object are as follows.
  • one of the output electrodes and one of the input electrodes of another similar circuit are electrically connected or disconnected, so that By increasing or decreasing the number,
  • the member that generates conductivity includes a first component including an insulator or a semiconductor, and a second component discharge cell filled with a second component including a metal ion. This can be achieved by providing a member including an electrolyte provided between the second component discharge cell and a plurality of second component discharge cells arranged at a predetermined distance from the second component discharge cell.
  • the nerve cell has an input threshold value, and when it exceeds the threshold value, it is excited and outputs a pulse output. Even after the threshold is exceeded, the intensity of the output pulse (the amount of neurotransmitter released at the synapse) and the frequency change in an analog fashion.
  • the intensity of the output pulse the amount of neurotransmitter released at the synapse
  • the frequency change in an analog fashion.
  • the perceptron and cog-tron which are conventional -Ural network devices, are compared with the device of the present invention.
  • a fixed panel depicting a triangle is read by a two-dimensional sensor, and an output element outputs digital data 1 for the triangle.
  • the wiring selection is advanced by making the coupling constant almost 0 and disconnecting the unnecessary one of the network wiring, or changing the connection coefficient of the connection part so that it does not function.
  • a connection function is provided so that the element that receives the sensor's most powerful input at the contour outputs a stronger output than the elements on both sides of the element, and learning is performed with a very large number of steps.
  • the wiring is first formed, and the wiring is the same for the element that recognizes the triangle and the element that recognizes the circle at first. Yes. Learning by reducing wiring with such a configuration. As a device, it does not grow, but learns by degeneration, and the situation is worse than teaching a new foreign language to a human old man.
  • Neocog-Tron has a multi-stage configuration that allows recognition of the same figure even if the place in the field of view is slightly shifted, so learning ability when other figures are presented at the same place
  • the device of the present invention does not have the ability aimed at.
  • a new branch is generated for a new input signal, and the wiring is strengthened by repeated input or feedback.
  • a feature of the device of the present invention is that it has a new branching rule for a new input. In other words, it has the property of learning while growing like an infant, so it has high learning efficiency. In the case of language learning, there is a possibility that it will be an efficient and perfect learning for young children to learn their native language.
  • Fig. 1 is a cross-sectional view, but as shown in Fig. 17, it extends from the top at approximately the same distance in the plane seen from the top around each of the branched parts extending from the bottom in Fig. 1. If the voltage is applied, the ion wiring can be formed with almost equal probability.
  • learning is performed while increasing the number of wires and changing their strength.
  • the second and subsequent new learnings proceed with almost the same efficiency as the first learning because there is a sufficient number of usable wires.
  • Wiring that has not been strengthened will be cut off by repeated application of an electric field in a direction different from wiring strengthening if other learning is performed, so that the number of new wires that can be used is secured even if learning is repeated.
  • FIG. 14 shows a correspondence table between the device of the present invention and the cerebral neocortex.
  • the memory can be used in the device of the present invention because the memory applies the parallel processing as it is as in the cerebral neocortex.
  • a large number of memories are formed in parallel as new wirings between cells corresponding to nerve cells, for example, wirings due to changes in ion distribution.
  • Traditional -Eural network devices originally have no interaction with storage. This is because the memory is stored as serial digital data on a hard disk, etc., and if you try to use it, the characteristics of the neural network device called parallel processing will be lost.
  • a high concentration region of ions is driven by an electric field in a solid electrolyte to reduce the electrical resistance of a path between cells corresponding to two nerve cells, Or use a memory mechanism.
  • This memory mechanism is very similar to the connection between nerve cells because it can increase the wiring between cells, eliminate the wiring, or strengthen the wiring with repeated voltage.
  • the solid electrolyte may be an inorganic material or an organic material. In view of heat resistance, an inorganic material is preferable.
  • Such a memory mechanism can be used for the increase and optimization of wiring corresponding to the increase in axon wiring in the cerebral neocortex layer structure 'hierarchical structure and optimization by scrap and build, and in the storage area. It can also be used for memory formation as axon compatible wiring.
  • Other memory mechanisms may be used for wiring formation as long as the resistance changes. Input from a two-dimensional optical sensor or microphone is first memorized.
  • the device of the present invention has a memory area, a logical processing area, and an area corresponding to a transfer path (bus) between them, and has the same architecture as the CPU of the current computer.
  • a transfer path bus
  • advanced functions similar to the entire cerebral neocortex can be realized.
  • at least one of these areas and the transfer path is the one described in the present invention, and the rest is used. Even with hybrid systems that use conventional CPU components, they can be operated with limited functions, and can produce powerful features not available with conventional CPUs.
  • the present invention in addition to newly generating wiring and means for storing in the form of parallel processing, another major feature is that it has means for extracting the memory and comparing it in parallel processing. It is possible to form a universal memory by grouping together memory. Furthermore, as shown in FIG. 13, it has a hierarchical structure like the cerebral neocortex.
  • the reason why the cerebral neocortex has a hierarchical structure as shown in Fig. 13 is that the past memory is referred to from the time series information of parallel multi-input obtained by sensing by visual, auditory, tactile, etc. of the external world. It is to get the universal recognition of the outside world.
  • FIG. 3 shows a conceptual diagram in the case of a visual system configured to realize the learning and growth action of the cerebral neocortex as described above with a semiconductor device.
  • Figure 4 shows the process of forming a universal recognition of a triangle. The process of forming universal recognition can be done in the same way as making an infant recognize a figure. When recognizing a polygon, it is common to teach by counting the corners. In addition, infants are likely to recognize black outlines. Therefore, the corner portion, which is a feature point of the figure, is first pointed, and for example, “Kado” is input to the device by voice to store the voice and the corner figure.
  • Recognition of feature points of a figure with corners is performed by, for example, the movement of the center of the sensing of the two-dimensional photosensor corresponding to the line of sight or transfer in a logical system.
  • the length of the memory time series is about 1 to 2 minutes, similar to humans.
  • Cell powers that recognize triangles with different shapes are sent to the upper layer as signals and connection signals for association, and triangle signals of many shapes are read associatively at the upper layer during readout. Connected to.
  • the representative cell of these associated groups is a universal cell, which is a recognition of a generalized triangle, regardless of shape.
  • the area surrounded by a large square near the center in Fig. 3 is the cognitive / thinking area.
  • Figs. There is a cell array with a back loop that corresponds to the part that forms some back loop with either S or NO.
  • One output of the decision cell is inverted through the NOT cell.
  • This is an inverting amplifier when an operational amplifier is used, and it may be considered that it corresponds to the inhibitory neurotransmitter release of nerve cells. You can use a circuit that is simpler than an inverting amplifier. In this area, the comparison between the storage and the input signal is performed.
  • the horizontal part of the network shown in FIG. 6 is the circuit, and how many times to go back is learned when you first teach logic processing by voice or text.
  • the ON / OFF pattern of the cell circuit for neuronal cells (hereinafter referred to as cell circuit, abbreviated as UC) stored as control memory in the diagonal circuit is sent to this part to stop it, and the ion wiring Can be determined by forming Similar to storing images, etc., the pattern with or without output is stopped at the part where the loop circuit with ion wiring is added to each cell circuit or cell circuit and dummy cell circuit, and the ion wiring is strengthened according to the pattern. You may do this as well.
  • the actual comparison is performed using the comparison circuit in the center of Fig. 3.
  • the memory index is a group consisting of association categories.
  • One category of association is a common point (matching point) such as individual logic of the group.
  • keywords, key images, key sounds, etc. such as V, characters, voices, and arithmetic symbols used in the process are indexed.
  • the visual system comparison process in Fig. 3 it is compared with the keyword group of logic processing stored in the past. If there is a matching keyword, the readout trigger paths are connected by, for example, ion wiring so that associative readout is performed one after another. Matching parts such as keywords are categories of association.
  • a conventional nonvolatile memory such as a flash memory, a hard disk, an optical disk, etc.
  • a parallel recording system also requires data conversion such as AD conversion, DA conversion, and MPEG. Even in that case, it is desirable to have multiple inputs / outputs and heads to enable at least partial parallel recording and playback.
  • the transfer of the memory is performed as follows. As shown in FIG. 12, time-series storage for a certain period of time, for example several minutes, is successively transferred to adjacent columnar structures and further transferred to the storage system. If a cell is oscillating or oscillating, or if it is not oscillating, there are several ways to transfer any time series pattern.
  • a method of providing a circuit is a good method. In this case, the ring circuit of the ring oscillator of the dummy cell circuit adjacent to each cell circuit in the transfer direction is connected by a switch circuit, and if the cell circuit oscillates, it oscillates and oscillates in the entire loop. So that the whole does not oscillate.
  • the two ring oscillators before and after the two cells are separated again, and oscillation is stopped by inserting a large resistor in the loop of the cell circuit that was oscillating backward. If the cell circuit does not oscillate, the loop circuit is connected and disconnected in the same way, but neither the cell circuit nor the dummy cell circuit oscillates. Transfer can be performed by repeating the above.
  • Another method is to provide another dummy line parallel to the line to be transferred and , Or not, oscillating, and not oscillating patterns are transferred to the dummy line by disconnecting the loop circuit in the same manner as above, and then transferred to the dummy line. It is also possible to stop the oscillation of the cells in the area, and then shift the pattern by one cell circuit and transfer the pattern to the original line with the dummy line force in the same manner as described above. However, the former method of providing dummy cell circuits is considered to require less space.
  • memory is usually classified into declarative memory and procedural memory, which are stored verbally, and declarative memory is classified into episode memory and semantic memory.
  • Memory of the result of repeated universalization in the present invention corresponds to semantic memory.
  • the device of the present invention interpolates and reconstructs the missing part of the input signal or memory in the same way as the function of the cerebral neocortex by comparing with the memory associated with the associative group. Obviously, it can be interpolated in the same way in the time axis direction and predict what will happen in the near future. For example, a part of the face of a specific person can be seen, and the presence of a universal cell for the face can be complemented and recognized.
  • the auditory recognition system can also be completed in a similar format to the visual system, taking into account frequency separation by the cochlea angle
  • image recognition may be performed without using memory similar to perceptron and cog-tron.
  • a conventional computer or microcomputer may be used for the part corresponding to the association area of the cerebrum. However, it is better to avoid entering directly between the recognition system and the storage system so that parallel processing is not interrupted.
  • the semiconductor device of the present invention includes a second component discharge cell composed of a first component and a second component, and a solid electrolyte region adjacent to the second component discharge cell. Two-component The second component supplied from the component discharge cell moves in the solid electrolyte region to form a wiring.
  • the first component is, for example, an insulator or a semiconductor
  • the second component is, for example, a metal ion
  • the solid electrolyte is Cu S or Ag S.
  • the crystallization region of the phase change memory connected only by the ion wiring is used as the wiring.
  • the wiring is not cut and the current is less plastic than the ion wiring, and the wiring is not cut.
  • a semiconductor device is defined as a device that uses a semiconductor at least in part. Therefore, it is possible that most is formed from an organic material, and most is formed from an insulator. Ideally, the entire system, including the detection system and storage system, can be made into a single-chip LSI, but it can be divided into multiple chips, or a part of it can be a circuit on a rigid or flexible printed circuit board. Silicon substrates and flexible printed circuit boards may be stacked alternately. In this case, the through electrode is not formed on at least one of the substrates. I like it! / It is preferable to provide a capacitor on the printed circuit board side because it is difficult to form with a silicon substrate.
  • the rule of branching of the output of the cell corresponding to the nerve cell is different from that of the conventional -Ural net, and the branch is positively performed for each new input and new processing.
  • the cell on the output side is shared only for the purpose of the universal recognition process for logical processing, as in the conventional -Uralnet device. Therefore, there is no need to optimize the connection function by learning.
  • the active branching that does not share the output side cell is possible because a connection is newly created and a connection that is not used can be canceled. Frequent memory references in addition to such aggressive bifurcations promote the formation of extremely complex and seemingly irregular networks similar to the cerebral neocortex, resulting in a complex system.
  • the scope of the present invention includes such hardware devices as well as software or hardware or software / hardware simulators if they can be simulated almost completely.
  • the semiconductor device of the present invention learns and memorizes while increasing the number of wirings or partially disappears, and by comparing with memory, for example, visually. On the other hand, it also has the ability to learn, predict and complement with high efficiency by using inputs from different systems such as hearing. This makes it possible to perform high-level intelligent work at high speed autonomously with creativity without external force programming.
  • the overall configuration of the device of the present invention has a six-layer structure similar to that of the cerebral neocortex as shown in FIG. 12, and a four-layer hierarchical structure as shown in FIG.
  • the structure is divided into columnar structures.
  • the layer where axonal branching occurs such as the fourth layer, is composed of 10 layers shown in FIG. 1 or 3 layers of cells shown in FIG.
  • the above four-level hierarchical structure is configured by arranging the six-layer structure in Fig. 12 in multiple in-plane directions. Has been.
  • the multilayer structural force shown in FIG. 1 or FIG. 2 is formed on the upper layer of the device shown in FIG. 10 or on the same substrate.
  • Figure 10 shows an example of the actual device structure on a silicon wafer. Transistors and the like are formed on the silicon wafer. However, it is not essential to use a silicon wafer, and other substrates such as glass may be used.
  • the structure of the branch connection wiring shown in FIG. 1 and FIG. 2 is between a large number of Ta 0 oxide microcrystals.
  • the metal element is packed with metal elements, and its resistance is low enough to be called an electrode.
  • an electrode As shown in the plan view in Fig. 17, there are many inputs (around 5 to 10) that are arranged at approximately equal distances around the output branch wiring (corresponding to the branching of neurons and axons) An ion conduction path (equivalent to a synaptic connection between nerve cells) is formed between the two.
  • Ta 0 As shown in the plan view in Fig. 17, there are many inputs (around 5 to 10) that are arranged at approximately equal distances around the output branch wiring (corresponding to the branching of neurons and axons) An ion conduction path (equivalent to a synaptic connection between nerve cells) is formed between the two.
  • a semiconductor such as ZnO or ZnS may be used.
  • One layer of the cerebral neocortex corresponds to the 10-layer structure shown in FIG. 1 or the 3-layer structure shown in FIG.
  • the ion conduction path has almost the same probability with respect to all the branched wirings that pass upward in the figure in the same columnar structure of the layer corresponding to the next cerebral neocortex. It is preferred that it be formed. If this is difficult due to the formation process of the branch wiring connection, the distance between the branch wirings may be limited by narrowing the columnar structure. If the columnar structure is made narrower and the number of branch connection wires in the columnar structure is reduced, the contents that can be recognized and memorized become simple, but the basic functions remain unchanged.
  • FIGS. 1 and 2 show examples of structures in which ion conduction paths are formed with almost the same probability even if the columnar structure is thick. Solid electrolyte layers and insulating layers are formed alternately, and each line of the branch wiring is formed by vertically passing through them.
  • An example of a solid electrolyte layer is Cu S. Cu S
  • a layer of the material may be used.
  • the solid electrolyte layer is formed so as to have a high resistance when no ion conductive path is formed in the layer.
  • Branch wiring has high conductivity.
  • Cu—Ta— with low oxygen content which is composed of copper (Cu), tantalum (Ta), and oxygen. It is an O film, and creates a conductive path in itself and in the solid electrolyte by Cu or Ta ion concentration.
  • Cu and Ta may be replaced with other metal elements and metalloid elements capable of ionization.
  • the lower branch wiring changes the relative position to the upper branch wiring for each layer of the solid electrolyte layer, and each is connected by in-plane wiring.
  • the distribution wiring of the upper cell is formed by vertically penetrating multiple layers of the solid electrolyte layer.
  • the ion conductive path is formed in the solid electrolyte layer between the lower branch wiring and the plurality of upper branch wirings.
  • the ion conductive path may be formed in the in-plane direction of the solid electrolyte layer, or may be formed in the up / down direction or the diagonally up / down direction, depending on whether the end of at least one of the branch wirings is deep in the solid electrolyte layer. If it is formed in-plane, it is also effective to induce a ionic conduction path by providing radial wiring to the branch wiring force branch wiring at the interface between the solid electrolyte layer and the insulating layer. There is also a part where guidance is performed far outside the columnar structure.
  • Such a structure is rotated 90 degrees with respect to the silicon wafer surface, branch wirings are formed in a horizontal plane (wafer surface or substrate surface direction), and the ionic conduction paths are all changed in angle in the plane, Alternatively, a part may be formed in-plane and the other may be formed at an angle. These layers are layered to form a structure that lays the cerebral neocortex on its side. When one conductive path is formed, the branch wiring is short-circuited in a DC manner, so that it is not difficult to form a conductive path between other branch wirings. A thin insulating layer may be formed between them. There may be an insulating layer at the interface of the metal electrodes connecting the horizontal direction in the figure.
  • the surface of the branch wiring pillar is substantially made of an oxide or nitride, and a metal element that conducts excessive ions more than the inside may be added.
  • a silicon oxide film 2 (not shown) of about 10 nm is first formed on a semiconductor substrate 1 by a CVD (Chemical Vapor Deposition) method or a thermal oxidation method.
  • a silicon nitride film 3 (not shown) is formed on the silicon oxide film 2 by a CVD method.
  • resist 4 (not shown)
  • the resist 4 is patterned using a lithography technique. The portion where the resist 4 remains is patterned so that an active region on the silicon substrate is formed, and the portion where the resist 4 is removed is formed so as to form a trench for element isolation.
  • the silicon nitride film 3, the silicon oxide film 2, and the silicon substrate 1 are etched in this order by dry etching using the resist 4 as a mask to form element isolation grooves 5 (not shown) in the silicon substrate 1. .
  • a silicon oxynitride film 6 (element isolation film) is deposited by a CVD method so that the groove 5 is filled.
  • CMP method chemical mechanical polishing method
  • the silicon nitride film 3 is removed by wet etching or dry etching to expose the silicon oxide film 2 on the active region of the semiconductor substrate 1.
  • a p-type (first conductivity type) well 10 is formed by boron ion implantation, and an n-type well 11 is formed by phosphorus ion implantation.
  • a resist pattern is formed on the semiconductor substrate 1 and used as a mask to selectively form a well 10
  • the first gate insulating film 21 is removed from the semiconductor substrate by, eg, thermal oxidation. Form on one.
  • the first gate insulating film is formed on the entire active region on the semiconductor substrate 1.
  • a polysilicon film 31 to be a first gate is deposited by a CVD method.
  • Polysilicon 31 can be deposited with P-type impurities and N-type impurities, but it can also be doped with N-type or P-type impurities by ion implantation after deposition without impurities. it can.
  • doping impurities by ion implantation polysilicon 31 on the N-type well 11 is doped with P-type impurities, and polysilicon 31 on the P-type shell 10 is doped with N-type impurities. Change the conductivity type and impurity concentration depending on the location. Is possible.
  • polysilicon 31 was patterned by lithograph and dry etching techniques.
  • a P-type low-concentration diffusion layer (LDD) 41 and an N-type LDD 42 were formed by ion implantation.
  • LDD low-concentration diffusion layer
  • N-type LDD 42 were formed by ion implantation.
  • the silicon oxide film 32 was deposited thinly, a part of the silicon oxide film 32 was removed by etch back, and a silicon oxide film sidewall 32 a was formed in the pattern of the polysilicon 31.
  • a P-type high concentration diffusion layer 43 and an N-type high concentration diffusion layer 44 were formed by ion implantation.
  • ion implantation For example, after depositing Conoret (Co) 45 by sputtering, annealing is performed at about 1000 ° C., and cobalt silicide 46 is formed on polysilicon 31, P-type high-concentration diffusion layer 43, and N-type high-concentration diffusion layer 44. did.
  • Co on the silicon oxide film 6 for element isolation was selectively removed on the side wall 34a that was not silicided.
  • the gate 31, the P-type high concentration diffusion layer 43, the N-type high concentration diffusion layer 44, and the wells 10 and 11 are reached.
  • Contact holes were formed.
  • An oscillation circuit, a logic circuit, and the like were formed by forming a metal wiring for connecting the formed NMOS and PMOS.
  • an input / output terminal 50 (not shown) made of metal was formed together to be connected to a multi-layer branch wiring capable of ion connection which will be formed later in the upper layer.
  • the solid electrolyte layer 201 was formed by a sputtering method.
  • the contact hole 301 was filled with a porous oxide film 401 containing copper (Cu) ions.
  • the porous oxide film 401 containing Cu ions on the solid electrolyte 201 was removed by etchback or CMP, and left only in the contact hole 301.
  • tungsten 501 was deposited by, for example, sputtering, and patterned by lithograph and dry etching techniques. At this time, the tungsten pattern is formed so as to cover all the contact holes 301 or a part of the contact holes 301.
  • the solid electrolyte layer 202 was formed by sputtering.
  • a contact hole 302 reaching the tungsten pattern 501 and a contact hole 302a formed in the space portion of the tungsten pattern 501 but not reaching the tungsten pattern were formed.
  • contact The holes 302 and 302a were filled with a porous oxide film 402 containing Cu ions.
  • the porous oxide film 402 containing Cu ions on the solid electrolyte 202 was removed by etch-back or CMP, and left only in the tans 302 and 302a.
  • the solid electrolyte layer 203 was formed by sputtering.
  • contact holes 303 reaching the tungsten patterns 501 and 502, and contact holes 303a formed in the space portions of the tungsten patterns 501 and 502 and not reaching the tungsten pattern were formed.
  • the contact holes 303 and 303a were filled with a porous oxide film 403 containing Cu ions.
  • the porous oxide film 403 containing Cu ions on the solid electrolyte 203 was removed by etchback or CMP, and left only in the contact holes 303 and 303a.
  • three layers 201, 202, and 203 are formed as the solid electrolyte layer, but it is also possible to form a structure of 10 layers or more by repeating the same process.
  • tungsten 504 was deposited by sputtering and patterned by lithographic and dry etching techniques. As a result, the porous oxide film 403 containing Cu ions remaining in the holes 303 and 303a was wired to complete the device.
  • the multi-layer branch wiring that can be ion-connected is configured so that each part is in contact in a plane parallel to the wafer. Also good.
  • the cell circuit as a circuit that is more preferable than the power described for the ring oscillator, there are an addition / subtraction for combining the operation similar to that of a nerve cell, and a combination of an integration circuit and a comparator circuit.
  • the integration circuit various known methods using an operational amplifier are desirable, but in order to reduce the circuit scale, a simple circuit that accumulates charges in a capacitor as shown in FIG. 5 may be used. A switch that discharges the capacitor by short-circuiting it with an analog switch circuit, etc. is provided. The charge is discharged in synchronization with the clock signal, and recharged (integrated) in response to new information. Since the required integration accuracy differs depending on the role of the cell, these may be used accordingly.
  • the comparator circuit uses a generally known operational amplifier. Also good. For example, if the input voltage is higher than the comparator level given as a voltage, the output voltage is not output, and if it is lower, the output voltage is output. If the comparator level is changed in pulses, the output can be changed to pulses. If the comparator level is given to the other terminal, the relationship between output and non-output can be reversed.
  • a simple known circuit that has a comparator function and does not use an operational amplifier circuit may be used. Those operating only with positive power supply voltage are particularly preferred. It is more preferable to have a threshold value and have an analog property that the output changes depending on the addition or subtraction or integration value above the threshold value.
  • the comparator circuit saturates the output and becomes a constant value when the amplification degree of the amplifier is large. However, if the amplification degree is reduced by a resistor or the like, the comparator circuit can have analog characteristics in which the voltage changes according to the input voltage. . When the output of the comparator is output, the integrated analog value on the input side may be output as it is. The comparator expresses the excitatory and inhibitory synapses cancel each other. Using a comparator greatly simplifies the logic circuit configuration. This is because the logic circuit of IF to THEN can be easily determined for matching and branching according to cell output conditions.
  • a plurality of parallel transfer systems may be configured, and different values from the memory may be given to the comparator level of each cell at the branching point.
  • the configuration is simple and accurate branching is possible. More complicated branching and direction-specific branching are possible, and auxiliary lines corresponding to each possible direction (for example, four directions, up, down, left, and right) are formed, and depending on the comparator level, passage is limited to the right direction, for example. do it.
  • the aggressive branching that does not share the output side cell is possible because a connection is newly generated and an unused connection can be eliminated.
  • the cell with the input line at the center, the cell arranged around it, and the cell arranged in the other layer in Fig. 1 are not connected.
  • a new ion wiring is formed with an equal probability, so that aggressive branching occurs.
  • the excitement state state with voltage output
  • the comparator level can be easily transmitted and shut off by setting the comparator level. Therefore, it is possible to select whether to transmit the excited state to both branches at the branch point or to transmit the excited state only to the newly formed person.
  • the cell circuits that output pulses are sequentially transferred.
  • the ionic connections connected to the waveform check terminals are shown as shaded lines. The ion connection is in the position before the output line splits with the force cell force that seems to be in the cell.
  • no voltage is generated in the next integration circuit, so that no pulse is generated in the next cell circuit or dummy cell circuit.
  • the pulse is not output while giving the maximum continuous comparison level to the cell circuit, so if there are two or more cells to be pulsed in succession, the nors will be generated. If the time constant during which the voltage of the addition / subtraction or integration circuit drops is reduced, it is possible to omit the dummy cells that exist every other part only for the purpose of transfer.
  • the cell circuit has an integration circuit and a self-oscillation circuit, and generates a pulse voltage.
  • An example of a self-oscillation circuit is one in which an operational amplifier is connected in series and a feedback loop is provided. [0062] As described above, by using a cell that outputs an analog voltage similar to a nerve cell, it is possible to detect changes in video and audio from the outside world in real time.
  • two vertical holes should be placed close to each other in parallel and one for the feedback loop.
  • the ionic conduction path of the feedback loop may be shared with the conduction path of the path facing from the lower layer to the upper layer.
  • Figure 3 shows a conceptual diagram for the visual system.
  • Memory also plays an important role in image recognition.
  • the length of the memory time series is about 1 to 2 minutes, similar to humans.
  • the cell power for recognizing triangles with different shapes is also sent to the upper layer as a signal and a connection signal for associating, and many shapes of triangle signals are read associatively at the upper layer when reading. Connected to.
  • the representative cell of these associated groups is the universal cell, which is the recognition of the generalized triangle, regardless of the shape.
  • the area surrounded by a large square near the center in Fig. 3 is the cognitive / thinking area.
  • This software flowchart as shown in Figs.
  • One output of the decision cell is inverted through the NOT cell.
  • the storage index is divided by a line, which indicates individual storage.
  • the memory index is a moving picture or audio storage system, like the heading screen of a DVD recorder, where the first still picture of the moving picture is extracted for search and arranged in the same way as a time-series signal. .
  • the device In the early stages when the device has only a few or very few memories stored, it contains regular repeating signals of various periods. This corresponds to the known tendency of the cerebral neocortex to look for regularity.
  • the output to the upper right is output to the upper layer through the upper layer of the cerebral neocortex. It corresponds.
  • the comparison circuit outputs a relatively high frequency pulse or high voltage when the pulse train from the storage system matches the pulse train of the input (incoming) information.
  • the signals on the storage system side are compared while being rotated and sent like an endless tape.
  • the time series signal input to a number of adjacent columnar structures is stored in the visual system for each sensor of the input 2D sensor.
  • the rotation is branched in the time axis direction. Rotate in the direction across each line, that is, in the spatial direction. Therefore, regularity such as triangles in the field of view can be compared.
  • the rotation may be performed over the entire field of view, but the field of view may be divided into, for example, four parts and rotated within each region.
  • Match determination is made if there is a match greater than or equal to a predetermined length in the spatial and temporal directions. If the above-mentioned predetermined length is shortened, there is a possibility that a match is determined although it does not actually match. If it is too long, it will be difficult to detect a match. Therefore, test several times to determine the optimum length.
  • the matching part is not only sent in the cell direction including the area slightly outside, but also transferred to the storage system and stored as it is. From this information, we can finally obtain universal recognition that associates many figures with associative groups. In other words, this is important for the progress of universalization, as will be described later.
  • the first layer may have the same format.
  • the signal from the two-dimensional photosensor is first processed and enters the next layered area as a parallel signal from the lower right of the figure.
  • This layered region may be the fourth layer of the next layer.
  • the layered area corresponds to the 6-layer structure of the cerebral neocortex.
  • the primary processing is, as is well known in the case of the visual system, so that one nerve cell is excited for a short segment of a specific angle of a part of the visual field, so that several retinal ganglia This refers to AND-logic processing of the pulse signal of the cell force by the visual cortex simple cells.
  • the device of the present invention may have the same 6-layer structure as the cerebral neocortex, but it may have a smaller or larger number of layers.
  • the associated image group is, for example, a group of triangles having different shapes and sizes, and is stored and associated every time a part of the image being viewed is determined to be a triangle.
  • These associated memories are not always stored close together. However, each time it is repeatedly read and newly stored, the one with the closest storage storage location is advantageous for reading, so the memory by the ion wiring is strengthened, and the remote one has fewer opportunities for reading and weakens the wiring. Such wiring plasticity causes the associated memories to be stored in close proximity. What is read out as a representative of the image group is an equilateral triangle or the first triangle seen.
  • the angle at which the two-dimensional photosensor array is directed is changed. If it is known that the cut out figure is a triangle, a triangle image group is extracted and compared, and the matching power with the stored figure is recognized. If there is no match with the stored triangle, it is added to the image group and the difference from the nearest triangle is also stored. For other events than images, universal recognition is formed in a similar way. In addition, triangles, letters, and triangles are stored in association with each other.
  • the output voltage force is measured by measuring the amount of the triangular portion displayed in white on a black background that occupies a wide range in the field of view in the circular range corresponding to the clear vision range.
  • a part of the flowchart of the method of examining the number of squares by moving to find the center of the circle where the output is maximum and detecting the direction in which the output of the force decreases slowly is shown.
  • the device of the present invention also branches from one cell to many graphic cells. This branch is intended to cut out a pixel group corresponding to a graphic, and has an analog value. For example, since the resistance value of the ion wiring is stored in the memory, the connection coefficient of each connection is not important. This is different from conventional neural network devices.
  • a voltage or pulse voltage is sent back in the direction opposite to the incoming signal. Since there is a diode so that the returned voltage or pulse voltage does not return to the output side of the lower layer, it goes in the direction of the figure recognition cell in the upper right in Fig. 3. As a result, an ion conductive path (ion wiring) is formed in the path connecting the line and the figure recognition cell. In other words, only five consecutive matching lines are connected to the figure recognition cell.
  • the image recognition cell has many forces, one by one, and can receive voltage or pulse voltage one by one.
  • the electric charge of the capacitor is accumulated for a certain period of time when the above switch is opened, and the voltage is given to the output circuit using the operational amplifier.
  • the voltage output or oscillation starts when the integrated power of the input from multiple wires exceeds a certain threshold, and the output voltage and oscillation frequency change slightly when the power increases, so it has analog characteristics. It is a kind of AND logic circuit.
  • the generated output voltage is applied to the next solid electrolyte layer to form a conductive path.
  • Figure 8 shows a schematic diagram of parallel transfer of signals to the memory system.
  • One line here corresponds to one line in Figs. 6 and 7, and one line of stored information, for example, a still image, is sent in many lines in parallel.
  • the force is increased by the required time or parallelism since they are sent from multiple columnar structures.
  • the range delimited by a short line segment above the line represents an individual cell circuit. Each cell circuit is a transfer dummy. Transfer is performed as described above for rotation of stored signals.
  • the dummy cell circuit When using a comparator or similar circuit, if a voltage or pulse voltage is applied to the cell circuit and a certain comparator level below the peak of the output voltage of the previous cell is applied to the next dummy cell circuit, the dummy cell circuit will Or outputs a Norse voltage.
  • a switch circuit for switching the location where the memory is stopped in response to the clock.
  • this switch can be realized by giving a comparator level to each branched cell and setting the value so that a signal can pass only by the comparator level of one cell. Since the maximum length of time for one continuous memory of human beings is several minutes, as long as a pulse or voltage is received, time switching corresponding to several minutes can be continued. This distributed place corresponds to the hippocampus in the brain. In the hippocampus, the oscillation pattern is preserved.
  • Each memory location in the hippocampus also has a transfer path, and once the memory is read out, it is again addressed to the cerebral neocortex, this time the temporal lobe. Forwarded to the appropriate location.
  • Each cell circuit and dummy cell circuit has a loop circuit as shown in the figure, and an ion wiring is provided. If there are multiple calls, the ion wiring corresponding to the cell that is oscillating or outputting voltage is strengthened, and information is stored for a long time as a pattern of wiring strength.
  • FIGS. 15A to 15F The experimental system for the four arithmetic operations is shown in FIGS. 15A to 15F.
  • FIG. 15F is a principle diagram showing the arrangement so that it is easy to use.
  • the number and operation symbol can be judged by limiting the 2D photosensor array to 15 pixels of 3 X 5 and presenting only the characters and operation symbols according to the position of the sensor array. I did it.
  • FIG. 18 shows a calculation flowchart of the carry portion of the calculation.
  • the determination part written as “match” corresponds to the circuit corresponding to the circuit that determines that the values match by the determination that the input to the cell is greater than or equal to the value of the input to the comparator in FIG. It is abbreviated.
  • the calculation proceeds while ANDing the memory by setting the comparator level of the sequence that adds the carry value and the input value and the memory of the addition. AND is an operation that is set so that the cell is excited and outputs only when there is input from two or more of the input branches almost simultaneously.
  • the circuit in FIG. 15F corresponds to the flowchart, but omits the determination for the multiplication / division first and the addition / subtraction coincidence determination.
  • the return point of the loop in the flowchart is searched when teaching a calculation method, for example, by voice or text.
  • a calculation method for example, by voice or text.
  • Fig. 15F shows a system that performs preliminary judgment of numbers using only the upper five pixels of the 15 pixels of character input.
  • the ability to make such predictive decisions using associative connections is the ability to recognize a flashlight or camera in a short time even if a line drawing of only a part of the flashlight or camera outline is presented, for example. Will be obtained.
  • Fig. 15A shows the regular arrangement of cells and connections.
  • the three columns on the left are the time-series signals corresponding to the sequential delivery of time-series signals between different columnar structures of the cerebral neocortex. Indicates delivery.
  • FIG. 15B shows an example of a combination of an integration circuit and a comparator circuit using a capacitor, and an integration circuit and a comparator circuit using an operational amplifier, as an example of a cell circuit.
  • the negative voltage VO may be the same as the positive voltage + V, but it may be slightly different.
  • Vth is a reference voltage for comparison.
  • the circuit in the previous stage is not necessarily an integration circuit, and it is not necessary to add multiple inputs of voltage or current.
  • a subtracting circuit may be used. Compared to the integration circuit, there is an advantage that a capacitor with a large capacity is not required.
  • FIG. 15C shows a process of switching a part of the cell circuit, which is all the same at first, to AND, OR, and NOT as appropriate by switching the connection to the power supply of positive and negative voltages as described above. ing.
  • FIG. 15D is a diagram showing an initial stage of connection by ion wiring of a transfer path to a storage system for numerical values of cell power of a logical system by a connection signal from a control memory.
  • FIG. 15E is a diagram showing when the connection is completed.
  • Fig. 15F shows the layout changed for better understanding. If almost the same comparator level is given to two branched comparators, and the output of one comparator is inverted by NOT circuit and added, the output is obtained only when the input signal is equal to the comparator level. This makes it possible to determine the match.
  • the connection pattern by the ion wiring is transferred from the control memory as a high and low voltage pattern in a part of the area in FIG. 15, and stopped to form the ion wiring at a location corresponding to High. It is the figure which showed the method to do.
  • the transfer path may be in one direction, but as shown in the center of Fig.
  • control memory It is possible to proceed with the hardware implementation of the logic while repeatedly confirming the correspondence between the memory representing the flow chart and the logic circuit to be formed. It can be made into hardware even if it is not given by the time of completion.
  • the calculation rule is given by a logical description that can be written in the visual system power flow chart. An example is shown in the figure.
  • the logic system learns the conversion table by trial and error by using the power (preliminarily) given to the conversion table for converting the flowchart into the logic circuit. Therefore, if the converted signal is transferred like the transfer of memory and the ion wiring is connected, the logical thinking circuit system is completed. This flowchart is actually executed by extracting the letters and voices that were learned (educated) at each step from the memory.
  • the clock time for learning and ion wiring is preferably more than 1 / 1,000,000 times less than 1 million so that the period of 3-4 years old from a newborn can be shortened. More preferably, it is 1 / 1,000,000 or less.
  • the length and wiring are formed with the same considerations as for coaxial cables, so that pulse propagation can be performed without problems.
  • Fig. 9 Generalized memory and logic ⁇ Control ⁇ Prediction ⁇
  • Fig. 9 many lines in parallel representing image pixels and audio frequency components are represented by a single line. In some cases, the cell at the end of the wiring is omitted.
  • the large square in Fig. 9 is the same cognitive 'thinking area as in the large square in Fig. 3, but it shows the part that moves to the stage of thinking after the universalization of video and audio.
  • the generalized storage area moves to the accumulation operation read-out operation according to the command from the judgment logic circuit area.
  • the read universal video is, for example, an image of a figure such as a triangle, an image of a device such as a camera, a computer, etc., and the type that was first memorized or most viewed is first played back. For example, if you see an incomplete picture of only a part of the outline, if the first type of missing part prediction does not match, many of the associated types, for example, the camera shape, are associated sequentially. Played.
  • the definition of associatively replayed groups is usually performed by keywords. Characteristic parts such as figures also act as a kind of keyword.
  • live video, generalized video and audio are read out as parallel analog signals, and thus are stimulated in the same way as human thought. It is a device to think while. Therefore, it is possible to respond quickly to changes in the outside world that can be known from live video.
  • a two-dimensional optical sensor that captures live video is 10
  • the number of memories by wiring formation is also limited to the minimum, and others are parallel-serial conversion and reverse conversion to hard disk drives and flash memory arrays. Rei memorize. However, in this case as well, the association for association is indexed so that it can be made between any stored contents at any time after storage. Even if it is simplified in this way, for example, it is possible to recognize a mini board and a stone on it and execute a paddle and improve its skill by learning.
  • connection since the connection is plastic, creativity and recognition ability are enhanced. In other words, if the network forming the logical system is not used, the connection point will be broken. Since there is no addressing in the main part of the device of the present invention, when forming a new logic network, the rules to avoid the use of the already used cells because the resistance is low and the potential difference is difficult to be applied apply. Is done. However, it is misunderstood that the broken part is not used, and a mixed network is formed immediately, and unexpected logic and association are widely called, and if these are selected, creativity and self-supporting It becomes possible to make a decision. A wide range of associations can be achieved by universalizing the category of associations that the memory index plays. The universalization of this associative category is that when new input is memorized, color and gradation are reduced corresponding to plasticity, and those that match many parts as a category of association are grouped together.
  • a semiconductor device comprising:
  • a semiconductor device characterized in that a cell corresponding to a nerve cell outputs a voltage or a pulse voltage when an input exceeds a threshold value.
  • the output of the cell corresponding to the nerve cell and the input of the next layer or the next layer are almost the same conditions as when the output is branched and the input of at least most cells in the same columnar structure is branched.
  • a semiconductor device characterized by using a comparison with parallel processing memory for learning.
  • a semiconductor device characterized in that a pattern with and without a cell voltage output is transferred in parallel in a sequential manner.
  • a semiconductor device characterized in that the correctness of the input signal recognition is determined by comparing the input signal with the speech or character signal of a given compliment given at the initial stage of the development of the recognition system.
  • a semiconductor device characterized by having means for visually or graphically giving a feature point of a figure to be recognized when a recognition system is developed.
  • a semiconductor device characterized in that when comparing an input signal with a stored signal, the signal on the storage system side is compared while being rotated and sent not in the time axis direction but in the space axis direction like an endless tape. .
  • a semiconductor device characterized in that the portion where the input signal matches the stored signal and its periphery are not only sent to the recognition cell but also transferred to the storage system and stored.
  • a semiconductor device in which a dummy cell for transfer is provided between cells for transferring an input signal and a stored signal pattern.
  • a dummy cell for transfer is provided between each cell, and the loop circuit of the ring oscillator of the dummy cell adjacent to each cell in the transfer direction is switched. Connect the circuit, then disconnect the two ring oscillators before and after the two cells again, and then stop the oscillation if the back cell is oscillating. Not transfer the pattern to forward.
  • a dummy cell for transfer is provided between each cell, and the maximum comparator level is set in each cell, the cell adjacent to the cell in the transfer direction, and the dummy cell.
  • a semiconductor device characterized by transferring a pattern with and without voltage output in order by repeating an operation of alternately giving a comparator level that fluctuates in a pulse shape through a value or an intermediate value.
  • a semiconductor device characterized in that when an input signal or a stored signal pattern is transferred, a means for stopping the transfer at least temporarily by providing a branch path at the storage location is provided.
  • a cell corresponding to a figure or the like is formed from a portion that matches the memory and the input signal, but if there is a partial match, the entire memory is read as an associative process.
  • Semiconductor device Semiconductor device.
  • a semiconductor device comprising means for newly forming a readout path for performing associative processing by forming a conductive path.
  • a semiconductor device comprising means for forming a readout path for performing associative processing at any time after storage, not just during storage and storage.
  • a semiconductor device that reads out memory by regenerating a pattern with and without voltage output utilizing the fact that the resistance of the read trigger system varies depending on the pattern.
  • the missing part of the input signal is interpolated and recognized in full form, or it is interpolated in the same way in the time axis direction.
  • a semiconductor device having means for predicting and coping with what happens.
  • a semiconductor device characterized in that at least a part of logic of a logical thinking area is stored in a logical 'control' expectation 'prediction storage area. This part corresponds to the area controlled by a given program in a conventional computer.
  • a semiconductor device comprising means for allowing logic to be developed.
  • a semiconductor device characterized in that it is an artificial intelligence device that performs part of the storage with a conventional serial storage device and performs parallel-serial conversion and inverse conversion as necessary.
  • a threshold value is given to the logic logic of OR with analog characteristics, and only cells corresponding to pixels whose brightness or color index is higher than a predetermined intensity are cut out. Means, then turn the outline of this part, then turn one cell inside, V, and so on, operate the logic cell group corresponding to the algorithm to recognize the shape Means, figure
  • a means for allowing the signals of the three passing cells to enter the cell that detects the angle of the above line segment In the process of linear movement in the in-plane direction of characters and characters, a means for allowing the signals of the three passing cells to enter the cell that detects the angle of the above line segment.
  • a semiconductor device characterized by having means for determining the shape of a figure, etc., clarifying a group of corresponding figures, and extracting and comparing them to recognize an accurate shape.
  • a method of inputting information to a semiconductor device wherein a predetermined method is used to indicate in advance whether the data is stored in a control memory or other memory.
  • a semiconductor device characterized in that a comparator level given to a cell corresponding to a nerve cell is also transferred as information.
  • the present invention relates to a semiconductor device having memory and logic judgment ability and creativity close to those of humans.
  • an android robot a humanoid robot that acts independently, and an instantaneous sudden danger It can be applied to autonomous driving vehicles that can cope with this.
  • FIG. 1 is a cross-sectional view showing a device structure corresponding to an axonal branch and a saddle-like protrusion according to the present invention.
  • FIG. 2 is a cross-sectional view showing a device structure corresponding to an axonal branch and a saddle-like protrusion according to the present invention.
  • FIG. 3 is a schematic diagram showing an image recognition / storage system according to the present invention.
  • FIG. 4] (a) to (1) are schematic diagrams showing the principle of recognition and storage of a triangle in the present invention.
  • FIG. 5 is a circuit diagram corresponding to a nerve cell of the device shown in one embodiment of the present invention.
  • FIG. 6 (a) is a diagram showing a logical thinking system of a device shown in one embodiment of the present invention.
  • FIG. 7 is a composite diagram of inter-cell wiring of the present invention.
  • FIG. 8 is a diagram showing a storage / transfer system of the device of the present invention.
  • FIG. 9 is a block diagram of the recognition / thinking area of the device of the present invention.
  • FIG. 10 (a) is a cross-sectional view of a transistor used in the present invention.
  • B shows the inverter circuit configured using (a).
  • C shows a ring oscillator circuit configured using (b).
  • FIG. 11 is a schematic diagram of a configuration of a conventional perceptron.
  • FIG. 12 is a schematic diagram of a layer structure and a columnar structure in the present invention.
  • FIG. 13 is a schematic diagram of a hierarchical structure in the present invention.
  • FIG. 14 is a table showing the structure and operation of cerebral neocortical operation and semiconductor neocortical device.
  • FIG. 15A is a diagram showing a logic circuit system (initial state) of four arithmetic operations in the present invention.
  • FIG. 15B (a) and (b) are resistances in the logic circuit system of the four arithmetic operations in the present invention! /, Is a diagram showing a cell property set due to partial short-circuiting using capacitor ion wiring.
  • FIG. 15C is a diagram showing a cell property set in the logic circuit system of four arithmetic operations according to the present invention.
  • FIG. 15D is a diagram showing connection by ion wiring in the logic circuit system of four arithmetic operations in the present invention.
  • FIG. 15E is a diagram showing a logic circuit system (completion of connection) of four arithmetic operations in the present invention.
  • FIG. 15F is a diagram showing the principle of the four arithmetic operation systems in the present invention.
  • FIG. 16 is a diagram showing a method of forming a logic circuit with information transferred from the logical memory in the present invention.
  • FIG. 17 is a plan view of ion wiring between cells of the present invention.
  • FIG. 18 is a flowchart in Example 1.
  • FIG. 19 is a flowchart in Example 1.
  • FIG. 20 is a pulse timing chart of stored data transfer.
  • Interlayer insulation film 21 ... Gate oxide film, 31 ... Polysilicon, 46 ... Silicide, 32a ... Side wall insulation film, 11 ... Swell, 1 ... Semiconductor substrate, 6 ... ⁇ Element isolation insulating film, 10 to ⁇ type well, 41,42 ⁇ ⁇ ⁇ type low concentration diffusion layer, 43,44 ⁇ ⁇ ⁇ type high concentration diffusion layer,

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Abstract

L'invention concerne un dispositif semi-conducteur, en particulier, un dispositif à intelligence artificielle, caractérisé par une capacité d'apprentissage avancée en augmentant les circuits et les nœuds d'un système servant à reconnaître une entrée extérieure tout en les supprimant partiellement. La mémoire est réalisée par un motif de disposition des nœuds de circuits. L'augmentation ou la suppression de circuits et de nœuds permet d'assurer la formation d'un chemin conducteur réalisé par mobilité d'ions, par exemple, et son changement d'épaisseur. Le dispositif semi-conducteur comporte en outre au moins une zone servant à mémoriser les informations entrées comme une image ou un son sur une base de séries en temps réel, une zone de mémorisation d'informations logiques en séries temporelles, une autre zone dans laquelle sont transférées les informations, et une zone de traitement logique.
PCT/JP2006/316750 2006-08-25 2006-08-25 Dispositif semi-conducteur WO2008023437A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0793277A (ja) * 1993-09-24 1995-04-07 Nec Corp ニューラルネットワークを用いた半導体集積回路装置
JPH07141313A (ja) * 1993-11-18 1995-06-02 Fujitsu Ltd 神経回路素子
WO2006070693A1 (fr) * 2004-12-27 2006-07-06 Nec Corporation Element de commutation, procede d’entrainement d’element de commutation, procede de fabrication d’element de commutation, circuit integre logique reinscriptible et element de memoire

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0793277A (ja) * 1993-09-24 1995-04-07 Nec Corp ニューラルネットワークを用いた半導体集積回路装置
JPH07141313A (ja) * 1993-11-18 1995-06-02 Fujitsu Ltd 神経回路素子
WO2006070693A1 (fr) * 2004-12-27 2006-07-06 Nec Corporation Element de commutation, procede d’entrainement d’element de commutation, procede de fabrication d’element de commutation, circuit integre logique reinscriptible et element de memoire

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