WO2008020403B1 - Method for improving interface reactions at semiconductor surfaces - Google Patents

Method for improving interface reactions at semiconductor surfaces

Info

Publication number
WO2008020403B1
WO2008020403B1 PCT/IB2007/053240 IB2007053240W WO2008020403B1 WO 2008020403 B1 WO2008020403 B1 WO 2008020403B1 IB 2007053240 W IB2007053240 W IB 2007053240W WO 2008020403 B1 WO2008020403 B1 WO 2008020403B1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor wafer
semiconductor
deuterium
degrees celsius
passivation
Prior art date
Application number
PCT/IB2007/053240
Other languages
French (fr)
Other versions
WO2008020403A3 (en
WO2008020403A2 (en
Inventor
Zsolt Nenyei
Thomas Theiler
Georg Roters
Hans-Joachim Meyer
Original Assignee
Mattson Tech Inc
Zsolt Nenyei
Thomas Theiler
Georg Roters
Hans-Joachim Meyer
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mattson Tech Inc, Zsolt Nenyei, Thomas Theiler, Georg Roters, Hans-Joachim Meyer filed Critical Mattson Tech Inc
Publication of WO2008020403A2 publication Critical patent/WO2008020403A2/en
Publication of WO2008020403A3 publication Critical patent/WO2008020403A3/en
Publication of WO2008020403B1 publication Critical patent/WO2008020403B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C8/00—Solid state diffusion of only non-metal elements into metallic material surfaces; Chemical surface treatment of metallic material by reaction of the surface with a reactive gas, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals
    • C23C8/02—Pretreatment of the material to be coated
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C8/00—Solid state diffusion of only non-metal elements into metallic material surfaces; Chemical surface treatment of metallic material by reaction of the surface with a reactive gas, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals
    • C23C8/06—Solid state diffusion of only non-metal elements into metallic material surfaces; Chemical surface treatment of metallic material by reaction of the surface with a reactive gas, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals using gases
    • C23C8/08—Solid state diffusion of only non-metal elements into metallic material surfaces; Chemical surface treatment of metallic material by reaction of the surface with a reactive gas, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals using gases only one element being applied
    • C23C8/24—Nitriding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/3003—Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H01L21/02326—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen into a nitride layer, e.g. changing SiN to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
    • H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator

Abstract

The present invention describes a method for producing ultra-thin thermally stoichiometric or almost stoichiometric nitrides on semiconductor wafers. The method according to the invention includes the H+- or D+-passivation of the free semiconductor surface, followed by nitriding either in an RTP system, an oven or in plasma. Compounds containing deuterium are preferred in all of the method steps of the invention in order to passivate the interface layer between the silicon surface and the dielectric.

Claims

AMENDED CLAIMS (received by the International Bureau on 05 September2008 (05.09.2008))
1. A method for producing silicon nitride layers on semiconductor wafers, the method having the following steps: a) Passivation of a free silicon surface of a semiconductor wafer with deuterium or a mixture of deuterium and hydrogen; b) Introducing the semiconductor wafer in a thermal processing chamber; c) Removing oxidising substances from the immediate surroundings of the semiconductor wafer by flushing the processing chamber with nitrogen and/or argon and/or helium, and/or by pumping the processing chamber to a pressure of less than 1 mbar; d) Introducing at least one gas from the group of gases NH3, NH2D, NHD2, ND3 in the processing chamber; e) Heating the semiconductor wafer to a temperature of between at least 600 and 700 degrees Celsius; f) Thermal nitriding of the silicon surface of the semiconductor wafer with at least one gas from the group of gases NH3, NH2D, NHD2, ND3 at temperatures of between 600 degrees Celsius and 1200 degrees Celsius.
2. A method for producing silicon nitride layers on semiconductor wafers, the method having the following steps: a) Passivation of a free silicon surface of the semiconductor wafer with deuterium and/or a mixture of deuterium and hydrogen; b) Introducing the semiconductor in a plasma processing chamber; c) Removing oxidising substances from the immediate surroundings of the semiconductor wafer by flushing the processing chamber
17. The method according to any of the preceding claims, characterised in that a gas selected from the group of gases NH3, NH2D, NHD2, ND3 is introduced into the processing chamber up to a pre-determined partial pressure.
18. The method according to any of the preceding claims, characterised in that in step c) the wafer is heated to a temperature of max. 400 degrees Celsius.
19. The method according to any of the preceding claims, characterised in that nitriding in step f) is implemented up to a desired thickness of the silicon nitride layer.
20. A method for preparing a semiconductor wafer having a free semiconductor surface for a subsequent thermal treatment, characterised in that the free semiconductor surface is passivated with deuterium and/or with a mixture of deuterium and hydrogen at temperatures of below 100 degrees Celsius is held until the next processing step at a temperature which is at least 15 degrees higher than the temperature of the surrounding atmosphere to reduce particle and organics deposition.
21. The method according to claim 20, characterised in that the semiconductor wafer is a germanium wafer and the free semiconductor surface is a germanium surface.
22. The method according to claim 20, characterised in that the semiconductor wafer is a silicon wafer and the free semiconductor surface is a silicon surface.
24. The method according to any one of Claims 20 to 22, characterised in that the passivation is implemented wet-chemically.
25. The method according to any one of Claims 20 to 22, characterised in that the passivation is implemented using gas-chemical methods.
26. The method according to any one of Claims 20 to 25, characterised in that the deuterium concentration used for the passivation is greater than 1 percent.
27. The method according to Claim 26, characterised in that the deuterium concentration is greater than 10 percent.
28. The method according to Claim 27, characterised in that the deuterium concentration is greater than 30 percent
29. A method for thermally treating a passivated semiconductor wafer according to any of Claims 20 to 28, characterized in that the semiconductor wafer is heated to a temperature of greater than 300° C during the thermal treatment.
30. The method according to Claim 29, characterised in that the passivated semiconductor wafer is heated by halogen lamps, arc lamps, taser lamps and/or inductive means.
31. A method for producing nitride, oxy-nitride and/or oxide layers on semiconductor wafers, the method comprising the following steps: a) Passivating a free surface of a semiconductor wafer with deuterium and hydrogen; b) Surrounding the passivated semiconductor wafer with at least one gas from the group of gases consisting of NH3, NH2D, NHD2, ND3, O2, N2O, NO and O3; c) Heating the surface of the passivated semiconductor wafer wherein the semiconductor wafer is held for a predetermined period of time between 200 degrees Celsius and 500 degrees Celsius and is heated in a subsequent step to at least 500 degrees Celsius, in order to completely remove the passivation and to form at least one of the above layers, where the passivation is removed.
33. The method according to claim 31 , characterized in that in step c) a different layer to the one formed in the subsequent step is formed.
34. The method according to claim 33, characterized in that in step c) the semiconductor wafer is surrounded by a different gas to the gas which surrounds the semiconductor wafer in the subsequent step.
35. The method according to any one of claims 31 to 35, characterized in that in step c) the surface of the passivated semiconductor wafer is heated in a plasma chamber.
36. The method according to claim 35, wherein nitriding of the semiconductor wafer is occurs in the plasma chamber fat electric voltages of less than 500 volts in at feast one gas selected from the group of gases consisting of NH3, NH2D, NHD2 and ND3.
37. The method according to any one of claims 31 to 36, wherein the semiconductor wafer is a silicon wafer,
38. The method according to any one of claims 31 to 35, characterized in that prior to step b) of the method, the semiconductor wafer is introduced into a thermal processing chamber.
PCT/IB2007/053240 2006-08-16 2007-08-14 Method for improving interface reactions at semiconductor surfaces WO2008020403A2 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
DE102006038076.2 2006-08-16
DE102006038076 2006-08-16
DE102007023258.8 2007-05-18
DE102007023258 2007-05-18
DE102007035990.1 2007-08-01
DE102007035990A DE102007035990A1 (en) 2006-08-16 2007-08-01 Method for improving interface reactions on semiconductor surfaces

Publications (3)

Publication Number Publication Date
WO2008020403A2 WO2008020403A2 (en) 2008-02-21
WO2008020403A3 WO2008020403A3 (en) 2008-10-30
WO2008020403B1 true WO2008020403B1 (en) 2008-11-20

Family

ID=38955079

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2007/053240 WO2008020403A2 (en) 2006-08-16 2007-08-14 Method for improving interface reactions at semiconductor surfaces

Country Status (2)

Country Link
DE (1) DE102007035990A1 (en)
WO (1) WO2008020403A2 (en)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6013553A (en) * 1997-07-24 2000-01-11 Texas Instruments Incorporated Zirconium and/or hafnium oxynitride gate dielectric
US6797644B2 (en) * 2000-08-01 2004-09-28 Texas Instruments Incorporated Method to reduce charge interface traps and channel hot carrier degradation
US6642156B2 (en) * 2001-08-01 2003-11-04 International Business Machines Corporation Method for forming heavy nitrogen-doped ultra thin oxynitride gate dielectrics
JP2003264190A (en) * 2002-03-08 2003-09-19 Toshiba Corp Semiconductor device and manufacturing method
US6670241B1 (en) * 2002-04-22 2003-12-30 Advanced Micro Devices, Inc. Semiconductor memory with deuterated materials
US6825538B2 (en) * 2002-11-20 2004-11-30 Agere Systems Inc. Semiconductor device using an insulating layer having a seed layer
KR100482372B1 (en) * 2002-12-03 2005-04-14 삼성전자주식회사 Method of forming gate oxide layer in semiconductor devices
JP4073393B2 (en) * 2003-12-02 2008-04-09 株式会社東芝 Manufacturing method of semiconductor device

Also Published As

Publication number Publication date
WO2008020403A3 (en) 2008-10-30
DE102007035990A1 (en) 2008-02-21
WO2008020403A2 (en) 2008-02-21

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