WO2008016737A3 - Sram having variable power supply and method therefor - Google Patents

Sram having variable power supply and method therefor Download PDF

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Publication number
WO2008016737A3
WO2008016737A3 PCT/US2007/068677 US2007068677W WO2008016737A3 WO 2008016737 A3 WO2008016737 A3 WO 2008016737A3 US 2007068677 W US2007068677 W US 2007068677W WO 2008016737 A3 WO2008016737 A3 WO 2008016737A3
Authority
WO
WIPO (PCT)
Prior art keywords
power supply
line
memory cells
sram
method therefor
Prior art date
Application number
PCT/US2007/068677
Other languages
French (fr)
Other versions
WO2008016737A2 (en
Inventor
Olga R Lu
Lawrence F Childs
Craig D Gunderson
Original Assignee
Freescale Semiconductor Inc
Olga R Lu
Lawrence F Childs
Craig D Gunderson
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=38653438&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO2008016737(A3) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Freescale Semiconductor Inc, Olga R Lu, Lawrence F Childs, Craig D Gunderson filed Critical Freescale Semiconductor Inc
Priority to JP2009522905A priority Critical patent/JP5179496B2/en
Priority to CN2007800281906A priority patent/CN101496107B/en
Publication of WO2008016737A2 publication Critical patent/WO2008016737A2/en
Publication of WO2008016737A3 publication Critical patent/WO2008016737A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A memory circuit (14, 16, 18, 20) has a memory array (14) with a first line of memory cells (13, 66), a second line of memory cells (15, 68), a first power supply terminal, a first capacitance structure (17, 70), a first power supply line (35, 67) coupled to the first line of memory cells (13, 66); and a second power supply line (39, 69) coupled to the second line of memory cells (15, 68). For the case where the second line of memory cells (15, 68) is selected for writing, a switching circuit (44, 52, 56, 94, 96, 98) couples the power supply terminal to the first power supply line (35, 67), decouples the first power supply line (35, 67) from the second line of memory cells (15, 68), and couples the second power supply line (39, 69) to the first capacitance structure (17, 71). The result is a reduction in power supply voltage to the selected line of memory cells by charge sharing with the capacitance structure (17, 70). This provides more margin in the write operation on a cell in the selected line of memory cells.
PCT/US2007/068677 2006-07-31 2007-05-10 Sram having variable power supply and method therefor WO2008016737A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009522905A JP5179496B2 (en) 2006-07-31 2007-05-10 MEMORY CIRCUIT AND MEMORY WRITE METHOD
CN2007800281906A CN101496107B (en) 2006-07-31 2007-05-10 Sram having variable power supply and method therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/461,200 2006-07-31
US11/461,200 US7292485B1 (en) 2006-07-31 2006-07-31 SRAM having variable power supply and method therefor

Publications (2)

Publication Number Publication Date
WO2008016737A2 WO2008016737A2 (en) 2008-02-07
WO2008016737A3 true WO2008016737A3 (en) 2008-07-17

Family

ID=38653438

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/068677 WO2008016737A2 (en) 2006-07-31 2007-05-10 Sram having variable power supply and method therefor

Country Status (5)

Country Link
US (1) US7292485B1 (en)
JP (1) JP5179496B2 (en)
CN (1) CN101496107B (en)
TW (1) TW200807417A (en)
WO (1) WO2008016737A2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8264896B2 (en) * 2008-07-31 2012-09-11 Freescale Semiconductor, Inc. Integrated circuit having an array supply voltage control circuit
KR20100028416A (en) * 2008-09-04 2010-03-12 삼성전자주식회사 Semiconductor memory device, method of operating the same
KR101505554B1 (en) * 2008-09-08 2015-03-25 삼성전자주식회사 Semiconductor Memory Device, Method of Operating the same
KR101446337B1 (en) * 2008-09-08 2014-10-02 삼성전자주식회사 Semiconductor Memory Device, Method of Operating the same
US8045402B2 (en) * 2009-06-29 2011-10-25 Arm Limited Assisting write operations to data storage cells
US20120120702A1 (en) * 2010-11-13 2012-05-17 Browning Christopher D Power saving technique in a content addressable memory during compare operations
US9005409B2 (en) 2011-04-14 2015-04-14 Tel Nexx, Inc. Electro chemical deposition and replenishment apparatus
US9017528B2 (en) 2011-04-14 2015-04-28 Tel Nexx, Inc. Electro chemical deposition and replenishment apparatus
US9303329B2 (en) 2013-11-11 2016-04-05 Tel Nexx, Inc. Electrochemical deposition apparatus with remote catholyte fluid management
WO2015171811A2 (en) * 2014-05-07 2015-11-12 Fong John Yit Sram memory cells with 1 to 10 bits of single ended, potential line combination, nonvolatile data
KR20180065073A (en) * 2016-12-06 2018-06-18 삼성전자주식회사 Sram device having uniform write characteristics
US10867646B2 (en) * 2018-03-28 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Bit line logic circuits and methods

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050128790A1 (en) * 2003-12-11 2005-06-16 Texas Instruments Incorporated Static random access memory device having reduced leakage current during active mode and a method of operating thereof
US6950354B1 (en) * 2004-09-06 2005-09-27 Fujitsu Limited Semiconductor memory
US20050285862A1 (en) * 2004-06-09 2005-12-29 Renesas Technology Corp. Semiconductor device and semiconductor signal processing apparatus

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4094008A (en) * 1976-06-18 1978-06-06 Ncr Corporation Alterable capacitor memory array
GB2259589A (en) * 1991-09-12 1993-03-17 Motorola Inc Self - timed random access memories
JP4198201B2 (en) * 1995-06-02 2008-12-17 株式会社ルネサステクノロジ Semiconductor device
JP4162076B2 (en) 2002-05-30 2008-10-08 株式会社ルネサステクノロジ Semiconductor memory device
JP3906166B2 (en) * 2003-02-25 2007-04-18 株式会社東芝 Semiconductor memory device
JP4053510B2 (en) 2004-03-23 2008-02-27 日本テキサス・インスツルメンツ株式会社 SRAM device
CN100483547C (en) * 2004-09-27 2009-04-29 国际商业机器公司 SRAM array with improved cell stability
JP4912016B2 (en) * 2005-05-23 2012-04-04 ルネサスエレクトロニクス株式会社 Semiconductor memory device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050128790A1 (en) * 2003-12-11 2005-06-16 Texas Instruments Incorporated Static random access memory device having reduced leakage current during active mode and a method of operating thereof
US20050285862A1 (en) * 2004-06-09 2005-12-29 Renesas Technology Corp. Semiconductor device and semiconductor signal processing apparatus
US6950354B1 (en) * 2004-09-06 2005-09-27 Fujitsu Limited Semiconductor memory

Also Published As

Publication number Publication date
US7292485B1 (en) 2007-11-06
TW200807417A (en) 2008-02-01
WO2008016737A2 (en) 2008-02-07
JP5179496B2 (en) 2013-04-10
CN101496107A (en) 2009-07-29
CN101496107B (en) 2012-06-13
JP2009545834A (en) 2009-12-24

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