WO2008001411A1

WO2008001411A1 - Process for producing semiconductor memory device

Info

Publication number: WO2008001411A1
Application number: PCT/JP2006/312594
Authority: WO
Inventors: Yuichi Matsui; Takahiro Morikawa; Motoyasu Terao; Norikatsu Takaura
Original assignee: Renesas Technology Corp.
Priority date: 2006-06-23
Filing date: 2006-06-23
Publication date: 2008-01-03
Also published as: TW200814382A; JPWO2008001411A1

Abstract

A memory layer of phase change memory consisting of a highly thermostable InGeSbTe film. This InGeSbTe film is formed by simultaneous sputtering of GeSbTe target (109a) of Ge2Sb2Te5 of stable composition and InTe target (109d) of In2Te3 of stable composition in sputtering chamber (101). Accordingly, aging change and local fluctuation of stoichiometric composition of the InGeSbTe film can be inhibited so that there can be obtained an InGeSbTe film ensuring high homogeneity of composition and crystal phase of crystal grains.

Description

Specification

Manufacturing method of semiconductor memory device

Technical field

TECHNICAL FIELD [0001] The present invention relates to a manufacturing technique of a semiconductor memory device, and more particularly to a technique effective when applied to the manufacture of a phase change memory using chalcogenide as a recording layer material.

Background art

[0002] Microcomputers for embedded devices (memory-embedded microcomputers) that incorporate a flash memory for storing programs and data are installed in information devices, home appliances, and in-vehicle devices. In recent years, as the functions of these devices have improved, the demand for higher performance of memory-embedded microcomputers has increased, and even for embedded flash memory, there has been a demand for improved rewrite resistance and further integration. Yes.

[0003] Also, in DRAM, which is a general-purpose memory, miniaturization of memory cells has been advanced in order to meet the demand for higher integration density. However, DRAM that stores information with the amount of charge stored in the capacitor has the problem that the storage capacity decreases if the capacitor area is reduced. In addition, if the dielectric material of the capacitor is thinned below a certain value, there is a problem that the leakage current increases. Previously, the capacitor could be formed in a deep trench to prevent the area from decreasing.However, if further miniaturization was promoted, the trench aspect ratio reached the limit of processing, and cutting-edge processing technology was developed. Even if you make full use of it, you will not be able to make a yield device.

In view of such a situation, recently, various new semiconductor memory elements have been proposed.

Typical examples include phase change RAM (PRAM) using phase change of chalcogenide materials, MRAM (Magnetic RAM) using spin of magnetic material, and oxidation / reduction of organic molecules. RRAM (Resistance RAM) using a material called a molecular memory or a strongly correlated electron system. Above all, phase change memory has attracted attention as the next generation of non-volatile memory for memory embedded microcomputers and DRAM replacement memory because of its features such as high speed of writing and reading, and high rewrite endurance and integration. Speak.

[0005] A phase change memory uses a chalcogenide film as a storage layer, and the chalcogenide is heated by heat. Using the change in the amorphous state (high resistance) and the crystalline state (low resistance) with different electrical resistance, the difference in the amount of current flowing through the film is stored and read out as "1" to "0" information. Multi-component chalcogenide, a storage layer material, has already been used as a recording layer material for optical discs such as CD-RW and DVD-RAM. Compared to it, it is easy to handle.

[0006] The following Patent Documents 1 to 6 disclose techniques for forming a multi-system chalcogenide film on the surface of an optical disc by sputtering using a plurality of types of sputtering targets.

[0007] JP 2004-255698 A (Patent Document 1) describes an InGeSbTe recording layer by sputtering using two types of targets (InSbTe—GeSb, InSbTe—Ge, GeSbTe—InSbTeTeGeSbTe—In). A technique for forming a film is disclosed.

JP-A-2005-254485 (Patent Document 2) describes three types of targets (GeTe-BiTe

The technology to form a BiGeSiTe recording layer by sputtering using -SiTe) is disclosed.

[0009] Japanese Unexamined Patent Publication No. 2001-56958 (Patent Document 3) discloses a technique for forming a recording layer by a sputtering method using two types of targets (GeSbTe—GeSGeSbTe—Ta, GeSbTe—InSbTe). Yes.

[0010] Japanese Unexamined Patent Publication No. 2000-79761 (Patent Document 4) describes AgGaGeSbTe, AgGaSbTe, Znln

A recording layer deposition technique is disclosed by a sputtering method using two or more targets of any of SbTe, GaSbTe, Sb, Ge, Ag, and SbTe.

[0011] Japanese Unexamined Patent Application Publication No. 2004-2688587 (Patent Document 5) describes two types of targets (CrTe-GeSb

Disclosure of recording layer deposition technology by sputtering using Te etc.! /

Japanese Laid-Open Patent Publication No. 4-106740 (Patent Document 6) describes a recording layer by sputtering using three types of single element targets (Ge—S b—Te) or three types of GeSbTe targets having different composition ratios. The film forming technique is disclosed.

Patent Document 1: Japanese Patent Application Laid-Open No. 2004-255698

Patent Document 2: Japanese Patent Laid-Open No. 2005-254485

Patent Document 3: Japanese Patent Laid-Open No. 2001-56958 Patent Document 4: JP 2000-79761 A

Patent Document 5: Japanese Unexamined Patent Application Publication No. 2004-268587

Patent Document 6: Japanese Patent Laid-Open No. 4-106740

Disclosure of the invention

Problems to be solved by the invention

[0013] When a semiconductor chip is mounted on a wiring board or the like, it is exposed to a temperature environment higher than its operating temperature, for example, 250 ° C for several minutes in the soldering process and 180 ° C for several hours in the crimping process. Is done. In the case of a memory-embedded microcomputer, mounting is usually performed after the program is stored in the memory part, so data is not erased due to thermal load during the mounting process. Data retention characteristics must be guaranteed even in high temperature environments.

[0014] However, chalcogenide, which is a storage layer material for phase change memory, becomes a metastable phase in a high-resistance amorphous state, so that crystallization (low resistance) proceeds rapidly in a high-temperature environment. There is a problem of end.

[0015] For example, the present inventors have studied the use of a ternary chalcogenide composed of Ge—Sb—Te as a storage layer material of a phase change memory. In the case of Ge Sb Te, 140 ° About C

2 2 5

When exposed to a high temperature environment, the data changes to an amorphous state force crystal state within a few hours and data is lost. Therefore, the present inventors examined the use of InGeSbTe, which has higher heat resistance than GeSbTe, as the storage layer material in order to realize a phase change memory that exhibits excellent data retention characteristics even in a high temperature environment.

[0016] Usually, a sputtering method is used to form a chalcogenide film on the surface of an optical disk or a semiconductor wafer. Therefore, an InGeSbTe target is required to form an InGeSbTe film by sputtering. However, since In does not completely dissolve in GeSbTe, when an InGeSbTe target is manufactured, for example, a crystal having a composition of Ge Sb Te is formed.

2 2 5

A phase-separated target in which grains and crystal grains having a composition of InTe are mixed is obtained.

twenty three

[0017] Here, when a target having a composition of Ge Sb Te force is used, the deposition rate is In Te or

Since it is about twice as fast as using a 2 2 5 2 3 threaded target, the sputtering of Ge Sb Te

The 2 25 5 rate is estimated to be about twice as large as In Te. As a result, the result is a different composition. When a single InGeSbTe target with mixed grains is used for film formation, the stoichiometric composition of InGeSbTe varies locally or changes over time.

[0018] In particular, in the case of a phase change memory that reads a signal by a difference in resistance value accompanying a phase change, unlike the optical disk that reads a signal by a difference in the refractive index of light, the above-described change in the composition of the storage layer Even slight variations can cause degradation of electrical characteristics and, in turn, manufacturing yield and reliability.

An object of the present invention is to provide a technology for manufacturing a phase change memory that exhibits excellent data retention characteristics even in a high temperature environment.

[0020] The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Means for solving the problem

[0021] Among the inventions disclosed in the present application, typical ones and effects obtained thereby will be briefly described as follows.

(1) An invention of the present application is a method for manufacturing a semiconductor memory device, comprising a step of forming a memory layer for storing information on a semiconductor substrate by a difference in electrical resistance value associated with a phase change. The layer is composed of a chalcogenide film having indium, germanium, antimony, and tellurium force, and the chalcogenide film is formed by sputtering using a plurality of types of targets each composed of a compound having a stable composition. .

(2) One invention of the present application is that a memory cell selecting MISFET formed on a main surface of a semiconductor substrate is electrically connected to the memory cell selecting MISFET, and information is obtained by a difference in electric resistance value accompanying a phase change. A method for manufacturing a semiconductor memory device having a memory layer for storing, wherein the memory layer is an indium, germanium, antimony, and tellurium force chalcogenide film formed on an interlayer insulating film covering the memory cell selecting MISFET The step of forming the memory layer includes the following steps (a) to (c).

(a) forming the chalcogenide film on the interlayer insulating film using a sputtering method using a plurality of types of targets each composed of a compound having a stable composition;

(b) forming a conductive film for the upper electrode on the chalcogenide film,

(c) by patterning the conductive film and the chalcogenide film, Forming the upper electrode made of a conductive film and the memory layer made of the chalcogenide film.

In the present application, the term “stable composition” refers to a composition in which a compound is not separated into crystal grains having different compositions and crystal phases even if the compound is kept in a high temperature environment for a long time. Point to. What can be expressed as stoichiometric composition, equilibrium composition, and compound composition can be a stable composition. If a target having a stable composition is used, the uniformity of the crystal phase and composition of the crystal grains constituting the target can be increased.

[0023] For example, in the case of a ternary system composed of Ge—Sb—Te, two kinds of Te compounds (GeTe and Sb

2

If Te) is mixed in an integer ratio, a stable composition is obtained. That is, (GeSb) (Sb Te) (0 <X

3 X 2 3 X- l

<Use a composition target that can be expressed in 1).

[0024] As shown in the state diagram of FIG. 20, at least three kinds of lines are connected on the line connecting GeTe and Sb Te.

twenty three

There is a compound composition. GeTe and Sb Te are considered pseudo-binary systems.

twenty three

When it is composed of a composition ratio of 6.6 atomic percent of Sb Te force (GeSb Te), it is as low as 870K.

2 3 4 7 When the composition ratio of GeTe is 50 atomic% and Sb Te force is ¾0 atomic% (GeSb

2 3 2

Te), stable up to 888K, GeTe force 6.6 atomic% and Sb Te force ¾3.3 atomic%

4 2 3

When constructed with a composition ratio (Ge Sb Te), it is stable up to 903K. Ge SbTe is also stable

It is known as 2 2 5 4 5 That is, GeSb Te, GeSb Te, Ge Sb Te, Ge

4 7 2 4 2 2 5

If a target with a composition that can be expressed in SbTe is used, the crystal phase and composition of the crystal grains are uniform.

4 5

The sex can be further increased. The composition of Ge, Sb, and Te is acceptable up to ± 2% variation.

[0025] For example, in the case of a binary system composed of Ge-Te, the composition is stable up to 430 ° C when the composition ratio of Ge is 50 atomic% and Te is 50 atomic%. In other words, a target with a composition that can be expressed in GeSb may be used. The composition of Ge and Te is acceptable up to ± 2% variation. For example, a binary system composed of Sb—Te is stable up to 617 ° C when it is composed of a composition ratio of 40 atomic% Sb and 60 atomic% Te. In other words, a target with a composition that can be expressed in Sb Te.

twenty three

It may be used. Note that the composition of Sb and Te can tolerate a variation of ± 2%. For example, a binary system composed of In—Te is stable up to 462 ° C when In is composed of 57.1 atomic% and Te is 42.9 atomic%. Composition with atomic% and Te 50 atomic% The composition is stable up to 696 ° C, and the composition is stable up to 649 ° C with an In force of 2.9 atomic% and Te of 57.1 atomic%. If the composition ratio of Te is 60 atomic% at atomic%, the composition is stable up to 605 ° C. If the composition ratio of Te is 7.5 atomic% and Te is 62.5 atomic%, 625 It is stable up to ° C, and it is stable up to 467 ° C when it is composed of a composition ratio of 71.4 atomic% In and 28.6 atomic% In. In Te, InTe (pair

4 3 Composition ratio = 1: 1) Use target with composition that can be expressed as In Te, In Te, In Te, In Te

3 4 2 3 3 5 2 5

It only has to be. It should be noted that the composition of In and Te can tolerate a variation of ± 2%.

The invention's effect

[0026] The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

[0027] Since a chalcogenide film with good electrical properties and high heat resistance can be produced, it can be used in a high temperature environment! / A phase change memory that exhibits excellent data retention characteristics can be manufactured with good yield.

Brief Description of Drawings

FIG. 1 is a cross-sectional view showing a method of manufacturing a phase change memory according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a method for manufacturing the phase change memory following FIG. 1.

FIG. 3 is a cross-sectional view showing a method for manufacturing the phase change memory following FIG. 2.

FIG. 4 is a cross-sectional view showing a method for manufacturing the phase change memory following FIG. 3.

FIG. 5 is a cross-sectional view showing a method for manufacturing the phase change memory following FIG. 4.

FIG. 6 is a cross-sectional view showing a method for manufacturing the phase change memory following FIG. 5.

FIG. 7 is a cross-sectional view showing a method for manufacturing the phase change memory following FIG. 6.

FIG. 8 is a schematic configuration diagram showing an example of a sputtering apparatus used for manufacturing a phase change memory.

9 is a schematic configuration diagram showing a sputtering chamber of the sputtering apparatus shown in FIG.

FIG. 10 is a sectional view of a key portion showing the method for manufacturing the phase change memory following FIG. 6.

FIG. 11 is a sectional view of a key portion showing a method for manufacturing the phase change memory following FIG. 10.

12 is a sectional view of the substantial part showing the production method of the phase change memory following FIG. 11. FIG.

13 is a sectional view of the substantial part showing the production method of the phase change memory following FIG. 12. FIG. 14 is a fragmentary cross-sectional view showing the manufacturing method of the phase change memory following FIG. 13.

FIG. 15 is a cross sectional view for a main portion showing the method for manufacturing the phase change memory following FIG. 14.

FIG. 16 is a cross sectional view for a main portion showing the method for manufacturing the phase change memory following FIG. 15.

17 is a fragmentary cross-sectional view showing the manufacturing method of the phase change memory following FIG. 16. FIG.

FIG. 18 is a schematic configuration diagram showing another example of a sputtering apparatus used for manufacturing a phase change memory.

FIG. 19 is a diagram for explaining the operation principle of the phase change memory according to the embodiment of the present invention.

FIG. 20 is a phase diagram of Ge—Sb—Te chalcogenide.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

[0030] (Embodiment 1)

A method of manufacturing a phase change memory according to the present embodiment will be described in the order of steps with reference to FIGS. First, as shown in FIG. 1, a p-type semiconductor substrate (hereinafter referred to as a substrate) 1 having a single crystal silicon force with a plane orientation (100) is prepared. As the substrate 1, a semiconductor substrate other than the single crystal silicon substrate, for example, an SOI (Silicon On Insulator) substrate, a single crystal Ge substrate, a GOI (Ge On Insulator) substrate, a strained silicon substrate in which strain stress is applied to the crystal, or the like is used. There is no problem.

Next, after an opening is formed in the substrate 1 by dry etching using the silicon nitride film as a mask, an oxide silicon film is embedded in the opening. Subsequently, the surface of the substrate 1 is flattened by a chemical mechanical polishing (CMP) method, and an element isolation groove 2 is formed, thereby defining an active region in which a transistor is formed.

Next, ion implantation and stretching heat treatment for adjusting the substrate concentration, and ion implantation and activation heat treatment for adjusting the threshold voltage are performed. Subsequently, after the surface of the substrate 1 is washed with a dilute hydrofluoric acid aqueous solution, thermal oxidation is performed to form the gate insulating film 3 made of an oxide silicon film having a thickness of about 3 nm on the surface of the substrate 1. As the gate insulating film 3, an insulating film other than a silicon oxide film, for example, a silicon oxynitride film (SiON film) whose surface is nitrided is used. Alternatively, a high-k film obtained by oxidizing or nitriding various metals, or a laminated film of these may be used.

Next, as shown in FIG. 2, after a polycrystalline silicon film 4n is deposited on the gate insulating film 3 by the CVD method, a cap made of an oxide silicon film is deposited on the polycrystalline silicon film 4n by the CVD method. Insulating film 5 is deposited. In order to make the polycrystalline silicon film 4n have n-type conductivity, phosphorus or arsenic is introduced during the film formation. The polycrystalline silicon film 4n serves as a gate electrode material, but a gate electrode material other than the polycrystalline silicon film 4n, such as a silicide film or a metal film, may be used.

Next, as shown in FIG. 3, the gate insulating film 5 and the polycrystalline silicon film 4n are patterned by dry etching using a photoresist film as a mask to form the gate electrode 4, followed by Then, phosphorus or arsenic is ion-implanted into the substrate 1 to form the n_ type diffusion layer 6.

Next, as shown in FIG. 4, a sidewall spacer 7 is formed on the side wall of the gate electrode 4 by anisotropically etching a silicon nitride film deposited on the substrate 1 by the CVD method, followed by Then, after ion implantation of arsenic into the substrate 1, an n + diffusion layer 8 constituting the source and drain is formed by performing an active heat treatment. The n-channel type memory cell selection MISFET is completed through the above steps. The gate electrode 4 can also be formed by a dummy gate process. In the dummy gate process, a dummy gate conductive film (such as a polycrystalline silicon film) deposited on the gate insulating film is first processed to form a dummy gate electrode, followed by formation of a source and drain, and then gate insulation. The film and dummy gate electrode are removed. Next, a gate insulating film is formed again, and a conductive film for a gate (such as a metal film) is deposited thereon, and then the conductive film is processed to form a gate electrode. When a dummy gate process is used, the gate insulating film is formed by using a high-k material having a low crystallization temperature.

Next, as shown in FIG. 5, an interlayer insulating film 10 made of an oxide silicon film is deposited on the substrate 1 by the CVD method, and then the surface is flattened by the mechanical mechanical polishing method. After contact, a contact hole 11 is formed in the interlayer insulating film 10 above the n + diffusion layer 8 (source and drain), and a plug 12 is formed inside the contact hole 11. The plug 12 serves to electrically connect the memory layer formed on the interlayer insulating film 10 and the MISFET for selecting the lower memory cell in the next process. For example, it is composed of a laminated film of a TiN film and a W film.

Next, as shown in FIG. 6, a first-layer wiring 13 is formed on the interlayer insulating film 10.

The wiring 13 is formed, for example, by depositing a W film on the interlayer insulating film 10 by sputtering and patterning the W film by dry etching using a photoresist film as a mask. The wiring 13 is electrically connected to the n + diffusion layer 8 through the plug 12 inside the contact hole 11.

Next, as shown in FIG. 7, an interlayer insulating film 14 made of an oxide silicon film is deposited on the substrate 1 by the CVD method, and then the surface is flattened by the mechanical mechanical polishing method. Then, through holes 15 and plugs 16 are formed in the interlayer insulating film 14 above the wirings 13 by a method similar to the method of forming the contact holes 11 and the plugs 12.

Next, an oxide tantalum (Ta 2 O 3) film is formed on the interlayer insulating film 14 using the following method.

An interface layer 18 consisting of 2 5, an InGeSbTe film 19a as a memory layer material, and a W film 20a as an upper electrode material are deposited.

FIG. 8 is a schematic configuration diagram showing a multi-chamber type sputtering apparatus used for forming the interface layer 18, the InGeSbTe film 19a, and the W film 20a. The sputtering apparatus 100 includes a plurality of chambers including a sputtering chamber 101 and a heat treatment chamber 102, a robot hand 103 that transports the substrate 1 (Ueno) to the plurality of chambers, a loader 104, and an unloader 105. It is configured so that film formation and heat treatment can be performed continuously inside the apparatus.

FIG. 9 is a schematic configuration diagram showing the sputtering chamber 101 of the sputtering apparatus 100 shown in FIG. At the center of the sputter chamber 101, a wafer stage 106 serving also as one electrode is installed, and a substrate 1 (wafer) is positioned on the wafer stage 106. Above the wafer stage 106, four force sword electrodes 108a, 108b, 108c, 108d force S, which also serve as target holders, are installed. The Ta target 109c is attached to the W target 109b, the force sword electrode 108c, and the InTe target 109d is attached to the force sword electrode 108d. Further, magnets 107a, 107b, 107c, and 107d for applying a magnetic field to the targets (109a to 109d) are installed on the force sword electrodes 108a to 108d, respectively. That is, the sputtering apparatus 100 is a multi-force sword type magnetron sputtering apparatus that performs film formation using four types of targets (109a to 109d) attached to four force sword electrodes (108a to 108d).

[0042] Here, the GeSbTe target 109a is composed of a GeSbTe compound having a stable composition, for example, Ge Sb Te. Similarly, InTe target 109d has a stable composition

2 2 5

InTe compounds such as InTe are used. As mentioned above, the stable composition is

twenty three

Even if the compound is kept in a high temperature environment for a long time, it cannot be separated into crystal grains with different compositions and crystal phases! Point to the composition! /

In order to form a film using the sputtering apparatus 100, first, Ar gas is introduced into the sputtering chamber 101, and the wafer stage 106 on which the substrate 1 (wafer) is mounted is rotated at a rate of about 60 revolutions per minute. Rotate horizontally. Subsequently, a predetermined voltage is applied between the force sword electrode 108c holding the Ta target 109c and the wafer stage 106 by applying a predetermined DC power. A predetermined magnetic field is applied to the Ta target 109c using the magnetic coil 107a.

Thereby, a plasma is formed between the force sword electrode 108c and the wafer stage 106, and the Ar gas is dissociated into Ar + ions. The dissociated Ar + ions collide with the Ta target 109c held by the force sword electrode 108c, and a Ta film 18a is formed on the surface of the substrate 1 (wafer) (FIG. 10). Next, the substrate 1 is transferred to the heat treatment chamber 102 shown in FIG. 8, and the Ta film 18a is radical-oxidized to form an interface layer 18 made of a tantalum oxide (Ta 2 O 3) film (FIG. 11).

twenty five

). The interface layer 18 functions as an adhesive layer that prevents the interlayer insulating film 14 and the memory layer material (InGeSbTe film 19a) formed thereon from being peeled off. It also serves as a heat resistance layer that suppresses escape. In FIG. 10 and subsequent cross-sectional views, illustration of the portion below the wiring 13 is omitted for easy understanding of the drawing.

Next, after returning the substrate 1 to the sputtering chamber 101 again, Ar gas is introduced into the sputtering chamber 101 and the wafer stage 106 on which the substrate 1 is mounted is rotated. Subsequently, a predetermined RF power is applied to the force sword electrode 108a holding the GeSb Te target 109a, the force sword electrode 108d holding the InTe target 109d, and the wafer stage 106, A predetermined magnetic field corresponding to each of GeSbTe target 109a and InTe target 109d is applied using magnetic coils 107a and 107d.

[0046] Thereby, plasma is formed between the force sword electrodes 108a and 108d and the wafer stage 106, and Ar gas is dissociated into Ar + ions. The dissociated Ar + ions collide with the GeSbTe target 109a held by the force sword electrode 108a and the InTe target 109d held by the force sword electrode 108d, and an InGeSbTe film 19a is formed on the interface layer 18 ( (Figure 12). Subsequently, the force sword electrodes 108a and 108d are turned off, and then the force sword electrode 108b holding the W target 109b is turned on to deposit the W film 20a on the InGeSbTe film 19a (FIG. 13).

[0047] The InGeSbTe film 19a formed by the above-described method has a stoichiometric composition because the two types of targets used (GeSb Te target 109a and InTe target 109d) both have stable yarns. As a result of suppressing local variation and fluctuation over time, the crystal phase and composition uniformity of the crystal grains are higher than those of InGeSbTe films formed using a single InGeSbTe target. It becomes a film.

Next, as shown in FIG. 14, after an oxide silicon film is deposited on the W film 20a by a CVD method, the oxide silicon film is patterned by dry etching using a photoresist film as a mask. The hard mask 21 is formed by Jung. Subsequently, as shown in FIG. 15, the upper electrode 20 is formed by patterning the W film 20a by dry etching using the hard mask 21 as a mask.

Next, after removing the hard mask 21, as shown in FIG. 16, the InGeSbTe film 19 a is patterned by dry etching using the upper electrode 20 as a mask, and then the interface layer under the InGeSbTe film 19 a is formed. Patter 18 Through the steps so far, the memory layer 19 made of the InGeSbTe film 19a is formed on the interlayer insulating film.

Next, as shown in FIG. 17, an interlayer insulating film 22 made of an oxide silicon film is deposited on the upper electrode 20 by a CVD method, and then the surface is subjected to an electrochemical mechanical polishing method. After flattening, the through hole 23 and the plug 24 are formed in the interlayer insulating film 22 on the upper electrode 20 by the same method as the method for forming the through hole 15 and the plug 16 described above. Next, the second layer 13 is formed on the interlayer insulating film 22 by a method similar to the method for forming the first layer wiring 13. A layer of wiring 25 is formed. The wiring 25 is electrically connected to the upper electrode 20 via the plug 24 inside the through hole 23.

Thus, in this embodiment, since two types of targets (GeSbTe target 109a and InTe target 109d) having a stable composition are sputtered simultaneously to form InGeSbTe film 19a, the chemistry of InGeSbTe film 19a Local variations in stoichiometric composition and fluctuations over time are suppressed. As a result, an InGeSbTe film 19a having a high crystal phase and composition uniformity of crystal grains can be obtained, so that a memory layer 19 having good electrical characteristics and high heat resistance can be obtained. Therefore, a phase change memory that exhibits excellent data retention characteristics even in a high temperature environment can be manufactured with high yield. In addition, since the wafer stage 106 on which the semiconductor substrate 1 is placed is rotated, the uniformity of the film thickness within the surface of the semiconductor substrate 1 can be improved even if a plurality of targets are sputtered simultaneously.

[0052] When forming the InGeSbTe film 19a, instead of simultaneously sputtering two types of targets (GeSbTe target 109a and InTe target 109d), a force sword electrode 108a holding the GeSbTe target 109a and Alternatively, RF power may be alternately applied to the force sword electrode 108d that holds the InTe target 109d, and the GeSbTe film formation and the InTe film formation may be alternately repeated. In this case, it is desirable to switch the RF power applied to the two force sword electrodes 108a and 108d in a short time in order to ensure the uniformity of the crystal phase and composition of the crystal grains.

[0053] The combination of two types of targets (GeSbTe target 109a and InTe target 109d) used when forming the InGeSbTe film 19a is a set that can be expressed by Ge Sb Te.

2 2 5

The combination of the compound and the compound having a composition that can be expressed by In Te is limited.

twenty three

There is no. That is, the GeSbTe target 109a has a composition that can be expressed by another GeSb Te compound having a stable yarn, for example, GeSb Te, GeSb Te, or Ge SbTe.

4 7 2 4 4 5

A compound can be used. In this case, the composition ratio of Ge, Sb, and Te in the GeSbTe composite can be allowed up to ± 2% variation.

[0054] Similarly, as the InTe target 109d, other InTe compounds having a stable composition, for example, In Te, InTe (composition ratio = 1: 1), a combination of compositions that can be expressed as In Te, In Te, and In Te are used.

4 3 3 4 3 5 2 5

Can be used. Also in this case, the composition ratio of In and Te in the InTe compound is ± 2%. Variations can be tolerated.

Further, in this embodiment, two or more types having a stable composition are formed by simultaneously sputtering two types of targets having a stable composition (GeSbTe target 109a and InTe target 109d) to form an InGeSbTe film 19a. The InGeSbTe film 19a is formed by simultaneously sputtering the target.

[0056] As an example, a first target composed of a GeTe compound, a second target composed of an SbTe compound, and a third target composed of an InTe compound are simultaneously sputtered, and InGeSbTe The film 19a can also be formed. In this case, a compound having a composition that can be expressed as GeTe (composition ratio = 1: 1) is used as a GeTe compound having a stable composition. In addition, as a SbTe compound having a stable composition, a compound having a composition that can be expressed by Sb Te is used.

twenty three

Use. Examples of InTe compounds having a stable composition include the above compounds (In Te, In Te, I

2 3 4 3 nTe, In Te, In Te, In Te) can be used.

3 4 3 5 2 5

[0057] When the above first to third targets are attached to the three force sword electrodes (for example, 108a to 108c) of the sputter channel 101 shown in FIG. 9, the remaining one force sword electrode (for example, 108d) Attach either W target 109b or Ta target 109c to the film. For example, when the W target 109b is attached to the remaining one force sword electrode, the oxide tantalum (Ta 2 O 3) film constituting the interface layer 18 is formed using a separate sputtering chamber.

twenty five

Just do it.

Further, as shown in FIG. 18, the InGeSbTe film 19a can be formed using a sputtering apparatus provided with three force sword electrodes (108a, 108b, 108c) in the sputtering chamber 101. In this case, the first to third targets (InTe target 109d, GeTe target 109e, SbTe target 109f) having the above-described stable composition are attached to the force sword electrodes (108a, 108b, 108c) and sputtered simultaneously. . Alternatively, two types of targets with stable composition (GeSbTe target 109a and InTe target 109d) are attached to two force sword electrodes, and the remaining one of the force sword electrodes is displaced by W target 109b or Ta target 109c. It is also possible to carry out film formation by attaching these.

[0059] According to the present embodiment in which the InGeSbTe film 19a is formed using a plurality of targets having different compositions, by changing the number and combination of the targets used, the InGeSbTe It is possible to optimize the composition ratio of the four types of atoms (In, Ge, Sb and Te) constituting the Te film 19a. It is also possible to optimize the composition ratio of the four types of atoms that make up the InGeSbTe film 19a by controlling the RF power applied to each force sword electrode while keeping the number and combination of targets constant. is there. Furthermore, by changing the RF power applied to the force sword electrode during film formation, the composition ratio of atoms along the film thickness direction of the InGeSbTe film 19a can be changed. Can be controlled along the film thickness direction.

In FIG. 9 and FIG. 18, the target surface and the semiconductor substrate surface are arranged parallel to each other. However, the present invention is not limited to this, and the target surface is arranged obliquely so as to face the center of the semiconductor substrate. May be. In this case, the film formation rate increases and at the same time the film thickness and composition uniformity improve. Further, in the drawing, the force is described as each target is arranged in a horizontal row. However, the present invention is not limited to this. For example, when the targets are arranged at equal distances from the center of the semiconductor substrate 1, the uniformity of the film thickness and composition is improved.

Next, the operation principle of the phase change memory obtained by the manufacturing method of the present embodiment will be described with reference to FIG. When the chalcogenide material is made amorphous, a reset pulse is applied so that the temperature of the chalcogenide material is heated above the melting point to rapidly cool it. The melting point is, for example, 600 ° C. The rapid cooling time (tl) is, for example, 2 nsec. When the chalcogenide material is crystallized, a set pulse is applied so that the temperature of the chalcogenide material is maintained above the crystallization temperature and below the melting point. The crystallization temperature is, for example, 400 ° C. The time (t2) required for crystallization is 50 nsec, for example.

[0062] While the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. There's nothing wrong!

Industrial applicability

[0063] The present invention can be applied to the manufacture of a phase change memory using a chalcogenide film as a storage layer.

Claims

The scope of the claims

[1] A method of manufacturing a semiconductor memory device comprising a step of forming a memory layer for storing information on a semiconductor substrate by a difference in electrical resistance value accompanying a phase change,

The memory layer is composed of a chalcogenide film having indium, germanium, antimony and tellurium force,

The method of manufacturing a semiconductor memory device, wherein the chalcogenide film is formed by sputtering using a plurality of types of targets each composed of a compound having a stable composition.

[2] The semiconductor memory according to [1], wherein a first target having a stable composition of indium-tellurium compound and a second target made of a germanium antimony tellurium compound having a stable composition are used. Device manufacturing method.

[3] A first target that has a stable composition of indium and tellurium, a second target that has a stable composition of germanium and tellurium, and an antimony and tellurium compound that has a stable composition. 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein a third target is used.

[4] MISFET for memory cell selection formed on the main surface of the semiconductor substrate;

A method of manufacturing a semiconductor memory device, comprising: a memory layer electrically connected to the memory cell selection MISFET and storing information by a difference in electrical resistance value associated with a phase change, wherein the memory layer comprises the memory cell The step of forming the memory layer comprising a chalcogenide film also having indium, germanium, antimony and tellurium force formed on an interlayer insulating film covering the selection MISFET,

(b) forming a conductive film for the upper electrode on the chalcogenide film,

(c) forming the upper electrode made of the conductive film and the memory layer made of the chalcogenide film by patterning the conductive film and the chalcogenide film; A method for manufacturing a semiconductor memory device, comprising:

[5] The semiconductor memory according to claim 4, wherein the first target having a stable composition of indium / tellurium compound and the second target made of a germanium antimony tellurium compound having a stable composition are used. Device manufacturing method.

[6] A first target with a stable composition of indium and tellurium, a second target with a stable composition of germanium and tellurium, and an antimony and tellurium compound with stable composition. A third target is used.

4. A method of manufacturing a semiconductor memory device according to 4.

7. The method for manufacturing a semiconductor memory device according to claim 4, wherein the conductive film is made of a tungsten film.

[8] The step of patterning the conductive film and the chalcogenide film includes:

(c-1) forming a silicon oxide film on the conductive film and then patterning the silicon oxide film;

(c-2) patterning the conductive film using the patterned silicon oxide film as a mask;

(c 3) patterning the chalcogenide film using the patterned conductive film as a mask;

The method of manufacturing a semiconductor memory device according to claim 7, comprising:

[9] MISFET for memory cell selection formed on the main surface of the semiconductor substrate;

(a) On the interlayer insulating film, a role as an adhesive layer for preventing peeling between the interlayer insulating film and the chalcogenide film and a role as a thermal resistance layer for suppressing heat escape from the memory layer. A step of forming an interfacial layer, (b) forming the chalcogenide film on the interface layer using a sputtering method using a plurality of types of targets each composed of a compound having a stable composition;

(c) forming a conductive film for the upper electrode on the chalcogenide film,

(d) forming the upper electrode made of the conductive film and the memory layer made of the chalcogenide film by patterning the conductive film, the chalcogenide film, and the interface layer;

A method for manufacturing a semiconductor memory device, comprising:

10. The semiconductor memory according to claim 9, wherein the first target having a stable composition of indium / tellurium compound and a second target made of a germanium antimony tellurium compound having a stable composition are used. Device manufacturing method.

[11] A first target with a stable composition of indium and tellurium, a second target with a stable composition of germanium and tellurium, and an antimony and tellurium compound with a stable composition A third target is used.

9. A method for manufacturing a semiconductor memory device according to 9.

12. The method of manufacturing a semiconductor memory device according to claim 9, wherein in the step (d), the chalcogenide film and the interface layer are continuously patterned.

13. The method for manufacturing a semiconductor memory device according to claim 9, wherein the interface layer is made of a tantalum oxide film.

[14] The step of forming the oxide-tantalum tantalum film includes a step of forming a tantalum film on the interlayer insulating film by a sputtering method, and a step of oxidizing the tantalum film,

14. The method of manufacturing a semiconductor memory device according to claim 13, wherein the formation of the tantalum film and the formation of the chalcogenide film are performed using the same sputtering apparatus.

15. The semiconductor memory device according to claim 14, wherein the film formation of the tantalum film, the film formation of the chalcogenide film, and the film formation of the conductive film are performed using the same sputtering apparatus. Production method.