JP5061113B2 - Manufacturing method of semiconductor memory device - Google Patents

Manufacturing method of semiconductor memory device Download PDF

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JP5061113B2
JP5061113B2 JP2008537343A JP2008537343A JP5061113B2 JP 5061113 B2 JP5061113 B2 JP 5061113B2 JP 2008537343 A JP2008537343 A JP 2008537343A JP 2008537343 A JP2008537343 A JP 2008537343A JP 5061113 B2 JP5061113 B2 JP 5061113B2
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film
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manufacturing
memory device
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JPWO2008041285A1 (en
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裕一 松井
貴博 森川
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ルネサスエレクトロニクス株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/16Manufacturing
    • H01L45/1641Modification of the switching material, e.g. post-treatment, doping
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/24Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures
    • H01L27/2436Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures comprising multi-terminal selection components, e.g. transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/06Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/12Details
    • H01L45/122Device geometry
    • H01L45/1233Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/14Selection of switching materials
    • H01L45/141Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H01L45/144Tellurides, e.g. GeSbTe
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/16Manufacturing
    • H01L45/1608Formation of the switching material, e.g. layer deposition
    • H01L45/1625Formation of the switching material, e.g. layer deposition by physical vapor deposition, e.g. sputtering
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/16Manufacturing
    • H01L45/1666Patterning of the switching material
    • H01L45/1675Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography

Description

  The present invention relates to a manufacturing technique of a semiconductor memory device, and more particularly to a technique effective when applied to the manufacture of a phase change memory using a multi-component chalcogenide film as a storage layer.

  Information devices, home appliances, in-vehicle devices, and the like are equipped with microcomputers for embedded devices (memory-embedded microcomputers) in which flash memories for storing programs and data are embedded. In recent years, as the functions of these devices have improved, there has been an increasing demand for higher performance of memory-embedded microcomputers, and even for embedded flash memory, there has been a demand for improved rewrite endurance and further integration. Yes.

  Also in DRAMs that are general-purpose memories, miniaturization of memory cells has been promoted in order to meet the demand for higher integration. However, a DRAM that stores information with the amount of electric charge stored in a capacitor has a problem that the storage capacity decreases when the area of the capacitor is reduced. In addition, when the capacitor dielectric material is thinned to a certain value or less, there is a problem that leakage current increases. Previously, capacitors could be prevented from being reduced by forming capacitors in deep trenches, but when further miniaturization was promoted, the trench aspect ratio reached the limit of processing, and cutting-edge processing technology was developed. Even if you make full use, you will not be able to make a device with good yield.

  In view of such circumstances, recently, phase change RAM (PRAM) using phase change of chalcogenide material, MRAM (Magnetic RAM) using spin of magnetic material, oxidation / reduction of organic molecules are used. Development of various new semiconductor memory elements such as a molecular memory and an RRAM (Resistance RAM) using a substance called a strongly correlated electron system is underway. Among these, the phase change memory is attracting attention as a next-generation memory embedded microcomputer flash memory and an alternative memory for DRAM because it can perform writing / reading at high speed and is advantageous for high rewrite endurance and integration.

  Phase change memory utilizes the fact that the chalcogenide film constituting the memory layer reversibly changes from an amorphous state (high resistance) with different electrical resistance to a crystalline state (low resistance) due to heat, and the difference in the amount of current flowing through the film Is a memory that stores and reads out information as "1" and "0" information. Multi-component chalcogenide, which is a storage layer material, has already been used as a recording layer material for optical discs such as CD-RW and DVD-RAM. Compared to the materials used in other semiconductor storage elements described above And easy to handle.

  A sputtering method is used to form a chalcogenide film on the surface of an optical disk or a semiconductor wafer. For example, Patent Documents 1 and 2 below disclose a technique for forming a multi-system chalcogenide film on the surface of an optical disk by sputtering using a plurality of types of sputtering targets.

  Japanese Patent Application Laid-Open No. 2004-255698 (Patent Document 1) forms an InGeSbTe recording layer by sputtering using two types of targets (InSbTe—GeSb, InSbTe—Ge, InSbTeGeSb, GeSbTe—InSbTe, GeSbTe—In). The technology to do is disclosed.

  Japanese Patent Laying-Open No. 2005-254485 (Patent Document 2) discloses a technique for forming a BiGeSiTe recording layer by sputtering using three types of targets (GeTe-BiTe-SiTe).

  Further, when a multi-system chalcogenide film is deposited by sputtering, Ar (argon) used as a discharge gas (sputtering gas) in the sputtering chamber is mixed in the film, and, for example, in an optical disc, rewriting resistance may be deteriorated. Are known.

Japanese Patent Laid-Open No. 2004-203011 (Patent Document 3) and Japanese Patent Laid-Open No. 2006-4595 (Patent Document 4) reduce the pressure of a sputtering gas (a rare gas such as Ar) during film formation, A technique for increasing the density of the recording layer by increasing the amount of high energy Ar irradiated to the recording layer, for example, by disposing a substrate close to the recording layer is disclosed. At that time, if the amount of Ar is small, a sparse film is likely to be formed. Conversely, if the amount of Ar is large, the density of the film increases, but Ar taken into the film becomes a void during repeated overwriting. Therefore, the discharge pressure should be controlled to 10 −2 to 10 −3 Pa. Japanese Patent Laid-Open No. 2005-251389 (Patent Document 5) discloses that an appropriate amount of Ar in the recording layer film is 0.1 atomic% or more and 1.5 atomic% or less, and high-frequency sputtering is performed rather than direct current sputtering. It is pointed out that the use is preferable because a high-density film can be obtained by reducing the amount of Ar in the film.

Japanese Patent Laid-Open No. 06-333275 (Patent Document 6) discloses a discharge gas (Ar) taken into a recording layer or a dielectric layer in contact with the recording layer when a recording layer of an optical information recording medium is formed by a sputtering method. ) Gradually precipitates and agglomerates, generating voids and causing problems such as a decrease in signal amplitude and an increase in noise. Further, as a countermeasure, a technique of forming at least one selected from the dielectric layer and the dielectric layer by sputtering in a discharge gas containing at least one of Xe (xenon) gas and Kr (krypton) gas. Is disclosed.
JP 2004-255698 A JP 2005-254485 A JP 2004-203011 A JP 2006-4595 A JP 2005-251389 A Japanese Patent Laid-Open No. 06-333275

  When a semiconductor chip is mounted on a wiring board or the like, it is exposed to a temperature environment higher than its operating temperature, for example, 250 ° C. for several minutes in a soldering process and 180 ° C. for several hours in a crimping process. For example, in the case of a memory-embedded microcomputer, mounting is generally performed after the program is stored in the memory portion, so that data is not erased due to a thermal load in the mounting process to some extent than the operating temperature. It is necessary to guarantee data retention characteristics even in high temperature environments.

However, chalcogenide, which is a storage layer material for phase change memory, has a problem that crystallization (low resistance) proceeds rapidly in a high temperature environment because it becomes a metastable phase in a high resistance amorphous state. . For example, the present inventors have studied the use of a ternary chalcogenide made of Ge (germanium) Sb (antimony) Te (tellurium) as a storage layer material of a phase change memory, but the storage layer is made of Ge 2 Sb. When composed of 2 Te 5 film, exposure to a high temperature environment of about 140 ° C. changes from an amorphous state to a crystalline state within a few hours and data is lost, which is not suitable for practical use.

  Therefore, in order to realize a phase change memory that exhibits excellent data retention characteristics even in a high temperature environment, the present inventors have used a GeSbTe film with In (as a storage layer material having higher heat resistance than the GeSbTe film described above. We are studying the use of InGeSbTe films to which indium is added.

  However, when In is added to the GeSbTe film for the purpose of improving heat resistance, the amount of discharge gas (Ar) mixed in the film is increased compared to the GeSbTe film when depositing the InGeSbTe film by sputtering. Problems arise.

  FIG. 25 is a graph showing the results of thermal desorption spectroscopy (TDS) analysis of Ar desorbed from the GeSbTe film and InGeSbTe film deposited by sputtering, and the amount of Ar desorption is larger than that of the GeSbTe film. It shows that there are more InGeSbTe films. From this analysis result, it can be seen that when In is added to the GeSbTe film, the amount of Ar mixed in the film increases.

One of the causes is that Ar is easily taken into the film because of the large mass of In. In general, mass M G of the discharge gas used in the sputtering process, the mass of the film formed and M F, the more the M F> M G, the amount of discharge gas to be mixed in the film is increased. That is, when In having a larger mass than Ar is added to the GeSbTe film, light Ar is sputtered into heavy In and taken into the film.

  Another reason is that when In is added to the GeSbTe film, the crystallization temperature of the film increases, and it becomes difficult to desorb the discharge gas by heat treatment after the film formation. That is, the crystallization temperature of the GeSbTe film is about 120 ° C., whereas the crystallization temperature of the InGeSbTe film is about 300 ° C. to 400 ° C., depending on its composition. Therefore, when heat treatment for crystallization is performed on the InGeSbTe film, sublimation of atoms such as Te constituting the film becomes remarkable, and the composition ratio of the film changes or the film thickness becomes thin.

  In order to prevent this, after depositing an amorphous InGeSbTe film, an upper electrode material such as a W (tungsten) film is deposited on top of the amorphous InGeSbTe film so that the atoms constituting the film are not easily sublimated. It is necessary to perform the heat treatment. However, when the upper electrode material is deposited on the InGeSbTe film and then subjected to heat treatment at 200 ° C. or higher, the Ar gas in the InGeSbTe film aggregates and voids are generated as shown in FIG. It causes defects such as variations in values and changes over time.

  Note that in the case where the memory layer material is a GeSbTe film, the crystallization temperature is as low as about 120 ° C., so that sublimation of atoms constituting the film hardly occurs during the heat treatment for crystallization. Therefore, Ar can be desorbed from the film during the heat treatment for crystallization, and then the upper electrode material can be formed. Therefore, the generation of voids as described above can be easily avoided.

  As described above, when a chalcogenide film is deposited by sputtering, Ar used as a discharge gas (sputtering gas) is mixed in the film, which causes problems such as deterioration of rewriting resistance in an optical disk. It is. However, in the case of an optical disc, since a polycarbonate substrate having low heat resistance is used as the disc material, the manufacturing temperature is limited to about 120 ° C. or less.

  On the other hand, in the case of a phase change memory, a metal wiring must be formed after forming a memory layer on a semiconductor substrate, so that a heat treatment step of 400 ° C. or higher is necessarily performed. Therefore, the influence of Ar mixing on the phase change memory is larger than that of the optical disk. In addition, it is difficult to apply the conventional Ar contamination prevention measures used in the optical disc manufacturing process to the manufacturing process of a phase change memory using a chalcogenide film having a high crystallization temperature such as an InGeSbTe film as a memory layer material. It is.

  An object of the present invention is to provide a technique capable of reducing the amount of discharge gas mixed into a film when an InGeSbTe film constituting a storage layer of a phase change memory is deposited by a sputtering method.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
(1) An invention of the present application is a method for manufacturing a semiconductor memory device, comprising a step of forming a memory layer for storing information on a semiconductor substrate by a difference in electrical resistance value accompanying a phase change, wherein the memory layer The step of forming a film includes a step of depositing an InGeSbTe film on the semiconductor substrate by a sputtering method using a rare gas having an atomic weight larger than Ar as a discharge gas.
(2) One invention of the present application is a method for manufacturing a semiconductor memory device, comprising a step of forming a memory layer for storing information on a semiconductor substrate by a difference in electrical resistance value accompanying a phase change, wherein the memory layer The step of forming a film includes a step of depositing an InGeSbTe film on the semiconductor substrate by a sputtering method in a state where the temperature of the semiconductor substrate is kept at 100 ° C. to 250 ° C.
(3) One invention of the present application is a method for manufacturing a semiconductor memory device, comprising a step of forming a memory layer for storing information on a semiconductor substrate by a difference in electrical resistance value accompanying a phase change, wherein the memory layer The step of forming a film includes a step of depositing an InGeSbTe film on the semiconductor substrate by a sputtering method while maintaining the pressure of the discharge gas at 1 Pa or higher.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The phase change memory can be manufactured with a high yield.

It is sectional drawing which shows the manufacturing method of the phase change memory which is one embodiment of this invention. FIG. 2 is a cross-sectional view showing a method for manufacturing the phase change memory following FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the phase change memory following FIG. 2. FIG. 4 is a cross-sectional view showing a method for manufacturing the phase change memory following FIG. 3. FIG. 5 is a cross-sectional view showing a method for manufacturing the phase change memory following FIG. 4. FIG. 6 is a cross-sectional view showing a method for manufacturing the phase change memory following FIG. 5. FIG. 7 is a cross-sectional view showing a method for manufacturing the phase change memory following FIG. 6. It is a schematic block diagram which shows an example of the sputtering device used for manufacture of a phase change memory. It is a schematic block diagram which shows the sputtering chamber of the sputtering device shown in FIG. FIG. 7 is a fragmentary cross-sectional view showing the method for manufacturing the phase change memory following FIG. 6. FIG. 11 is a fragmentary cross-sectional view showing the phase change memory manufacturing method following FIG. 10; FIG. 12 is a fragmentary cross-sectional view showing the manufacturing method of the phase change memory following FIG. 11; FIG. 13 is a fragmentary cross-sectional view showing the manufacturing method of the phase change memory following FIG. 12; FIG. 14 is a main part cross-sectional view showing the phase change memory manufacturing method following FIG. 13; FIG. 15 is an essential part cross-sectional view showing a method for manufacturing the phase change memory following FIG. 14; FIG. 16 is a main part cross-sectional view showing the manufacturing method of the phase change memory following FIG. 15; FIG. 17 is a main part cross-sectional view showing the phase change memory manufacturing method following FIG. 16; It is a graph which shows the TDS analysis result of Xe which detach | desorbs from the InGeSbTe film | membrane deposited by the method of this invention. It is a schematic block diagram which shows the other example of the sputtering device used for manufacture of a phase change memory. It is a graph which shows the TDS analysis result of the discharge gas desorbed when heat-treating six types of InGeSbTe films deposited by changing the temperature of the substrate. It is a graph which shows the substrate temperature dependence of the discharge gas desorption amount calculated | required from the TDS analysis result of FIG. It is a graph which shows the TDS analysis result of the discharge gas desorbed when heat-treating four types of InGeSbTe films deposited by changing the pressure of the discharge gas in the sputtering chamber. It is a graph which shows the discharge gas pressure dependence of the discharge gas desorption amount calculated | required from the TDS analysis result of FIG. It is the figure which showed typically a mode that Ar gas desorbed from the InGeSbTe film aggregated and a void was generated. It is a graph which shows the TDS analysis result of Ar desorbed from the GeSbTe film | membrane and InGeSbTe film | membrane deposited by sputtering method.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
The method of manufacturing the phase change memory according to the present embodiment will be described in the order of steps with reference to FIGS. First, as shown in FIG. 1, a p-type semiconductor substrate (hereinafter referred to as a substrate) 1 made of single crystal silicon having a plane orientation (100) is prepared. As the substrate 1, in addition to a single crystal silicon substrate, for example, an SOI (Silicon On Insulator) substrate, a single crystal Ge substrate, a GOI (Ge On Insulator) substrate, a strained silicon substrate in which a strain stress is applied to the crystal, or the like may be used. Absent.

  Next, after an opening is formed in the substrate 1 by dry etching using the silicon nitride film as a mask, a silicon oxide film is embedded in the opening. Subsequently, the surface of the substrate 1 is planarized by a chemical mechanical polishing (CMP) method, and an element isolation trench 2 is formed, thereby defining an active region where a transistor is formed.

  Next, ion implantation for substrate concentration adjustment and stretching heat treatment, and ion implantation for threshold voltage adjustment and activation heat treatment are performed. Subsequently, after cleaning the surface of the substrate 1 with a dilute hydrofluoric acid aqueous solution, the gate insulating film 3 made of a silicon oxide film having a thickness of about 3 nm is formed on the surface of the substrate 1 by performing thermal oxidation treatment. As the gate insulating film 3, an insulating film other than a silicon oxide film, for example, a silicon oxynitride film (SiON film) in which the surface is nitrided, a high-k film in which various metals are oxidized or nitrided, or a laminated film thereof You can use it.

  Next, as shown in FIG. 2, after depositing a polycrystalline silicon film 4n on the gate insulating film 3 by the CVD method, a cap insulating film 5 made of a silicon oxide film is deposited on the polycrystalline silicon film 4n by the CVD method. To do. In the polycrystalline silicon film 4n, phosphorus or arsenic is introduced during the film formation in order to make the conductivity type n-type. The polycrystalline silicon film 4n serves as a gate electrode material, but a gate electrode material other than the polycrystalline silicon film 4n, such as a silicide film or a metal film, may be used.

Next, as shown in FIG. 3, the cap insulating film 5 and the polycrystalline silicon film 4n are patterned by dry etching using a photoresist film as a mask to form the gate electrode 4, and then the substrate 1 is coated with phosphorus. Alternatively, arsenic ions are implanted to form the n type diffusion layer 6.

Next, as shown in FIG. 4, a silicon nitride film deposited on the substrate 1 by the CVD method is anisotropically etched to form sidewall spacers 7 on the side walls of the gate electrode 4. After ion implantation, an activation heat treatment is performed to form the n + diffusion layer 8 constituting the source and drain. The n-channel type memory cell selection MISFET is completed through the steps so far. The gate electrode 4 can also be formed by a dummy gate process. In the dummy gate process, first, a dummy gate electrode is formed by processing a dummy gate conductive film (polycrystalline silicon film, etc.) deposited on the gate insulating film, followed by forming a source and drain, and then a gate insulating film. Then, the dummy gate electrode is removed. Next, a gate insulating film is formed again, and subsequently a conductive film for a gate (such as a metal film) is deposited thereon, and then the conductive film is processed to form a gate electrode. When the dummy gate process is used, the gate insulating film can be formed using a high-k material having a low crystallization temperature.

Next, as shown in FIG. 5, an interlayer insulating film 10 made of a silicon oxide film is deposited on the substrate 1 by a CVD method, and then the surface is planarized by a chemical mechanical polishing method, and then an n + diffusion layer is formed. A contact hole 11 is formed in the interlayer insulating film 10 above 8 (source, drain), and a plug 12 is formed inside the contact hole 11. The plug 12 serves to electrically connect the memory layer formed on the interlayer insulating film 10 in the next step and the underlying memory cell selection MISFET. For example, the plug 12 is a laminated film of a TiN film and a W film. Constitute.

Next, as shown in FIG. 6, a first layer wiring 13 is formed on the interlayer insulating film 10. The wiring 13 is formed by, for example, depositing a W film on the interlayer insulating film 10 by sputtering and then patterning the W film by dry etching using a photoresist film as a mask. The wiring 13 is electrically connected to the n + diffusion layer 8 through the plug 12 inside the contact hole 11.

  Next, as shown in FIG. 7, an interlayer insulating film 14 made of a silicon oxide film is deposited on the substrate 1 by a CVD method, and then the surface thereof is planarized by a chemical mechanical polishing method. The through hole 15 and the plug 16 are formed in the interlayer insulating film 14 on the wiring 13 by the same method as that for forming the plug 12.

Next, an interface layer 18 made of a tantalum oxide (Ta 2 O 5 ) film, an InGeSbTe film 19a that is a storage layer material, and a W film 20a that is an upper electrode material are formed on the interlayer insulating film 14 using the following method. accumulate.

  FIG. 8 is a schematic configuration diagram showing a multi-chamber type sputtering apparatus used for forming the interface layer 18, the InGeSbTe film 19a, and the W film 20a. The sputtering apparatus 100 includes a plurality of chambers including a sputtering chamber 101, a heat treatment chamber 102, and the like, a robot hand 103 that transfers the substrate 1 (wafer) to the plurality of chambers, a loader 104, and an unloader 105. The heat treatment can be continuously performed inside the apparatus.

  FIG. 9 is a schematic configuration diagram showing the sputtering chamber 101 of the sputtering apparatus 100 shown in FIG. At the center of the sputtering chamber 101, a wafer stage 106 that also serves as one electrode is installed, and the substrate 1 (wafer) is positioned on the wafer stage 106. Above the wafer stage 106, four cathode electrodes 108a, 108b, 108c, and 108d that also serve as a target holder, and a magnet 107a for applying a magnetic field to the cathode electrode are installed. The cathode electrode 108a has GeSbTe. A W target 109b is attached to the target 109a and the cathode electrode 108b, a Ta target 109c is attached to the cathode electrode 108c, and an InTe target 109d is attached to the cathode electrode 108d. That is, the sputtering apparatus 100 is a multi-cathode magnetron sputtering apparatus that performs film formation using four types of targets (109a to 109d) attached to four cathode electrodes (108a to 108d).

The GeSbTe target 109a is composed of a GeSbTe compound having a stable composition, for example, Ge 2 Sb 2 Te 5 . Similarly, the InTe target 109d is made of an InTe compound having a stable composition, for example, In 2 Te 3 . The stable composition refers to a composition that does not separate into crystal grains having different compositions and crystal phases even when the compound is kept in a high temperature environment for a long time.

  In order to form a film using the sputtering apparatus 100, first, Ar is introduced as a discharge gas into the sputtering chamber 101, and the wafer stage 106 on which the substrate 1 (wafer) is mounted is rotated at a rate of about 60 revolutions per minute. Rotate horizontally. Subsequently, a predetermined voltage is applied between the cathode electrode 108c holding the Ta target 109c and the wafer stage 106 by applying a predetermined DC power. Further, a predetermined magnetic field is applied to the cathode electrode 108c using the magnet 107a.

As a result, plasma is formed between the cathode electrode 108c and the wafer stage 106, and the Ar gas is dissociated into Ar + ions. The dissociated Ar + ions collide with the Ta target 109c held by the cathode electrode 108c, and a Ta film 18a is formed on the surface of the substrate 1 (wafer) (FIG. 10). Next, the substrate 1 is transferred to the heat treatment chamber 102 shown in FIG. 8, and the Ta film 18a is radical-oxidized to form the interface layer 18 made of a tantalum oxide (Ta 2 O 5 ) film (FIG. 11). The interface layer 18 serves as an adhesive layer that prevents the interlayer insulating film 14 and the memory layer material (InGeSbTe film 19a) formed thereon from peeling off, and Joule heat escapes from the memory layer to the plug 16 when information is rewritten. It also serves as a heat resistance layer that suppresses this. In FIG. 10 and subsequent cross-sectional views, illustration of a portion below the wiring 13 is omitted for easy understanding of the drawing.

  Next, after returning the substrate 1 to the sputtering chamber 101 again, Xe gas is introduced into the sputtering chamber 101 and the wafer stage 106 on which the substrate 1 is mounted is rotated. The pressure of the Xe gas introduced into the sputter chamber 101 is about 0.5 Pa. Further, the temperature of the substrate 1 on the wafer stage 106 is about 80 ° C. Subsequently, a predetermined RF power is applied to the cathode electrode 108a holding the GeSbTe target 109a, the cathode electrode 108d holding the InTe target 109d, and the wafer stage 106, and a predetermined magnetic field is applied to the cathode electrodes 108a and 108d using the magnet 107a. Apply.

As a result, plasma is formed between the cathode electrodes 108a and 108d and the wafer stage 106, and the Xe gas is dissociated into Xe + ions. The dissociated Xe + ions collide with the GeSbTe target 109a held by the cathode electrode 108a and the InTe target 109d held by the cathode electrode 108d, and an amorphous InGeSbTe film 19a is formed on the interface layer 18. (FIG. 12). Subsequently, after the cathode electrodes 108a and 108d are turned off, the cathode electrode 108b holding the W target 109b is turned on to deposit the W film 20a on the InGeSbTe film 19a (FIG. 13).

  Next, the substrate 1 is transferred to the heat treatment chamber 102 shown in FIG. 8, and the substrate 1 is heat-treated in a nitrogen atmosphere at about 300 ° C. to 400 ° C. to crystallize the amorphous InGeSbTe film 19a. Note that if the substrate 1 is heat-treated prior to the step of depositing the W film 20a, sublimation of atoms constituting the InGeSbTe film 19a becomes remarkable, and the composition ratio of the film varies or the film thickness decreases. Therefore, this heat treatment is preferably performed in a state where the InGeSbTe film 19a is covered with the W film 20a.

  In the InGeSbTe film 19a formed by the above method, since the two types of targets used (GeSbTe target 109a and InTe target 109d) both have a stable composition, the stoichiometric composition varies locally, As a result, the crystal phase and composition uniformity of crystal grains are higher than those of an InGeSbTe film formed using a single InGeSbTe target.

  Next, as shown in FIG. 14, after depositing a silicon oxide film on the W film 20a by a CVD method, the silicon oxide film is patterned by dry etching using a photoresist film as a mask, thereby forming a hard mask 21. Form. Subsequently, as shown in FIG. 15, the upper electrode 20 is formed by patterning the W film 20 a by dry etching using the hard mask 21 as a mask.

  Next, after removing the hard mask 21, as shown in FIG. 16, the InGeSbTe film 19a is patterned by dry etching using the upper electrode 20 as a mask, and then the interface layer 18 under the InGeSbTe film 19a is patterned. Through the steps so far, the memory layer 19 made of the InGeSbTe film 19a is formed on the interlayer insulating film.

  Next, as shown in FIG. 17, an interlayer insulating film 22 made of a silicon oxide film is deposited on the upper electrode 20 by a CVD method, and then the surface is planarized by a chemical mechanical polishing method. Through holes 23 and plugs 24 are formed in the interlayer insulating film 22 above the upper electrode 20 by a method similar to the method of forming the holes 15 and the plugs 16. Next, a second layer wiring 25 is formed on the interlayer insulating film 22 by a method similar to the method of forming the first layer wiring 13. The wiring 25 is electrically connected to the upper electrode 20 via the plug 24 inside the through hole 23.

  FIG. 18 shows a TDS analysis result of Xe desorbed from the InGeSbTe film 19a formed by the above method. As a comparative example, the TDS analysis result of Ar desorbed from an InGeSbTe film formed using Ar as a discharge gas is shown in FIG. As illustrated, the InGeSbTe film 19a formed using Xe as the discharge gas has a smaller amount of discharge gas desorption than the InGeSbTe film formed using Ar as the discharge gas. This tendency is particularly remarkable at a temperature of 200 ° C. or higher, which is the crystallization temperature of the InGeSbTe film 19a.

  This is because Xe having a mass larger than that of Ar is difficult to be mixed into the film during the deposition of the InGeSbTe film 19a. Therefore, even when Kr (krypton) having a larger mass (atomic weight) than Ar is used as the discharge gas, the amount of discharge gas mixed into the InGeSbTe film is reduced as compared with the case where Ar is used as the discharge gas. be able to. However, since Xe has a larger atomic weight than Kr, the effect of reducing the amount of discharge gas mixed in the InGeSbTe film is larger for Xe than for Kr.

  As described above, in this embodiment, since the InGeSbTe film 19a is formed using Xe as the discharge gas, desorption of the discharge gas can be suppressed during the heat treatment for crystallization. As a result, in the InGeSbTe film 19a. It is possible to suppress the problem that voids are generated.

  As a result, a phase change memory including the storage layer 19 made of the InGeSbTe film 19a having high heat resistance and exhibiting excellent data retention characteristics even in a high temperature environment can be manufactured with high yield.

  In the present embodiment, since two types of targets having a stable composition (GeSbTe target 109a and InTe target 109d) are simultaneously sputtered to form the InGeSbTe film 19a, the stoichiometric composition of the InGeSbTe film 19a is locally increased. Fluctuations and fluctuations with time are suppressed. As a result, an InGeSbTe film 19a having a high crystal phase and composition uniformity of crystal grains can be obtained, so that a memory layer 19 having good electrical characteristics and high heat resistance can be obtained. Accordingly, a phase change memory that exhibits excellent data retention characteristics even in a high temperature environment can be manufactured with a high yield.

  When forming the InGeSbTe film 19a, the cathode electrode 108a for holding the GeSbTe target 109a and the InTe target 109d are held instead of simultaneously sputtering two types of targets (GeSbTe target 109a and InTe target 109d). Alternatively, RF power may be alternately applied to the cathode electrode 108d, and the GeSbTe film formation and the InTe film formation may be alternately repeated. In this case, it is desirable to switch the RF power applied to the two cathode electrodes 108a and 108d in a short time in order to ensure the uniformity of the crystal phase and composition of the crystal grains.

Further, the combination of two types of targets (GeSbTe target 109a and InTe target 109d) used when forming the InGeSbTe film 19a is a compound having a composition that can be represented by Ge 2 Sb 2 Te 5 and a composition that can be represented by In 2 Te 3. The combination with the compound is not limited. That is, as the GeSbTe target 109a, another GeSbTe compound having a stable composition, for example, a compound having a composition that can be expressed as GeSb 4 Te 7 , GeSb 2 Te 4, or Ge 4 SbTe 5 can be used. In this case, the composition ratio of Ge, Sb, and Te in the GeSbTe compound can tolerate a variation of ± 2%.

Similarly, as the InTe target 109d, other InTe compounds having a stable composition, for example, In 4 Te 3 , InTe (composition ratio = 1: 1), In 3 Te 4 , In 3 Te 5 , and In 2 Te 5 are represented. A compound having a composition that can be used can be used. Also in this case, the composition ratio of In and Te in the InTe compound can tolerate a variation of ± 2%.

  In this embodiment, two types of targets (GeSbTe target 109a and InTe target 109d) having a stable composition are simultaneously sputtered to form an InGeSbTe film 19a. However, three or more types of targets having a stable composition are simultaneously formed. The InGeSbTe film 19a can also be formed by sputtering.

As an example, an InGeSbTe film 19a is formed by simultaneously sputtering a first target composed of a GeTe compound, a second target composed of an SbTe compound, and a third target composed of an InTe compound. You can also In this case, a compound having a composition that can be expressed by GeTe (composition ratio = 1: 1) is used as the GeTe compound having a stable composition. In addition, a compound having a composition that can be expressed as Sb 2 Te 3 is used as the SbTe compound having a stable composition. As the InTe compound having a stable composition, the above-described compounds (In 2 Te 3 , In 4 Te 3 , InTe, In 3 Te 4 , In 3 Te 5 , In 2 Te 5 ) can be used.

When the first to third targets are attached to the three cathode electrodes (for example, 108a to 108c) of the sputtering chamber 101 shown in FIG. 9, the W target 109b or the remaining one cathode electrode (for example, 108d) A film is formed by attaching any of the Ta targets 109c. For example, when the W target 109b is attached to the remaining one cathode electrode, the tantalum oxide (Ta 2 O 5 ) film constituting the interface layer 18 may be separately formed using a CVD apparatus.

  In addition, as shown in FIG. 19, the InGeSbTe film 19a can be formed using a sputtering apparatus provided with three cathode electrodes (108a, 108b, 108c) in the sputtering chamber 101. In this case, the first to third targets (InTe target 109d, GeTe target 109e, SbTe target 109f) having the above-described stable composition are attached to the cathode electrodes (108a, 108b, 108c) and simultaneously sputtered. Alternatively, two types of targets having a stable composition (GeSbTe target 109a and InTe target 109d) are attached to two cathode electrodes, and either the W target 109b or the Ta target 109c is attached to the remaining one cathode electrode. Membranes can also be performed.

(Embodiment 2)
In the first embodiment, the amount of discharge gas mixed into the InGeSbTe film 19a is reduced by using a rare gas element having a mass larger than that of Ar as the discharge gas. However, the InGeSbTe film is deposited by sputtering. In this case, the amount of discharge gas mixed into the InGeSbTe film can be reduced by increasing the temperature of the substrate 1 (wafer).

  That is, in this embodiment, when the InGeSbTe film is formed using the sputtering apparatus 100 shown in FIG. 8, the temperature of the substrate 1 positioned on the wafer stage 106 of the sputtering chamber 101 shown in FIG. Film formation is performed at a temperature higher than that of Form 1.

  FIG. 20 is a graph showing a TDS analysis result of discharge gas (Ar) desorbed when six types of InGeSbTe films deposited at different temperatures of the substrate 1 are heat-treated. FIG. 21 is a graph showing the substrate temperature dependence of the discharge gas (Ar) desorption amount obtained from the TDS analysis result. From these graphs, it can be seen that the amount of discharge gas mixed into the InGeSbTe film can be reduced by forming the film with the temperature of the substrate 1 set to 100 ° C. to 250 ° C., preferably 150 ° C. to 200 ° C. .

  The reason why the amount of discharge gas mixed into the film is reduced when the substrate temperature is increased can be explained as follows. That is, when the substrate temperature is increased, the distance that the sputtered particles that have reached the substrate can move on the surface of the film is increased, and the film is denser because it is stabilized at a lower position in terms of energy. When the film is densified, the force of discharging the discharge gas (Ar) that cannot be chemically bonded to the constituent elements of the film is increased, and thus the amount of discharge gas mixed into the film is reduced. In this embodiment, the case where an InGeSbTe film is formed using Ar as a discharge gas has been described. However, the same applies to the case where an InGeSbTe film is formed using Kr or Xe as a discharge gas. Can do.

(Embodiment 3)
In the first embodiment, the amount of discharge gas mixed into the InGeSbTe film 19a is reduced by using a rare gas element having a mass larger than that of Ar as the discharge gas. However, the InGeSbTe film is deposited by sputtering. In this case, the amount of discharge gas mixed into the InGeSbTe film can be reduced by increasing the pressure (concentration) of the discharge gas.

  That is, in this embodiment, when forming the InGeSbTe film using the sputtering apparatus 100 shown in FIG. 8, the pressure of the discharge gas introduced into the sputtering chamber 101 shown in FIG. 9 is higher than that in the first embodiment. Set and perform film formation.

  FIG. 22 is a graph showing a TDS analysis result of the discharge gas (Ar) desorbed when the four types of InGeSbTe films deposited by changing the pressure of the discharge gas (Ar) in the sputtering chamber 101 are heat-treated. FIG. 23 is a graph showing the discharge gas pressure dependence of the discharge gas (Ar) desorption amount obtained from the TDS analysis result. From these graphs, it can be seen that the amount of discharge gas mixed in the InGeSbTe film can be reduced by forming the film with the discharge gas pressure set to 1 Pa or higher, preferably about 1.2 Pa to 2.4 Pa. .

This, the higher the pressure of the discharge gas, the cathode electrode 108a of the sputter chamber 101 shown in FIG. 9, the Ar + ion concentration in the plasma formed between the 108d and the wafer stage 106 increases, Ar + ions together This is because the amount of Ar that reaches the surface of the substrate 1 and is taken into the film decreases as a result of the increase in collision / scattering frequency.

  In this embodiment, the case where an InGeSbTe film is formed using Ar as a discharge gas has been described. However, the same applies to the case where an InGeSbTe film is formed using Kr or Xe as a discharge gas. Can do.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, it is possible to reduce the amount of discharge gas mixed into the InGeSbTe film by combining two or more discharge gas mixing prevention measures described in the first to third embodiments.

  Further, according to the present invention, when the InGeSbTe film constituting the memory layer is deposited by the sputtering method, the amount of discharge gas mixed in the film can be reduced, so that the conductive film for the upper electrode is formed on the InGeSbTe film. After depositing, when a heat treatment for crystallizing the InGeSbTe film is performed, a problem that voids are generated in the InGeSbTe film can be suppressed. Thereby, a phase change memory that exhibits excellent data retention characteristics even in a high temperature environment can be manufactured with a high yield.

  The present invention can be applied to manufacture of a phase change memory using a chalcogenide film as a memory layer.

Claims (13)

  1. A method of manufacturing a semiconductor memory device comprising a step of forming a memory layer for storing information on a semiconductor substrate by a difference in electrical resistance value accompanying a phase change, wherein the step of forming the memory layer comprises:
    (A) depositing a chalcogenide film made of indium, germanium, antimony and tellurium on the semiconductor substrate by a sputtering method using a rare gas having an atomic weight larger than argon as a discharge gas;
    Only including,
    The method of manufacturing a semiconductor memory device, wherein the discharge gas has a pressure of 1.2 Pa to 2.4 Pa .
  2.   2. The method of manufacturing a semiconductor memory device according to claim 1, wherein the rare gas is xenon.
  3.   2. The method of manufacturing a semiconductor memory device according to claim 1, wherein the rare gas is krypton.
  4. After the step (a),
    (B) depositing a conductive film for an upper electrode on the chalcogenide film;
    (C) a step of crystallizing the chalcogenide film by heat-treating the semiconductor substrate after the step (b);
    The method of manufacturing a semiconductor memory device according to claim 1, further comprising:
  5.   5. The method of manufacturing a semiconductor memory device according to claim 4, wherein the chalcogenide film and the conductive film are formed using the same sputtering apparatus.
  6.   5. The method of manufacturing a semiconductor memory device according to claim 4, wherein the conductive film is a tungsten film.
  7.   2. The method of manufacturing a semiconductor memory device according to claim 1, wherein when forming the chalcogenide film by the sputtering method, a plurality of types of targets each made of a compound having a stable composition are used.
  8. A method of manufacturing a semiconductor memory device comprising a step of forming a memory layer for storing information on a semiconductor substrate by a difference in electrical resistance value accompanying a phase change, wherein the step of forming the memory layer comprises:
    (A) in a state wherein the coercive Chi the temperature of the semiconductor substrate to 100 ° C. to 250 DEG ° C., was Tsu holding the pressure of the discharge gas 1.2Pa~2.4Pa, indium on said semiconductor substrate, germanium, antimony and tellurium Depositing a chalcogenide film by sputtering,
    A method for manufacturing a semiconductor memory device, comprising:
  9.   The method of manufacturing a semiconductor memory device according to claim 8, wherein a more preferable temperature of the semiconductor substrate is 150 ° C. to 200 ° C.
  10. After the step (a),
    (B) depositing a conductive film for an upper electrode on the chalcogenide film;
    (C) a step of crystallizing the chalcogenide film by heat-treating the semiconductor substrate after the step (b);
    The method of manufacturing a semiconductor memory device according to claim 8, further comprising:
  11. The sputtering method, as the discharge gas, a method of manufacturing a semiconductor memory device according to claim 8, wherein the use of argon.
  12. A method of manufacturing a semiconductor memory device comprising a step of forming a memory layer for storing information on a semiconductor substrate by a difference in electrical resistance value accompanying a phase change, wherein the step of forming the memory layer comprises:
    (A) depositing a chalcogenide film made of indium, germanium, antimony and tellurium on the semiconductor substrate by a sputtering method in a state where the pressure of the discharge gas is maintained at 1.2 Pa to 2.4 Pa ;
    A method for manufacturing a semiconductor memory device, comprising:
  13. After the step (a),
    (B) depositing a conductive film for an upper electrode on the chalcogenide film;
    (C) a step of crystallizing the chalcogenide film by heat-treating the semiconductor substrate after the step (b);
    The method of manufacturing a semiconductor memory device according to claim 12, further comprising:
JP2008537343A 2006-09-29 2006-09-29 Manufacturing method of semiconductor memory device Expired - Fee Related JP5061113B2 (en)

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JPH06333275A (en) * 1993-02-22 1994-12-02 Matsushita Electric Ind Co Ltd Optical information recording medium and its production
JP2005117030A (en) * 2003-09-17 2005-04-28 Mitsubishi Materials Corp Phase-change film for semiconductor nonvolatile memory, and sputtering target for forming the film
WO2005112118A1 (en) * 2004-05-14 2005-11-24 Renesas Technology Corp. Semiconductor memory
JP2006156886A (en) * 2004-12-01 2006-06-15 Renesas Technology Corp Semiconductor integrated circuit device and manufacturing method therefor

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Publication number Priority date Publication date Assignee Title
JPH06333275A (en) * 1993-02-22 1994-12-02 Matsushita Electric Ind Co Ltd Optical information recording medium and its production
JP2005117030A (en) * 2003-09-17 2005-04-28 Mitsubishi Materials Corp Phase-change film for semiconductor nonvolatile memory, and sputtering target for forming the film
WO2005112118A1 (en) * 2004-05-14 2005-11-24 Renesas Technology Corp. Semiconductor memory
JP2006156886A (en) * 2004-12-01 2006-06-15 Renesas Technology Corp Semiconductor integrated circuit device and manufacturing method therefor

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