WO2007149676A3 - Method for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates - Google Patents

Method for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates Download PDF

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Publication number
WO2007149676A3
WO2007149676A3 PCT/US2007/069709 US2007069709W WO2007149676A3 WO 2007149676 A3 WO2007149676 A3 WO 2007149676A3 US 2007069709 W US2007069709 W US 2007069709W WO 2007149676 A3 WO2007149676 A3 WO 2007149676A3
Authority
WO
WIPO (PCT)
Prior art keywords
temperature
select gates
word lines
compensated
voltages
Prior art date
Application number
PCT/US2007/069709
Other languages
French (fr)
Other versions
WO2007149676A2 (en
Inventor
Nima Mokhlesi
Dengtao Zhao
Original Assignee
Sandisk Corp
Nima Mokhlesi
Dengtao Zhao
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/424,812 external-priority patent/US7342831B2/en
Priority claimed from US11/424,800 external-priority patent/US7391650B2/en
Application filed by Sandisk Corp, Nima Mokhlesi, Dengtao Zhao filed Critical Sandisk Corp
Publication of WO2007149676A2 publication Critical patent/WO2007149676A2/en
Publication of WO2007149676A3 publication Critical patent/WO2007149676A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification

Abstract

Reading and verify operations are performed on non-volatile storage elements using temperature-compensated read voltages for unselected word lines, and/or for select gates such as drain or source side select gates of a NAND string. In one approach, while a read or verify voltage is applied to a selected word line, temperature-compensated read voltages are applied to unselected word lines and select gates. Word lines which directly neighbor the selected word line can receive a voltage which is not temperature compensated, or which is temperature-compensated to a reduced degree. The read or verify voltage applied to the selected word line can also be temperature-compensated. The temperature compensation may also account for word line position.
PCT/US2007/069709 2006-06-16 2007-05-25 Method for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates WO2007149676A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/424,812 US7342831B2 (en) 2006-06-16 2006-06-16 System for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates
US11/424,800 2006-06-16
US11/424,812 2006-06-16
US11/424,800 US7391650B2 (en) 2006-06-16 2006-06-16 Method for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates

Publications (2)

Publication Number Publication Date
WO2007149676A2 WO2007149676A2 (en) 2007-12-27
WO2007149676A3 true WO2007149676A3 (en) 2008-03-13

Family

ID=38834211

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/069709 WO2007149676A2 (en) 2006-06-16 2007-05-25 Method for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates

Country Status (2)

Country Link
TW (1) TWI336081B (en)
WO (1) WO2007149676A2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020109539A1 (en) * 1999-07-22 2002-08-15 Kabushiki Kaisha Toshiba Multi-level non-volatile semiconductor memory device with verify voltages having a smart temperature coefficient
US20020159315A1 (en) * 2001-03-29 2002-10-31 Kabushiki Kaisha Toshiba Semiconductor memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020109539A1 (en) * 1999-07-22 2002-08-15 Kabushiki Kaisha Toshiba Multi-level non-volatile semiconductor memory device with verify voltages having a smart temperature coefficient
US20020159315A1 (en) * 2001-03-29 2002-10-31 Kabushiki Kaisha Toshiba Semiconductor memory

Also Published As

Publication number Publication date
WO2007149676A2 (en) 2007-12-27
TW200805382A (en) 2008-01-16
TWI336081B (en) 2011-01-11

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