TW200805382A - System and method for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates - Google Patents

Abstract

Reading and verify operations are performed on non-volatile storage elements using temperature-compensated read voltages for unselected word lines, and/or for select gates such as drain or source side select gates of a NAND string. In one approach, while a read or verify voltage is applied to a selected word line, temperature-compensated read voltages are applied to unselected word lines and select gates. Word lines which directly neighbor the selected word line can receive a voltage which not temperature compensated, or which is temperature-compensated to a reduced degree. The read or verify voltage applied to the selected word line can also be temperature-compensated. The temperature compensation may also account for word line position.

Description

200805382 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to non-volatile memory technology. [First as technology]

Half-body § recalls are increasingly used in a variety of electronic shocks. For example, non-volatile semiconductor memory can be used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, or other devices. Electrically erasable and programmable eeprom and flash memory are among the most popular non-volatile semiconductor memories. Both the EEPROM and the flash memory use a floating gate 16 that is positioned above and insulates the channel region in the semiconductor substrate. The floating gate is positioned between the source region and the non-polar region. A control electrode is disposed above the floating gate and insulated from the floating electrode. The threshold voltage of the transistor is controlled by the amount of charge held on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to allow conduction between its source and drain is protected by the charge level on the floating gate. When stylized-EEPROM or flash memory devices (such as __ nand flash memory devices), a stylized voltage is typically applied to the control gate and the bit line is grounded. The electrons from the channel are injected into the floating gate. When the electrons accumulate in the floating gate, the grass sticks to the field, and the threshold is negatively charged and the threshold voltage of the storage element rises, thereby causing the storage of 70 pieces to be stylized. More information about stylization is available in ‘ % for Source Side Self

Boosting Technique for Non-Vni +·ι a.

Volatile Memory, U.S. Patent No. 1, 218, 185, filed to s. s. s. s. s. </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; The EEPROM and flash memory device have a floating gate for storing two charge ranges, and thus, the memory element can be programmed/erased between two states (eg, an erased state and a -stylized state). Such a flash memory device has a device called a flash memory device. A multi-state flash memory device identifies a plurality of different allowable/effective stylized thresholds separated by prohibited ranges. The voltage range is constructed. Each of the different threshold voltage ranges corresponds to a predetermined value in the set of data bits encoded by the device. The non-volatile 5 memory device (such as Nand) In flash memory devices, temperature changes can cause various reading and writing data to be subjected to varying temperatures based on their environment. For example, some existing brothers It is considered to be used in conjunction with. Industrial, military, and even consumer applications can experience significant temperature changes. Temperature affects many transistor parameters, the most important of which is the threshold pressure. Temperature changes can cause read errors and widen the threshold voltage distribution of different states of the non-volatile storage element. Currently, temperature changes are compensated for by taking into account the temperature change of the threshold voltage of the storage element. In this way, the read/verify voltage applied to the selected word line is changed. This method can solve at most the average offset problem of the threshold voltage distribution of the storage element. For the sake of simplicity, it is assumed that the threshold voltages are all in the same lean state. However, there is a need for an improved technique to further reduce the expansion of the per-electrical distribution of each of the states due to temperature changes of the 121I85.doc 200805382. [Invention] The present invention provides for operation Non-volatile storage systems and methods to address these and other problems in which temperature compensated electrolysis is applied to non-selective non-volatile The present invention achieves various benefits 'including improved read and write performance. In the -K (8) example, the non-volatile memory is operated by: first voltage ( For example, a read or verify voltage is applied to a select word line t to determine a stylized state of the first non-volatile storage element associated with the selected word line. The first non-volatile storage element is disposed in a group Non-volatile storage in a 7C piece. For example, the first electric dust may be a read voltage, which is a stabilizing state after reading the first non-volatile storage element after its stylization. Or, the first The voltage can be a verification voltage that is used to verify that the first non-volatile storage element has reached the desired stylized state. For example, such verification power can be applied to a series of such programmed pulsations of such pulsations. between. Moreover, while applying the first voltage, a temperature-compensated electrode is applied to one or more non-selected word lines associated with the non-volatile storage element group. In one method, the same temperature compensated voltage is applied to each of the non-selected word lines. In another method, different temperature compensated voltages are applied to different non-selected word lines. In the re-method, one or two unselected word lines directly adjacent to the selected word line receive an amount that is not temperature compensated or temperature compensated by a decrease (relative to the temperature applied to other unselected word lines) The voltage of the compensation voltage). A voltage compensated by temperature 121185.doc 200805382 may also be applied to the source and/or the poleless selection, such as when the selected non-volatile storage element is in a NAND string. The first voltage can also be temperature compensated. ^ In her example, the non-volatile storage benefit is applied by applying a -first voltage to a selected word line to determine a program of the first non-volatile storage element associated with the selected word line. State. The first non-volatile storage element is disposed in the set of non-volatile storage elements. In addition, the first electrical a is temperature compensated according to a relative position of the selected word line in a plurality of word lines associated with the set of non-volatile storage elements. For example, a larger temperature compensation magnitude can be used when the selected word line is closer to the pole than the source of the block comprising the plurality of word lines. In another embodiment, the non-volatile storage is operated by applying -first to a selected word line to determine a first non-volatile storage element associated with the selected word line. a stylized state in which the first-non-volatile age component is disposed in the _ group of non-volatile storage elements. At the same time as the first electromigration is applied, 'the temperature-compensated electricity is applied to at least- The first-non-selected word line associated with the volatile storage element. In addition, 'when the first-th power is applied, the amount is reduced without temperature compensation or temperature compensation--relative to the application to (four)-non-line The temperature compensated voltage is applied to at least one of the non-selected word lines associated with the set of non-volatile storage elements. In the method, the 'less-first-non-selected word lines are not directly adjacent to the selection Word line, and the to;: A first unselected word line is directly adjacent to the selected word line. In the re-addition case, the non-volatile storage is operated by the following method. 121185.doc 200805382: a first Applying a voltage to a selected word line to determine a phase associated with the selected word j The stylized state of the non-volatile storage element, wherein the non-volatile storage element is disposed in a set of non-volatile storage elements. The field/non-volatile storage element is not directly adjacent to the selection gate Applying a first temperature-compensated voltage to the selected gate associated with the second non-volatile storage element while applying the first voltage of the first pass; when the first volatile storage element is directly adjacent to the select gate At the very extreme, applying a voltage that is not temperature compensated or temperature compensated by a decrease (relative to the first temperature compensated voltage) is applied to the selection gate while the first private is being applied The pole and the first non-volatile storage element can be disposed in a NAND string, wherein the select gate is on the source or drain side of the NAND string. Provided for operating non-volatile memory and non-volatile storage A system of non-volatile storage systems such as &quot;&quot;Hai includes a set of non-volatile storage elements or circuits for operating the non-volatile storage element group as described herein. [Embodiment] ^月Offer - used for A system and method for improving read and write performance in a method of operating, failing, and modifying. The improved performance is achieved by applying a voltage of ''reserved' to the non-selective non-volatile storage gate. Achieved. 亘鹖〆忐π' ^ Included · Reduced reading interference, the reduction between the eight evils ▲ Several 铪, due to the use of larger stylized steps ^ or Hunting by the state compression An operational window that is closer together and reduced. 121185.doc -10- 200805382 An example of a memory system suitable for use in constructing the present invention uses a NAND flash memory structure that includes a plurality of transistors arranged in series Between the two selected gates, the series transistors and the select gates are referred to as a NAND string. Figure 1 is a top view showing a NAND string. Figure 2 is an equivalent circuit of the NAND string. The NAND strings illustrated in Figures 1 and 2 include four connected in series and sandwiched between a first select gate 120 and a second select gate 122.

The transistors 100, 102, 104 and 106. Select gate 120 strobes the NAND string connections to bit line 126. Select gate 122 strobes the NAND string connection to source line 128. The selection gate 120 is controlled by applying a suitable voltage to the control gate 12?cg. The selection gate 122 is controlled by applying a suitable voltage to the control gate 122C (}. Each of the transistors 1〇〇, 1〇2, 1〇4, and 1〇6 has a control gate and A floating gate. The transistor 1 has a control gate 100CG and a floating gate i〇〇FG. The transistor 102 includes a control gate 102CG and a floating gate 102FG. The transistor 1〇4 includes a control gate 104CG and a floating gate. Gate i〇4FG. The transistor 1〇6 includes a control gate 1〇6Cg and a floating gate 106FG. The control gate i〇〇CG is connected to (or is) the word line WL3, and the control gate 102〇(} is connected to The word line WL2, the control gate i〇4ce is connected to the word line WL1, and the control gate 106CG is connected to the word line w1〇. In an embodiment, the transistors 100, 102, 104 and 1〇6 are all storage elements. Also referred to as a memory unit. In other embodiments, the storage element may comprise a plurality of transistors, or may be different from that illustrated in Figure 4. Select gate Η. Connect to select line SGD. Select gate 122 is connected to Select line SGS. Figure 3 provides a cross-sectional view of the above NAND string. As shown in Figure 3, the transistor in the NAND string is formed in p-well 14〇. Each transistor is packaged 121185.doc 200805382 includes a stacked gate structure consisting of a control gate (100CG, 102CG, 104CG, and 106CG) and a floating gate (100FG, 102FG, 104FG, and 106FG). The control gates and floating gates are typically formed by depositing polycrystalline seconds. The floating gates are formed on the surface of the P-well on top of an oxide film or other dielectric film. The control gate is floating. Above the gate, an intermediate polysilicon dielectric layer separates the control gate from the floating gate. The control gates of the storage elements (100, 102, 104, and 106) form word lines. N+ doped diffusion regions 13〇, I32 , 134, 136 and 138 are shared between adjacent storage elements,

Thereby the storage elements are connected in series to each other to form a NAND string. The N+ doped regions form the source and drain of each of the storage elements. For example, the N+ doping region 130 serves as the drain of the transistor 122 and the source of the transistor 106, and the N+ doping region 132 serves as the drain of the transistor 1〇6 and the source of the transistor 1〇4. The N+ doping region 134 is used as the drain of the transistor 104 and the source of the transistor 1〇2, and the N+ doping region 136 is used as the drain of the transistor 1〇2 and the source of the transistor 1〇〇, and N+ Doped region 138 is used as the drain of the transistor 1 及 and the source of the transistor 12 。. N+ doped region 126 is connected to the bit line of the NAND string while n+ doped region 丨28 is connected to one of the plurality of NAND strings to share the source line. Note that although Figure I-3 shows four storage elements in a NAND string, the use of four transistors is only an example. An example NAND string for use in one of the techniques described herein may have fewer than four memory storage elements or more than four storage elements. For example, some NAND strings will include 8, b, 32, or 64 storage elements. The discussion herein is not limited to any particular number of storage elements in a NAND string. Bamboo stocks Each storage element can be stored in analogy or in digital form. 121185.doc 200805382 Material. When storing the digits of one bit, the possible threshold of the storage component is divided into two ranges 'The two ranges are assigned to (4) the data "1" and "〇". In a NAND type In the example of flash memory, the threshold voltage is negative after the storage element is erased and is defined as logic &quot;i&quot;. And after a stylized operation, the threshold voltage is positive and defined as logic &quot;0, When the threshold voltage is negative and a read is attempted by applying 0 volts to the control gate, the bank 2 component will conduct to indicate that the logic 正 is being stored. When the threshold voltage is positive and the hunter is applied to the control gate When squatting to try a read operation, the storage element will not be turned on. This indication stores the logic 〇. : The storage element can also store multiple states 'by storing multiple digital data bits. In this case, the threshold voltage window is divided into multiple states. For example, if four states are used, four threshold voltage ranges are assigned to the data values "U,,," 1〇", &quot;〇1, , and &quot;(10)&quot;. In an example of a NAND type memory, the threshold voltage is negative after the erase operation and is defined as "11". Use the positive threshold for the status "1〇", "〇1,, and"〇〇&quot;. In some embodiments, a Gray code assignment scheme is used to assign a data value (eg, a logic state) to a threshold range such that if a threshold voltage of a floating gate is erroneously shifted to its neighboring physical state , it will only affect the single digit 7L. (4) The threshold for the storage of the components of the storage device. The specific relationship between the voltage ranges depends on the data coding scheme used by the storage components. For example, U.S. Patent No. 6,222,762 and claimed on June 13th of the year of the test, and 标 CCells F〇r A Me, 7 SyStem, US Patent Application No. 1/〇, 461, No. 244 describes various data encoding schemes for multi-state flash memory components, both of which are incorporated herein by reference in their entirety. (4) Examples of flash memory and its operation' ~ There are ways to use these US patents/special shots in this article: US Patent No. 5, No. 315; US Patent No. 5,774,397; U.S. Patent No. 5,386,422; U.S. Patent No. 6,456,528; and U.S. Patent No. 6,522,58. In addition to NAND flash memory, other types of non-volatile memory can be used in the present invention. Another type of storage element of a flash EEPROM system utilizes a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner. Such a storage element is described in a by Chan et al.文旱&quot;A True S ingle-Transistor 〇xide-Nitride_Oxide EEPROM Device),, (IEEE Electr〇nDevice (10), ed. &quot; Volume, Νο. 3, March 1987, pp. 93-95). The three layers of dielectric formed by the ruthenium oxide and ruthenium oxide (&quot;ΟΝΟ) are sandwiched between a conductive control gate and a surface of the semiconductive substrate above the channel of the storage element. The germanium storage element is programmed by injecting electrons into the nitride from the channel of the storage element, wherein the electrons are trapped and stored in a limited area. The stored electrical street then changes the threshold voltage of a portion of the channel of the storage element in a detectable manner. The storage element is erased by injecting a thermal cavity into the nitride. See also "A EEPR〇m with MONOS Memory Cell for Semiconductor Disk" by Nozaki et al.

Application (IEEE Journal of Solid-State Circuits), Vol. 26, Νο. 4, April 1991, pp. 497-501), which describes a split gate structure with 121185.doc •14-200805382 to similar storage elements A doped polysilicon gate extends over a portion of the channel of the storage element to form a separate select transistor. Both of the above articles are incorporated herein by reference in their entirety. The stylization techniques mentioned in the section "'Nonvolatile Semiconductor Memory Technology" by William D. Brown and Joe E. Brewer (IEEE Press, 1998) 1.2 are also described in the section as applicable to dielectric-electric Charge trapping device, which is incorporated herein by reference. The present invention also uses the storage elements described in this paragraph. Thus, the techniques described herein are also applicable to the coupling between dielectric regions of different storage elements. Another method for storing two bits in each storage element has been described by Eitan et al. in 'NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell'' (IEEE Electron Device Letters), Volume 21, No. 11, November 2000, pp. 543-545. A dielectric layer extends across the channel between the source diffusion region and the drain diffusion region. The dielectric material of the other data bit is localized in the dielectric layer adjacent to the source. The multi-state data storage system reads the dielectric space by reading the dielectric space. The binary state of the separate charge storage regions is implemented. The storage elements described in this paragraph can also be used in the present invention. Figure 4 illustrates an example of an array of such NAND storage element arrays as shown in Figures 1-3. Each row, a bit line 206 is coupled to the drain terminal 126 of the drain select gate of the NAND string 150. Along each column of the NAND string, a source line 204 can be connected to the source select gate of the NAND string. Examples of the operation of a ναν〇 architecture array and a uniform portion can be found in U.S. Patent Nos. 5,570,315, 5,774,397, and 121,185, doc -15-200805382 6,046,935. Recall that the array of storage elements is divided into a large number of storage flash EEPROMs. Usually for fast έ, the block is the erase unit. It can be replaced by ^ k η , Ρ 'each block is divided A small number of storage elements are divided into several pages. The page is a stylized unit. The two blocks are usually divided into individual segments, and the stomach can be used as a basic process.

The minimum number of storage elements known as a write once /φ φ ^ . I A list of storage elements 仵中通七 stores one or more data pages. One or more ^, can store one or feather &amp; One sector includes user data and i甬堂白红分4 is taken from Bellow. The overhead data I $ includes an error correction code (ECC) from the user data of the sector, ϋΟΡ, _L #. One part of the controller (described below) can only be programmed to calculate the ECC in the array, and it is also checking the ECC from the array &quot; 卞~. Alternatively, store Ecc and/or other overhead data in a different page than the user profile to which it belongs. A user data sector is typically 512 bytes and is equivalent to the size of a sector within the disk drive. The overhead data is usually ^16-20 bytes appended. A large number of pages form a block, for example from a tamping page (for example) up to 32, 64, 128 or more wτ # 曲曲不4. In some embodiments, a column of NAND strings includes one block. In one embodiment, the ρ·well is raised to an erase voltage (eg, 20 volts) by a source line and a bit line, and the ρ·well is raised to an audible period and a selection is made. The word line of the block is grounded to erase the memory storage element Du Dinger. Due to capacitive coupling, the unselected word lines, bit lines, select lines, and source 0 are also raised to 121185.doc -16- 200805382 = a small portion of the electric castle. Thus, when the _strong. electric field is applied to the doping mechanism to emit the electrons of the floating idler to the substrate side, the data of the selected storage device is erased. When the electrons are transferred from the floating gate to (4), the threshold voltage of the selected storage element is lowered. Erasing can be performed on a single block of the entire memory array or a storage element of another unit. Figure 5 illustrates a memory device having read/write circuits for parallelizing one of the pages of the storage element in accordance with one embodiment of the present invention. Memory device 296 can include one or more memory dies (10). The memory die 298 includes a two-dimensional array of storage elements 3, a control circuit 310, and a term fetch/write circuit. In some embodiments, the array of storage elements can be three dimensional. The memory array 3 can be addressed by the word line by the column decoder 330 and by the bit line by the line decoder. The read/write circuit 365 includes a plurality of sense blocks and allows one page of storage elements to be read or programmed in parallel. Typically, a controller 350 is included in the same memory device 296 (e.g., a removable memory card) in the form of one or more memory die 298. Commands and data are transferred between the host and controller 350 via line 32 and between the controller and one or more memory dies 298 via line 318. Control circuit 310 cooperates with read/write circuit 365 to perform memory operations on memory array 300. The control circuit 31 includes a state machine 312, an on-chip address decoder 314, a temperature compensation control 315, and a power control module 316. The temperature compensation control 3 15 will be further explained below in particular in conjunction with FIG. State machine 3 12 provides wafer level control of memory operations. Wafer 121185.doc 200805382 The dead address decoder 314 provides an address interface between the address used by the host or memory controller and the hardware address used by the decoders 330 and 360. Power control module 316 controls the power and voltage supplied to the word lines and bit lines during memory operation. In some embodiments, certain components of Figure 5 can be combined. In a different design, one or more of the components of Figure 5 (alone or in combination) other than storage element array 300 can be considered a management circuit. For example, one or more management circuits may include control circuit 31, state machine 312, decoder 3 14/360, power control 316, sense block 4, read/write circuit %^ control to 3 Any of the 50 or any combination thereof. FIG. 6 illustrates another arrangement of the memory device 296 shown in FIG. The access of the various peripheral circuits to the memory array 300 is performed in a symmetrical form on the opposite side of the array J, thereby halving the density of the access lines and circuits on each side. Therefore, the column decoder is split into column decoders 330A and 330B, and the row decoder is split into row decoders 36A and 36B. Similarly, the read/write circuit is split into a read/write circuit 365A connected from the bottom of the array 300 to the bit line and a read/write circuit 365B connected from the top of the array 300 to the bit line. In this way, the density of the read/write modules is substantially halved. The apparatus of Figure 6 can also include a controller as described above with respect to the apparatus of Figure 5. Figure 7 is a block diagram of an additional sensing block 400 that is partitioned into a core portion called a sensing module 380 and a shared portion 39A. In one embodiment, each bit line will have a single sensing module 38 and a plurality of sensing modules 380 will have a common portion 390. In one example, a sense 121185.doc •18· 200805382 test block will include a common portion 390 and eight sensing modules 380. Each of the sensing modules in a group communicates with an associated shared portion via a data bus 372. For further details, reference is made to U.S. Patent Application Serial No. </RTI> </RTI> </RTI> </RTI> <RTIgt; </RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; The manner of reference is incorporated herein.

Sensing module 380 includes a sensing circuit 370 that determines whether the conductive current in a connected bit line is above or below a predetermined threshold level. Sensing module 380 also includes a bit line latch 382 for setting a voltage state on a connected bit line. For example, latching in a predetermined state in bit line latch 382 will cause the connected bit line to be pulled to a specified stylized inhibit state (e.g., Vdd). The boring tool 390 includes a processor 392, a set of data latches 394 coupled to the ι/〇 = outer 6 between the data latch 394 group and the data bus 32 〇. Processor 392 performs the calculations. For example, one of its functions is to store the material stored in the sensed storage element and to stabilize the determined data in the lean (four) memory data latch 394 group for storage in the read; 392 identified data bits. It is also used to store the data bits input from the data bus 320 during the i-times. The input "L" element indicates the writer's data to be programmed into the memory. The 1/0 interface 1 provides a interface between the Beckey latch 394 and the data bus 32 (). During the lower item fetch or sensing period, the operation of the system is in the state machine 3i2 control, and the 6-Hai state machine control supplies the different control gates to the stored address j^21185.doc -19-200805382 storage element. When the sensing module 380 steps through a variety of predetermined control gate voltages corresponding to various memory states supported by the memory, it can trip under 4 turtles C and a round by bus bar 3 7 2 The sensor module (4) is supplied to the processor 392. At this time, the processor 392 determines the result memory state by considering the trip event of the sensing module and the information about the (four) gate voltage applied by the state machine 393 from the state machine. Then it will be different. The binary state of the memory state is stored in the data latch 394. In another embodiment of the core portion, the bit line latch 382 has a double turn, that is, the latch for latching the output of the sense core group 380 can also function as described above. Latches. Some embodiments will include multiple processors 392. In one embodiment, 'per-processor 392 will include an output line (which is not shown in the figure = making each of the far output lines connected by &quot; or &quot; together. Inverting the output lines before connecting to the "or" line of the connection. - When a stylization process is made during the stylization verification process, which is due to the status of the received connection &quot; or &quot; The machine can determine... when the stylized bit reaches the desired level. For example, when the state is at the level it expects, the bit-logic of the bit outputs the 222 line or the line. (or reverse the data υ ° when all the bits of the material 〇 (or reverse the data η pull process. Because -,, ', 彳 the state machine knows to terminate the program-like off-machine / processor and 8 sense modules Group communication, so the sorrow, the machine needs to add logic to the connection 392 to read 8 times, or to process, ,, correlate the result of the bit line to make the state machine only 121185.doc -20 - 200805382 A read of the connected "or" line is required. Similarly, by correctly selecting the logical level, all The state machine can detect when the first bit changes its state and change the algorithm accordingly. During the stylization or verification, the data to be programmed is stored in the data latch 394 from the data bus 320. Under state machine control, the stylization operation involves applying a series of programmed voltage ripples to the control gate of the addressed storage element. After each program pulse is read back (verified) to determine if the storage element has been programmed into a The desired memory state. The processor 392 monitors the memory state read back relative to the desired memory state. When the two match, the processor 222 sets the bit line latch 214 to pull the name line. The state of the stylization inhibit is specified to a state that prohibits the storage element coupled to the 7G line from being further programmed, even when the programmed ripple occurs on its control gate. In other embodiments, the processor is initially The bit line latch 382 is loaded and the sense circuit sets the latch to a disable value during the verify process. /(4) The memory H stack 394 includes - corresponding to the sense module Data latches, and in the only embodiment, each sensing module 380 has three data latches. In some embodiments (but not required), the data latching cry is implemented as a shift The temporary storage 11 converts the parallel data stored therein into: serial data of the bus bar 320, and vice versa. In the preferred embodiment, the items corresponding to the m stored in the # memory can be taken. All data latches of the / write block are linked together to form a tap shift register state so that a data can be input or output by serial transport. In other words, r is used. A row of read/write rights groups, so that their assets, and the latches are latched into each group, and the data 121185.doc -21- 200805382 is sequentially moved into or out of the data bus, as if it were One part of the shift register for the entire read/write block is general. Additional information regarding the structure and/or operation of various embodiments of the non-volatile memory device can be found in the following patents: (1) U.S. Patent Application Serial No. 2004/0057287, issued March 25, 2004, &quot; -Volatile Memory And Method With Reduced Source Line Bias * Errors; (2) US Patent Application No. 2004/0109357, published on Jun. 10, 2004, 'Non-Volatile Memory And Method with Improved Sensing'; (3) U.S. Patent Application Serial No. 11/015,199, filed on Dec. 16, 2004, entitled &quot;Improved Memory Sensing Circuit And Method For Low Voltage Operation, by Raul-Adrian Cernea; (4) 2005 US Patent Application No. 11/099, 133, entitled "'Compensating for Coupling During Read Operations of Non-Volatile Memory", filed on April 5, the inventor is Jian Chen; and (5) December 28, 2005 U.S. Patent Application Serial No. U.S. Patent Application Serial No. Serial No. No. No. No. No. No. No. No. No.

Raul-Adrian Cernea. All five patent documents just listed above are incorporated herein by reference in their entirety. Referring to Figure 8, an exemplary structure of an array of storage elements 300 is illustrated. As an example, a NAND flash EEPROM with a partition of 1, 24 blocks is illustrated. The data stored in each block can be erased at the same time. In one embodiment, the block is simultaneously subjected to the smallest unit of the erased storage element. In each block, in this example, there are 8,512 corresponding to the bit line BL0, 121185.doc -22-200805382 ^ BL8511. In the λ example of all bit line (ABL) architectures, all bit lines of the block can be selected simultaneously during read and program operations. A storage element along a common word line and connected to any bit line can be programmed simultaneously. Figure 8 shows four storage elements connected in series to form a Nand string. Although the figure shows that four (four) memory elements are included in each _NAND string, it can also be used: - less than four storage elements (for example, 16, 32, "ones") The gate is selected from the drain gate, connected to the selected gate drain line SGD, and connected to a corresponding bit line, and the other terminal is connected to the source select gate (which is connected to the selected closed source line SGS). Connected to the ^ source. - In another embodiment called the parity structure, as shown in Figure 9, the bit lines are divided into even bit lines and odd bit lines. Figure 9 illustrates one will. An example of a block of a body array organized into an odd-even memory structure. In an odd-numbered/even-bit line architecture, a storage element along a common word line and connected to an odd bit line is simultaneously programmed, while in another time program A storage element along a common sub-line and connected to an even bit line. The data can be programmed into different blocks and the data can be read simultaneously from different blocks. In this κ case, there are 8,512 partitions. It is an even-numbered line and an odd-numbered line. The bit line is also a book] minute #一J刀成偶数线线(BLe) and odd Bit line (BLo). In this example, T is not connected in series to form a NAND string. The memory map includes four memory elements in each NAND string: however, it can also be used. More or less than four storage elements. During the construction of reading and stylization, select 4,256 121185.doc -23- 200805382

Save your mail. The selected storage elements have the same word line and the same type of bit line (e.g., even bit lines or odd bit lines). Therefore, 532 data bytes can be simultaneously read or programmed (which form a logical page), and: a memory block can store at least 8 logical pages (four word lines, each with a countable logical page) With even logical pages). For multi-state storage, when each storage element stores two data bits, each of which is stored in a different page, one block stores 16 logical pages. Blocks and pages of other sizes can also be used. For an ABL or parity architecture, the storage element can be used to erase the source line and the bit line floating by raising the well to an erase voltage (e.g., &lt; 2G volts) and grounding the word line of the -select block. You can install the entire memory array, a separate block, or the memory with $_立β八+ μ七_α. Another unit of the storage element of the clothing compartment is implemented to remove the floating gate of the electronic self-storing piece to the p-well zone to make the Vth of the storage element negative. In the read and verify operations, the select gates (SGD and SGS) are connected to a voltage between 2.5 volts and 4.5 volts and the unselected word lines (eg, when WL2 selects the word line), it is WLQ, WUawl3 ) Raise to - read through the electricity (usually - (4) in the range of 4.5 volts to 6 volts) to operate the transistor as a transfer gate. The selection word line WL2 is connected to the power, and the level of the electromigration is determined for each read and verify operation to determine whether the VTH of the associated memory element is above or below this level. For example, in a read operation of a pair of quasi-storage elements, the word line and ground can be selected to detect if the VTH is above the stagnation. The select word line WL2 can be connected to, for example, 〇8 volts, 121185.doc •24-200805382 in a verify operation for two quasi-storage elements to verify that the vTH has reached at least 8 volts. The source and well are under crouching. The selected bit line (assumed to be an even bit line (BLe)) is precharged to a level of, for example, 〇·7 volts. If Vth is above the read or verify level on the word line, then the potential level of the bit line (BLe) associated with the storage element of interest maintains a high level due to the non-conductive storage element. On the other hand, if the Vth is lower than the read or verify level, the associated bit line (7) [the potential level of the uniformity will be lowered by the conductive storage element to discharge the bit line to, for example, less than 〇5 volts. The low level. Therefore, the state of the storage element is detected by a voltage comparison sense amplifier connected to the bit line. The above erase, read and verify operations are performed in accordance with techniques well known in the art. Therefore, those skilled in the art can change many of the details explained. Other erasing, reading and verifying techniques known in the art can also be used. Figure 10 illustrates an exemplary threshold voltage distribution of the array of storage elements as each storage element stores two data bits. A first threshold voltage distribution E of one of the erased storage elements is provided. It also shows the threshold voltage distribution A and BAC of the stylized storage element. In one embodiment, the L-limit voltage in the £ distribution is negative and the threshold voltage in the A, B &amp; C distribution is positive. Each of the different threshold voltage ranges corresponds to a predetermined value of the set of data bits. Stylized to the storage component: The specific relationship between the threshold voltage levels of the component is dependent on the data encoding scheme used for the storage component. For example, 'U.S. Patent No. 6,222,762 and (10) 4 years (10) ^, the United States specializes in the opening of the towel, please (4) complete 55_ to explain the data encoding scheme for each of the multi-equivalent flash memory storage components' two applications 121185. Doc-25·200805382 is incorporated herein by reference in its entirety. In an embodiment, the Gray code assignment scheme assigns a data value to the threshold voltage range so that if the threshold voltage of the second active erroneously erroneously shifts to its neighbor

Only one bit is affected. For example, a J example of a price for a threshold voltage range E (state e) means assigning a threshold voltage range A (state A) to &quot;1〇&quot;, assigning a range B (state B), 〇〇 ,,,$^ and 6 5 limit voltage range C (state C) assignment. In other embodiments, four states are not used, but the invention is also applicable to other polymorphic structures' including == structures that include more or less than four states. Three read reference MVra, Vrb and vrc are provided to retrieve data from the storage element (4). By testing - if the threshold of a given storage component is repeatedly above or below vmuw, the system can determine (4) what state the storage component is in. In addition, three verification references are provided, „vva, Vvwvve. When the storage elements are programmed to state eight, the system will test whether their storage has a threshold voltage greater than Vva or equal to Vva. When stored When the component is programmed to state B, the system will test whether the storage component has a power limit greater than or equal to Vvb. When the storage component is programmed = state C, the system will test whether the storage component has greater than or equal to The threshold voltage of Vvc. In the embodiment called full sequence programming, the self-erase state E of the memory component can be directly programmed to any of the stylized states A, 8 or f. 'You can first erase a population of staging storage elements so that all storage elements in the group are in the erased state e. Then, 121185.doc -26- 200805382 will be controlled by a series such as shown in Figure 13. The stylized pulsation depicted by the gate voltage sequence directly programs the storage element into state A, B, or C. When some storage elements are programmed from state E to state A, the other storage elements are programmed from state E to State B and/or from state E to state c. When staging from state E to state c on WLn, it maximizes the parasitic consumption of coupling to the adjacent floating gate of wLn-1. The amount of charge on the floating gate below WLn varies the most from the voltage change from state E to state A or from state E to state b. When staging from state E to sorrow B, coupling The coupling amount to the adjacent floating gate is reduced but still high. When the state E is programmed to state A, the coupling amount is further reduced. Therefore, the correction required for each state of WLn-Ι is subsequently read. The amount will vary depending on the state of the adjacent storage elements on WLn. Figure 11 illustrates an example of a two-pass technique for a stylized multi-state storage element that stores two different pages (the next page and the previous page) The four states are: state Ε (1ι), shape ^AdO), state B (〇〇), state c (〇1). For the state £, the two pages are stored 1 for white. State A, the next page stores a "〇" and the upper page stores a "1". For State B, both pages are stored "square ,,. For state c, save the file and save the page "”". Note that although a particular bit pattern is assigned to each of these states, a different bit pattern can be assigned. °, in the _, fish mouth, and privateization, according to the position to be programmed to the next logical page, the threshold voltage level of the storage element is 6 again. If the bit system is - T, the threshold voltage will not change because it is in the appropriate state due to the previous erasure of 121185.doc -27-200805382. However, if the bit to be programmed is $-logic "G", then the threshold level of the storage element is increased to become state A, as indicated by arrow U00. This will terminate the first pass of stylization. In the second pass stylization, the threshold voltage level of the storage element is set according to the bit in the normalized upper logical page. If the upper logical page bit wants to store a logical &quot;Γ, then no stylization will occur, because the storage component is viewed in the stylization of the next page bit and is in the state of £ or all of them are carried - One of the page bits &quot;n. If the upper logical page bit is to be - logical, 〇 &quot;' then the threshold voltage offset. If the first pass keeps the storage element in the erased state E, then in the second phase, the storage element is programmed to increase the threshold voltage to be in state c, as indicated by arrow 1120. . If the storage element has been programmed into state A as a result of the first programming, then the storage element is further programmed in the second pass to increase the threshold voltage to state 6 as indicated by arrow 1110. Drawn. The result of the second pass is that the storage element is to be programmed to store the logic of one of the pages &quot;〇&quot; without changing the state of the information on the next page. In Figure 10 and Figure u, the amount of coupling of the floating gate to the adjacent word line depends on the final state. In one embodiment, if a data sufficient to fill an entire page is to be written, then the system can be set to implement a full sequence of writers. If the enough data is written into an entire page, the stylization process can program the page with the received data. When the follow-up data is received, the system stylizes the page. In still another embodiment, the system can begin writing in a stylized page mode and if subsequently received enough to fill all of the 121185.doc -28 - 200805382 or most of the storage elements of the word line , then convert to full sequence stylized mode. Further details of this embodiment are disclosed in the "Pipe lined Programming of Non-Volatile Memories Using Early Data', filed on December 14, 2004 by the inventors Sergy A. Gorobets and Yan Li. In U.S. Patent Application Serial No. 13,125, the disclosure of which is incorporated herein in its entirety by reference.

12A-C disclose another process for staging non-volatile memory for any particular storage element by writing to a particular page associated with a particular page after writing an adjacent storage element for a previous page. Components to reduce the coupling effect of the floating gate to the floating gate. In an exemplary embodiment, the non-volatile storage element uses four data states to store two data bits for each storage element. For example, assume that the state is an erased state, while states A, B, and C are stylized states. Status £ store data u. State A stores data 〇1. State B stores data 1〇. Status c stores data 〇〇. This is an example of a non-Gray code, since both bits vary between neighboring states A and B. Other codes for data status to physical data status can also be used. Each data element stores two data pages. For the purpose of reference, these data pages are referred to as the upper page and the lower page; however, other marks may be assigned thereto. For state A, the upper page stores the bit 〇 and the next bit stores the bit 1 〇 for the plethora of P 百 on the page to store the bit 1 and the next page is stored in the bit 〇. Material state C, both pages store bit data I This stylized process is a two-step process. In the first step, the page is turned down. If the next page is to remain in the data, then the storage 2 state remains in the state £. If the arsenal is to be stylized to the cockroach, the library will store a threshold voltage of 121185.doc -29- 200805382 to program the storage component to state B. Thus, Figure 12A shows the stylization of the storage element from state e to state B. State B' is an intermediate state B. Therefore, the verification point is depicted as Vvb, Vvb, which is lower than Vvb. In one embodiment, after a storage element is programmed from state E to state W, the NAND string is Its adjacent storage element (WLn+1) will be programmed in relation to its next page. For example, referring back to Figure 2, after the page below the stylized f.x storage element 1〇6, the lower page of the storage element 104 will be programmed. After the staging of the storage element 104, if the storage element 1〇4 has a threshold voltage from the state of the first to the state B', the coupling effect of the floating gate to the floating gate will increase the view of the storage element 106. At the threshold voltage. This will have the effect of widening the threshold voltage distribution of the sorrow B' to the threshold voltage distribution depicted by the threshold voltage distribution 1250 of Figure 12B. When the page is stylized, the apparent widening of the threshold voltage distribution will be corrected. Figure 12C, , and show the process of simplification of the upper page. If the storage element is in the erasing state E and the upper page remains at 1, the storage element will remain in the state E. If the storage element is in the state, and the page information on it is to be programmed to 〇, then the storage The threshold voltage of the component will rise so that the storage element # is in state A. If the storage component is in the intermediate threshold voltage distribution (10) and the upper page data is to be maintained, the health component will be programmed to The most, , and ς state B. If the storage element is in the middle threshold voltage distribution and the upper page data is to be changed to data 则, the threshold private pressure of the storage element will be raised to make the storage element in the state c. The process illustrated by the figure reduces the effect of the floating gate to the floating pole. This is 121185.doc -30- 200805382 because the page is stylized only on the storage element and the apparent storage limit of a given storage element The voltage has an effect. An example of an alternate state code is when the page data system 1 is moved from the distribution 1250 to the state C, and moves to the state B when the upper page data is 。. Although FIG. 12A-C provides a Information And examples of two data pages, but the concepts taught in Figures 12A-C can also be applied to other embodiments having more or less than four states and different from two pages. Figure 13 shows a voltage waveform 13〇〇 And comprising a series of stylized pulses 131, 132, 133, 1340, 1350, ... applied to a word line selected for stylization. In one embodiment, the programmed pulses have a voltage Vpgm The voltage begins at 12 volts and is incremented by, for example, 0.5 volts for each successive stylized pulsation until a maximum of 2 volts is reached. Between these programmed pulsations, the pulsing groups 1312, 1322 are verified. 1332, 1342, 1352, ... In some embodiments, each data can be programmed to have a verification pulse. In other embodiments, there may be more or less verification pulses. The verification pulse can have amplitudes such as Vva, Vvb, and Vvc (Fig. 1A). In one embodiment, the data is threaded along a common word to the storage element. Therefore, before applying the program pulse , select these word lines The word line will be referred to as a selected word line. The remaining sub-line in a block is called a non-selected word line. The selected word line can have one or two adjacent word lines. If the selected word line has two adjacent lines The word line, the adjacent word line on the drain side is referred to as the drain side adjacent word line and the adjacent word line on the source side is referred to as the source side adjacent word line. For example, if FIG. 2iWL2 selects the word line, 121185.doc -31- 200805382 is the source side adjacent word line and the WL3 system side is adjacent to the word line. Each storage element block includes a set of bit lines forming a row and a set of word lines forming a column. - real _ towel, the bit line system 4 彳 is divided into odd bit lines and even bit lines. At the same time, stylized along a common word line and connected to the storage elements of the odd bit line, and stylized at another time A storage element ("odd/even stylized n") along a common word line and connected to even bit lines. In another embodiment, the storage elements ("all bits are threaded") are threaded along a word for all of the bit lines in the block. In other embodiments, the bit lines or blocks may be decomposed into other groups (e.g., left and right groups, more than two groups, etc.). Figure 14 illustrates a threshold voltage as a function of temperature and word line position. Line 1410 represents the relationship of temperature coefficient to word line position. Line 142 〇 represents the ratio of the threshold voltage change to the temperature change (ΔντΓΟ versus word line position, where Vread is the temperature compensation for the voltage applied to the unselected word line. In this case, the temperature dependence is reduced. Although the dependence of the position of a word line is reduced, the dependency dependence of the position of the sub-line still exists. The line 丨43〇 indicates the relationship of (AVt〆C) to the position of the sub-line where the Vread pair is applied to the unselected word line. The voltage is compensated for temperature and Vcgr is the temperature compensation for the voltage applied to the selected word line. In this case, the magnitude of the temperature dependence is further reduced relative to line 142, and word line position dependencies still exist. Line 丨44〇 indicates the relationship of (ΔVT/C) to the position of the word line, where Vread is temperature compensated for the voltage applied to the unselected word line and is applied to the selected word due to further word line position dependence Vcgr ' The voltage of the line is implemented as vCgr2 temperature compensation. In this case, the position dependence of the word line position of 121185.doc -32-200805382 is substantially removed relative to the case of line 1430. The word line dependency can also be obtained by ~(4) Shi Select word line. &amp; Specific 5. It has been observed that the threshold voltage of non-volatile storage elements decreases with increasing temperature. The voltage change with respect to temperature change can be expressed as a temperature = number (4), which is usually about _2mvrc. The temperature coefficient is dependent on various features of the device, such as doping, layout, etc. Furthermore, it is expected that the temperature coefficient will increase in magnitude as the memory size decreases. The temperature coefficient identifies the voltage. Or the ratio of current change to temperature change. For example, for a range of -4 (TC to +85T:, the threshold voltage can vary by about (85_ (-40)) x (-2) == 250 mV. Therefore, The read or verify operation accuracy of one or more selected storage elements associated with the selected word line can be improved by reading or verifying the voltage applied to a selected word line based on the temperature bias. Further, when not used Depending on the temperature compensation of the word line, the temperature coefficient may vary depending on the word line position, as indicated by line 14 1 。. For example, assuming that there are 32 word lines in a block, line 1410 may be at WL0 (source) Side word line) has a value of approximately -1.9 mV The value of /°C and has a value of about -2.1 mV/°C at WL31 (the drain side word line). Therefore, in a possible design, the temperature coefficient varies by 0.2 mV across the word line. Experimental data obtained on a 70 nm ABL architecture wafer shows an average page temperature coefficient change of approximately 15% based on the word line address, where WL3 1 (its series resistance is completely on its source side) due to its source side Temperature-induced series resistance changes and suffers more damage, resulting in additional body effects than W1〇 pages that also experience series resistance changes (but only at their drain sides). Various techniques are known for temperature compensation. The read voltage is supplied to the selected word line 121185.doc -33- 200805382. Most of these techniques do not rely on obtaining an actual temperature measurement, but this method is also possible. For example, U.S. Patent No. 6,801,454, the disclosure of which is incorporated herein by reference in its entirety, the entire disclosure of the disclosure of the disclosure of the entire disclosure of The patent is incorporated herein by reference. The circuit uses a bandgap current that includes a portion that is independent of temperature and a temperature dependent portion that increases with increasing temperature. The nominal &quot;N〇n-Volatile Mem〇ry Whh Temperature_c〇宁

U.S. Patent No. 6,56, 152, the disclosure of which is incorporated herein by reference in its entirety in its entirety in its entirety in its entirety in its entirety in its entirety in its entirety in its entirety in its entirety in its entirety. U.S. Patent No. 5,172,338, the disclosure of which is incorporated herein by reference in its entirety in the same extent as the data storage unit and the temperature of the reference storage unit formed on the integrated circuit. Compensation Technology 'This patent is incorporated herein by reference. The reference health unit provides a reference level 'the measured current or voltage of the selected unit can be compared to the reference = quasi-phase. Temperature compensation is provided because the temperature affects the reference level in the same manner as the value read from the data storage early element. Any of these techniques, as well as any other known techniques, as described herein, can be used to provide temperature compensation for voltages of selected word lines, unselected word lines, and/or selected gates.

Therefore, by means of conventional techniques, the read or verify voltage applied to one or more of the selected storage elements by the selected word line is temperature compensated. However, the voltage applied to the remaining word lines (which is referred to as the read voltage ν_) is applied to the selected 121185.doc •34-200805382

The voltage of the closed-pole (which is called the selection of the interpole, the source (four) or the selection of the idle, the Vsgd of the drain) has not been temperature compensated. It has been thought that temperature compensation is only performed on selected storage elements. In particular, people think that the non-selective storage element and the selection gate are overdriven to exceed their voltage: so that the temperature change does not significantly affect its conductivity. However, when the transistor is scaled down to smaller In the case of dimensions, the features are degraded, and the saturation: current is increasingly deviated from a flat profile, as indicated by the small slope of the graph of the gate voltage (Veg) from the drain current (6). In order to address these issues, it is recommended that Vread, Vsgd, Vsgs, and any other necessary transistors in the path of a storage element that is currently being read have a temperature compensated bias applied to their gates, such that each The on current of the transistor becomes less dependent on temperature. By performing temperature tracking on these applied voltages, the spread of the threshold distribution of each state due to temperature changes can be further reduced. This result can be exploited in a variety of ways (which are not necessarily mutually exclusive). For example, *Vread can be subtracted. Therefore, the overdrive amount, i.e., the degree of Vread exceeding the threshold voltage of the highest stylized state of the storage element, can be reduced, thereby reducing the associated read disturb caused by the use of a high Vread value. This reduction in Vread helps with many different read/verify techniques. This reduction is especially important for read/verify techniques that employ multiple read operations. For example, applied by Jian Chen on April 5, 2005 and is nominally '’Compensating For Coupling During Read Operations Of

Non-Volatile Memory, co-pending U.S. Patent Application Serial No. 1 1/099,133 (file number SAND-1040US0) describes a type in which each of the stylized states for 121185.doc-35-200805382 is selected for storage at different levels. The element performs a plurality of read operations, which are incorporated herein by reference. For example, the increment between levels can be 50-100 mV. This technique opposes the capacitive shank of the word line to the word line. Effect 'When a subsequent storage element (usually a drain side neighbor) is subsequently programmed, the threshold voltage offset of a previously programmed storage element is further reduced. If the offset is about large, it can cause A read dream error. When the adjacent storage element is stylized to a higher state (for example, the blame C), the face is the highest. To solve this problem, according to the stylized proximity after the storage element is selected The state of the adjacent storage elements on the word line selects one of a plurality of read operations for each stylized state. In one variation of this technique, as indicated by the verification pulsation group in FIG. Everything on the line State using a read level, while adjusting a read voltage is applied to the adjacent word line. Forth in this variation on March 17, 2006 and filed by the Nima Mokhlesi nominally ,, Read

Operation For Non-Volatile Storage With Compensation For Coupling, co-pending U.S. Patent Application Serial No. (SAND-1089US2), filed on In either case, the number of read operations used to read the same amount of data increases, and the effect of read disturb increases. The temperature compensation technique provided in this paper can alleviate this problem. A further advantage of the temperature compensation technique is that between the various stylized states (example #state E, A, BAC), the current limit and the distribution = redundancy can be reduced with the change of temperature. The increase in the voltage-limited distribution is increased. Another advantage is that the program can be increased by the following method: 121185.doc -36-200805382 performance can be increased, for example, by consuming a threshold voltage distribution of various stylized states. It is redundant and uses a larger step size in stylized pulsating staircase series. Another advantage is that the entire memory operation window (for example, for storing data in storage elements) The voltage limit range can be reduced by shortening the stylized shape L [shrinking closer to the start-up. This not only reduces read and write interference, but also increases write performance, because a desired program is achieved. The stylized pulsations required for the state will be reduced by a smaller window, and further by providing a count of selected word lines on other non-selected word lines (the NAND-non-volatile storage elements) Correlation) The temperature-compensated voltage improvement accuracy of the relative position. This accuracy improvement can be seen by comparing line 14 to 1430. The temperature of the selected word line can be selected individually or in combination with the unselected word line. Compensation is used to implement this temperature compensation. See Figure (5). A word line dependency can also be provided for the unselected word lines. ' ...^丨~Unfairly collected and temperature-compensated voltages are applied to all non-selectives in the timing diagram. The word line is applied to two select gates. In general, between the read and verify operations, the word line or other control line is connected to the voltage, which is for each read and verify operation. Prescribed to determine the relevant storage = Whether the threshold voltage has reached this level. After applying the word line voltage, measure the conduction current of the storage element to determine whether the storage element is turned on. If the measured current is greater than a certain value, it is assumed The voltage of the storage element is applied to the word line is greater than the threshold voltage stored in the storage element. If the conduction current is not greater than the value, the cardiac storage element is not turned on = 121185.doc -37- 200805382 The voltage applied to the word line is no greater than the threshold voltage of the storage element. There are a number of ways to measure the conduction current of a storage element during a read or verify operation. In one example, it is allowed (or not allowed) to The NAND string including the storage element measures the rate at which the bit line is discharged to measure the conduction current of the storage element. The charge on the bit line is measured after a period of time to determine if it has been discharged. In another embodiment, the selection of the conduction of the storage element allows current to flow or not flow on a single bit line, which is measured based on whether a capacitor in the sense amplifier is charged due to current flow. Two examples are discussed above. Figure 15a shows the waveforms SGD, WLunselected, WLn, SGS, select BL, and the source starting at a steady state voltage Vss of about 0 volts. SGD represents the gate of the gate selection gate. WLunselected represents a non-selected word line. WLn is selected for reading/verifying word lines. The gate of the gate side of the SGS system selects the gate of the gate. The bit line selected by the BL system for reading/verification is selected. The source line of the source storage element (see Figure 4). Note that there are two variations of the SGS and the selected BL. A set of such waveforms SGS (option 1) and select BL (option 1) illustrate a read/verify operation for an array of storage elements by determining whether the bit line has been discharged Measure the conduction current of a storage component. Another set of such waveforms SGS (option 2) and select BL (option 2) illustrate a read/verify operation of a one-to-one array of storage elements for discharging a dedicated capacitor in the sense amplifier The rate is used to measure the conduction current of a storage element. First, reference will be made to SGS (option 1) and selection BL (option 1) to describe the sensing circuit involved in measuring the conduction current of a storage element by determining whether the bit line has been discharged. 121185.doc -38 - 200805382 And the behavior of the array of storage elements. At time _, SGD and SGS (option 2) are raised to Vsgd·^ respectively, where V is the temperature compensated enthalpy. Vsgd VII and Vsg_ are obtained by biasing Vsgd and Vsgs for temperature respectively. For example, ^ and %# are about 3.5 volts. For example, temperature compensation can be applied in accordance with the compensation techniques described above. Raise the non-selected word line to Vread-tc. Vread_tc is biased against temperature

Obtained by Vread. For example, Vread is approximately 6 volts. The selected word line is boosted to Vcgr-tc (control gate read voltage) for a read operation, such as Vra, Vrb or Vrc of FIG. 1 or raised to a verify level for a verify operation, such as a map. 10 Vva, Vvb or Vvc. In one method, select BL (option 1) is precharged to approximately 伏7 volts. Vread_tc applied to the unselected word line acts as an overdrive voltage because it causes the non-selected storage element to conduct and act as a transfer gate. The overdrive voltage applied to the non-selective storage element is equal to the amount of voltage applied to the control gate that exceeds the threshold voltage. As mentioned, Vread is selected to a level well above the maximum voltage of the storage element to ensure that the non-selected storage element is in a conducting or conducting state. For example, the threshold voltages of states E, A, and c can be assumed to be -2 volts, volts, 2 volts, and 4 volts, respectively, while Vread can be 6 volts without temperature compensation. In this case, the storage element in state E is driven by the center (-2) = 8 volts, the storage element in state A is driven by 6_〇 = 6 volts, and the storage element in state B is 6_2. = 4 volts overdrive, and the storage element in state C is driven over 6-2 = 2 volts. Although the non-selective storage element is in a conductive state in each case, its conductivity will vary based on the degree of overdrive. The higher the drive, the better the conductivity of the non-selective storage component 121185.doc -39- 200805382' because of its smaller source-pole resistance and higher current carrying capacity. Similarly, the lower the drive, the worse the conductivity of the non-selected components due to their larger source-drain resistance and lower current carrying capacity. Therefore, the storage elements in the same NAND string as the selected storage elements will have different electrical conductivities depending on their stylized state, even if they are all in a general conductive state. Therefore, the read level of the selected storage element will be affected by the non-selected storage element according to its corresponding stylized state. Assume that a temperature compensation is -0.2 volts = 5.8 volts

For example, for reasons similar to non-selective storage elements, the voltage applied to the selected gate can be temperature compensated, thereby allowing Vsygd-tc or Vsgs_tc to be Susy. The temperature compensation of the unselected word lines and the selected gates tends to make the reading of the threshold voltage of the selected word line more dependent on the temperature. Thus, the mother-non-selective storage elements in series with the selected storage element have a small effect on the reading obtained by selecting the threshold voltage of the storage element, for example, 3 mV. Although a non-selective storage element has less effect on reading, when there are 31 (four) selection materials, the cumulative effect of each of the non-selected (four) storage component towels can be aggregated to a significant level, such as % mv . The temperature compensated effect material of the unselected word line has more word line (4) devices and is more pronounced when a reduced overdrive voltage is used. The NAND string at the gate t2 can control the bit line. Similarly, at the source side, the source is selected to be closed by SGS (option υ is raised to vs (four) and == provides a path to dissipate the charge on the bit line. If selected for storage of the component If the power-limiting WLn is also 隹, the 隹 隹 is greater than Vcgr or applied to the selected word line, the selected storage element will not be turned on and the bit line 121185.doc 200805382 will not be discharged, as shown by line 1450. If the threshold voltage in the storage element selected for reading is lower than Vcgr_tc or lower than the verify level applied to the selected word line wLn, then the storage element selected for reading will be conductive (conductive) and the bit line The voltage will be dissipated as depicted by curve 1452. At some point after time 12 and at time t3, which is determined by the particular implementation, the sense amplifier will determine if the bit line has been dissipated by a sufficient amount. Between ^ and ,, the sense amplifier measures the estimated BL voltage. At time ,, the plotted waveform will be reduced to Vss (or another alternate or recovered value). Reference will be made to SGS (option 2) And select BL (option 2) to discuss the sensing circuit and storage element array The rate at which a dedicated capacitor is charged in the charge sense amplifier measures the behavior of the conduction current of the storage element. At time 11, SGD rises to Vsgd_tc, the unselected word line (WLunselected) rises to Vread-tc, and the word line is selected (WLn) is raised to vcgr_tc (eg, Vra, Vrb, or Vrc) for a read operation, or raised to a verify level (eg, Vva, Vvb, or Vvc) for a verify operation. In this case, What the NAND string is doing, the sense amplifier keeps the bit line voltage not k, so that the sense amplifier measures the current flowing when the bit line is "clamped" to the voltage. After time t1 and before time t3 At a point (which is determined by the particular implementation), the sense amplifier will determine if the capacitor in the sense amplifier has dissipated a sufficient amount. At time t3, the waveform depicted will be reduced to Vss (or another Alternate or recovered value. Note that in other embodiments, the timing of certain waveforms may be changed. Figure 15b illustrates the timing diagram of Figure 15a, wherein different temperature compensated voltages are applied to the selected word line based on word line position. As combined As discussed in 丨4, in a method of 121185.doc -41 - 200805382, when the position of the word line is closer to the source than the source, the temperature compensation can be made to a higher value (for example, a negative value) Large) applied to the selected word line. This is illustrated by the timing diagram of Figure 15b, the towel is applied to a

The temperature compensated voltage applied to the selected word line (e.g., WLG) near the source is shown by the dashed line and the temperature compensated voltage applied to the selected word line (e.g., WL3i) closer to the pole is displayed by a solid line. The temperature-compensated voltage applied thereto when the word line Μ and the drain t are selected is in the middle of the voltage applied thereto when the word line is on the source side or the drain side, for example, from the source or (4) The distance is proportional. A word line position dependency can be provided for the voltage applied to one or more of the select gate and the unselected word line. Figures 16-18 can be modified in an analogy manner to provide a word line position dependency. Figure 16 is a timing diagram illustrating the behavior of certain waveforms during a read/verify operation where the temperature compensated voltage is applied to all non-selected word lines except for the word line directly adjacent to a selected word line, and applied to both Select the gate. The waveforms SGD, SGS (option 1) and SGS (option 2) are the same as in Figure 15a. The selection of the BL and source waveforms (not shown) is also the same as in Figure Ua. The waveform representing WL0 to WLn-2 represents a temperature-compensated read applied to a word line between the first word line WL0 and the word line WLn_2 and including the first word line WL0 and the word line WLn_2. Taking the voltage, the word line WLn-2 is next to the source side of the selected word line WLn adjacent to the word line WLn-1. Waveforms labeled WLn-2 through WL3 1 represent application to word line WLn+2 (which is followed by one of the drain side adjacent word lines WLn+Ι of the selected word line WLn) and WL31 (which is directly adjacent to the drain side select gate) A temperature compensated read voltage between and including the word lines of word lines WLn+2 and WL3 1 . Suppose there are thirty-two storage 121185.doc -42- 200805382 components on a NAND string, but different numbers can be used. For such non-selected word lines, temperature compensation is applied as described. Similarly, for the selected word line WLn, a temperature-compensated control gate read voltage Vcgr_tc is applied.

For either or both of the word lines WLn_i and WLn+丨 directly adjacent to the selected word line, the applied read voltage is not temperature compensated, or is temperature compensated-reduced by an amount 'eg' and applied to The temperature of other unselected word lines is reduced by the amount of time. The optimal compensation for a particular pair of memory devices can be determined by testing. The desirable situation is to treat the word lines 丨 and WLn+i differently than other word lines by selecting a parasitic capacitance path between the storage element and the near storage element. That is, a temperature applied to the Vread adjacent to the storage element is capacitively coupled to the selected storage element to shift its threshold voltage higher. This may be problematic especially for the above described read/verify techniques that employ multiple read levels for each stylized state. Further, it is desirable that the word lines WLn-Ι and WLn+Ι are processed in a manner different from each other with respect to temperature compensation. Figure 17 is a timing diagram illustrating the behavior of certain waveforms during a read/verify operation. Figure 1 shows the selected word line directly adjacent to the source side select gate. Waveforms SGD, SGS (options 1} and (10) (option 2) are the same as in Figure 选择. Selecting the muscle and source waveforms (not shown) is also the same as in Figure 15a (4). Here, select word line WL0 directly (four) source side The gate is selected. As mentioned, for some such read/verify techniques, it is desirable to not use temperature compensation for the reading of the transistor applied to the adjacent component. These adjacent transistors are included in the source. The side selects the closed pole and the other side includes the disconnecting element. Therefore, in the possible method, the applied electricity 121185.doc -43- 200805382 is not temperature compensated, or temperature compensated The compensation is less than the amount applied to other non-selected word lines and another select gate (which is not directly adjacent to the drain side select gate of the selected storage element). In particular, Vsgs can be applied to SGS, Vread-tc It can be applied to WL〇 and WL2 to WL3 i, VRad can be applied to WL1 ' and Vsgd-tc can be applied to SGD.

Figure 18 is a timing diagram illustrating the behavior of certain waveforms during a read/verify operation in which the selected word line is directly adjacent to a drain side select gate. The waveforms SGD, SGS (option 1) and 8 &lt; 38 (option 2) are the same as in Fig. 15a. The selection of bl and source waveforms (not shown) are also the same as in Figure 15a. Here, the selected word line WL3 1 is directly adjacent to the drain side selection gate. As mentioned, for certain read/verify techniques, it is desirable to not use temperature compensation for the read voltage applied to the transistor adjacent to the selected storage device. These adjacent transistors include a drain side select gate on one side and wl3 turns on the other side. Therefore, in a possible method, the applied voltage is not temperature compensated, or the temperature compensation is applied to other unselected word lines and another selected gate (not directly adjacent to the source side select gate of the selected material element) The compensation is a small amount. Specifically, Vsgs can be applied to (10), Ha can be applied to WL0 to WL39, Vread can be applied to hunger, and can be applied to SGD. Therefore, in the methods of FIGS. 17 and 18,

Whether the storage component is selected or not smoked 14 sy L ~ dry \ no, the work selection will be applied to one or two select gates, the power is set to be different, also in the 1 J &lt; bit early, for example, one Temperature compensated level or compensated level. Figure is a flow diagram illustrating an embodiment of a method for staging non-volatile memory. In some embodiments, the storage element is erased prior to characterization of 121185.doc -44 - 200805382 (in blocks or other units). In step 1900, the controller issues a data entry, and the control circuit 310 receives the input. In step 1905, the address of the specified page address is self-controlled. The host or host is input to the decoder 314. In step 1910, one of the programmed pages of the addressed page is input to a data buffer for stylization. The data is latched into a suitable set of latches. In step 1915, the controller issues a , stylized &quot;command to the state machine 312. After being triggered by the "stylized" command, the stepped pulsations 1310, 1320, 1330 of Figure 13 applied to the appropriate word line are used, 1340, 1350, . . . program the data latched in step 1 91 0 to the selection of the control of the state machine 312. In step 1920, the programmed voltage Vpgm is initialized to start pulsing (eg 12 Volt or another And initializing the stylized counter PC maintained by the state machine 3 to 〇. In step 1925, the first Vpgm pulse is applied to the selected word line to begin programming the storage elements associated with the selected word line. Stored in a specific data latch, which indicates the stylized corresponding storage element, grounds the corresponding bit line. On the other hand, if the logic "1" is stored in the specific latch, this indication corresponds to If the storage element remains in its current data state, the corresponding bit line is connected to vdd to disable stylization. In step 1930, as discussed, the appropriate temperature compensated voltage is used and either temperature compensated or temperature compensated A reduced amount of voltage is used to verify the state of the selected storage element. If it is detected that the target threshold of a selected storage element has reached the appropriate level, the lean material stored in the corresponding data latch is changed. It is logic "1". If it is detected that the threshold voltage has not yet reached the appropriate 121185.doc -45-200805382, the target γ, ,] does not change the data stored in the corresponding data latch. In this way, ',, and privately, one has a logical 储存 stored in its corresponding data latch, 1 丨丨 〇 σ 二 2 ^ 70 lines. When all data latches store logic, the "," recorder (by the above-mentioned "wired" or "type" mechanism) knows all the two choices: the thread f τ Μ has been programmed. In step (7), it is checked that the data [= 均 is stored with logic ''1'. If so, the stylization process 70 is successful and all the selected storage elements are programmed and verified. The "pass" state is reported in step 。 0. In one embodiment, as previously described in Figure 15.18, the verification of step 193() includes providing a temperature compensated voltage to one or more unselected word lines and providing To one or more selection gates. ' ” If it is determined in step 1935 that not all data latches store a logical "1", then the stylization process continues. In step 1945, the stylized counter pc is checked against the stylized limit value PCmax. An example of a stylized limit value is twenty, but other quantities can be used. If the stylized counter pc is not small; at PCmax, the stylization process has failed and is reported in step 195, "failed" state. If the stylized counter PC is less than PCmax, the Vpgm level is increased by the step size and in step 1955 The programmatic counter PC is incrementally incremented. After step 1955, the process loops back to step 1925 to apply the next Vpgm pulse. The present invention has been described above for purposes of illustration and description. This document is not intended to be exhaustive or The invention is limited to the precise forms disclosed, and many modifications and changes can be made in accordance with the teachings hereinabove. The selection of the embodiments is intended to best explain the principles of the invention and its application. (The skilled person in the art is able to make the best use of the present invention in various embodiment forms suitable for the specific application of the specific model 121185.doc -46 - 200805382 and using various modifications. The scope of the present invention is intended to be covered by the accompanying patent application. Figure 1 is a top view of a NAND string. Figure 2 is an equivalent circuit diagram of a NAND string. Figure 3 is a cross-sectional view of a NAND string. Figure 5 is a block diagram of a non-volatile memory system. Figure 6 is a block diagram of a non-volatile memory system. Figure 7 is a block diagram of a sensing block. Figure 8 illustrates an example of an organization of memory blocks organized into blocks of all bit line memory architectures. Figure 9 illustrates the organization of a memory array organized into blocks of parity memory architecture. An example of a form is shown in Figure 10. Figure 10 illustrates an exemplary threshold voltage distribution group.Figure 11 illustrates an exemplary threshold voltage distribution group. "Figure 12A-c shows various threshold voltage distributions and details - for stylized non- Process of Volatile Memory Figure 13 is an exemplary waveform of a control gate applied to a non-volatile storage element during stylization. Figure 14 illustrates a threshold voltage as a function of temperature and word line position. A timing diagram that explains the behavior of certain waveforms during a read/verify operation, in which a temperature compensated voltage is applied to all unselected word lines and applied to two select gates. 121185.doc -47- 200805382 Figure 15b shows Figure 15a is a timing diagram in which different temperature compensated voltages are applied to selected word lines based on word line locations. Figure 16 is a timing diagram illustrating the behavior of certain waveforms during read/verify operations, where temperature compensated The voltage is applied to all non-selected word lines except the sub-lines directly adjacent to the selected sub-line and applied to the two select gates. Figure 17 is a timing diagram illustrating the behavior of certain waveforms during read/verify, where The selected word line is directly adjacent to a source side select gate. Figure 18 is a timing diagram illustrating the behavior of certain waveforms during read/verify 'where the selected word line is directly adjacent to a drain side select gate. Figure 19 is a flow diagram illustrating one embodiment of a process for stylizing a non-volatile quotation body. [Main component symbol description] 100 transistor 100FG floating gate 100CG control gate 102 transistor 102FG floating gate 102CG control gate 104 transistor 104CG control gate 104FG floating gate 106 transistor 106CG control gate 121185.doc 200805382 106FG 120 120CG 122 122CG 126 128 130 132 134 136 138 140 150 204 206 286 298 300 310 312 314 315 316 Floating gate transistor control gate transistor control gate without terminal N+ doped layer N+ doped diffusion region N+ Doped diffusion region N+ doped diffusion region N+ doped diffusion region N+ doped diffusion region p well region NAND string source line bit line memory device memory grain memory array control circuit state machine on-chip address decoder temperature Compensation Control Power Control Module 121185.doc -49- 200805382 318 Line 320 Data Bus 330 Decoder 330A Column Decoder 330B Column Decoder 350 Controller 360 Decoder 360A Line Decoder 360B Line Decoder 365 Read/Write Circuit 365A Read/Write Circuit 365B Read/Write Circuit 370 Sensing Circuit 372 Bus Bar 380 Sensing Mode Group 382 Bit Line Latch 390 Common Part 392 Processor 393 Input Line 394 Data Latch 396 I/O Interface 400 Sensing Block 1250 Threshold Voltage Distribution 1300 Waveform 121185.doc -50- 200805382 1310 Common Part 1312 Verification Pulsation group 1320 Common portion 1322 Verify pulsation group 1330 Common portion 1332 Verify pulsation group 1340 Common portion 1342 Verify pulsation group 1350 Common portion 1352 Verify pulsation group 1410 Line 1420 Line 1430 Line 1440 Line 1450 Line A State B State Bf State C State E Shape Evil 121185.doc - 51 -

Claims (1)

200805382 X. Patent Application Range: 1. A non-volatile storage system comprising: a set of non-volatile storage elements; and - one or more circuits 'by a plurality of control lines and the set of non-volatile storage ports Communication, the one or more circuits (4) will be at least - the first 2. [Knowing to the selection control line to determine at least one of the first non-volatile storage (four) associated with the selection control line - a stylized state, and (8) at - the time during which the at least - first voltage is applied At least a portion of the period 'will: a temperature compensated voltage is applied to at least - a first non-selected control line associated with the set of non-volatile storage elements. The non-volatile storage system of claim 1, wherein the one or more circuits apply a series of the first voltages to the selection control line to determine the at least one first non-volatile storage element Stylized, the temperature compensated voltage is applied when each of the series of first voltages is applied to the select control line. 3. The non-volatile storage system of claim 1, wherein: the temperature compensated one of the levels is set according to the relative position of the at least one first non-selected control line in one of the plurality of control lines . 4. The non-volatile storage system of claim 1, wherein the one or more circuits apply a voltage to a direct proximity to the selection during at least a portion of the time during which the at least one first voltage is applied a second non-selected control line of the control line, the (four) temperature compensated or temperature compensated - relative to the reduced amount of the temperature compensated voltage applied to the first non-selected control line. The non-volatile storage system of claim 1, wherein: wherein: at least a portion of the time during which the at least one first voltage is applied, or a plurality of circuits, the temperature-compensated voltage is applied. One of the gates of the NAND string including the at least one _ _ non-volatile storage element controls the gate. 6_ The non-volatile storage system of claim 1, wherein the non-volatile storage (four) of the at least - the first non-selective control is maintained in a conductive state. The non-volatile storage system of item 1, wherein: the first voltage comprises a read voltage, and the read voltage is used to read the first non-volatile storage element after the program is programmed to... The stylized state of the sexual storage element. 8. The non-volatile storage system of claim 1, wherein: at least a first voltage comprises a verification voltage, and wherein the at least one first non-electricity is determined to be used in a stylized state. Period 9. The non-volatile storage system of the request, wherein: the at least one first voltage is temperature compensated. 10. In the non-volatile storage system of claim 1, wherein: ·===: The selection control line is temperature compensated at the plurality of control positions. The non-volatile storage system of claim 1, wherein: the set of non-volatile storage elements comprises a plurality of level storage elements. 12. A method for operating a non-volatile reservoir, comprising: 121185.doc 200805382 applying at least a _th voltage to a select word line to determine at least a disc = a word line associated with a non-volatile The storage component - Cheng Xinhuan. 4 at least one first non-volatile storage element is disposed in a set of non-volatile storage elements; and 13. 14. / / 15. 16. Love at - at least a portion of the time during which the at least one first voltage is applied A temperature compensated voltage is applied to at least one H select word line associated with the set of non-volatile storage elements. The method of claim 12, wherein: applying a first voltage such as series 忒 to the selected word line to determine the stylized state to the 'first non-volatile storage element, the temperature compensated voltage is Applied when each of the series first voltages is applied to the selected word line. The method of claim 12, wherein: the one of the temperature compensated voltages is set according to a relative position of a non-selected word line to a plurality of word lines associated with the set of non-volatile storage elements. quasi. The method of claim 12, further comprising: applying a voltage to a second unselected word line directly adjacent to the selected word line during at least a portion of a time during which the at least one first voltage is applied The voltage is not temperature compensated or temperature compensated by an amount relative to the decrease in the temperature compensated voltage applied to the first unselected word line. The method of claim 12, further comprising: applying a temperature compensated voltage to the at least one first non-spreading during at least a portion of time 121185.doc 200805382 at which the at least one first voltage is applied One of the at least one selection gate of a NAND string of the storage element controls the gate. 17. The method of claim 12, wherein: /,,, and the voltage of the device is sufficient to maintain the non-volatile storage element associated with the at least one first unselected word line in a conductive state. 18. The method of claim 12, wherein: The first voltage includes a read voltage for reading the stylized state of the at least non-volatile storage element after at least the volatile component has been programmed. The method of claim 12, wherein: the second to fourth voltage comprises a verification voltage for determining whether the first non-volatile storage element has reached a desired stylized state . The method of claim 12, wherein the at least one first voltage is temperature compensated. 21. The method of claim 12, wherein: one of the word lines associated with the selected word line is associated with the set of non-volatile storage element handles. Relative position to perform the at least one first-voltage 121185.doc