WO2007148160A2

WO2007148160A2 - Method of multi-layer lithography

Info

Publication number: WO2007148160A2
Application number: PCT/IB2006/052666
Authority: WO
Inventors: Terry Sparks
Original assignee: Freescale Semiconductor, Inc.
Priority date: 2006-06-20
Filing date: 2006-06-20
Publication date: 2007-12-27
Also published as: WO2007148160A3; TW200807503A

Abstract

A method of patterning a first resist layer (10') according to a pattern formed in a patterned second resist layer (14') formed thereon. A first resist material (10) is first at least partially pyrolyzed so as to form a hard mask resist layer (10'). A surface of the first resist layer (10') then generally functionalized with a silicon-containing group, such as by way of silylation, so as to define a silicon-containing surface layer (12). The first resist layer (10') (including silylated surface layer 12) is then, for example, dry developed according to the pattern formed in the second resist layer to form a corresponding pattern in the hard mask layer (10'). The patterned second resist layer (14') may be, for example, about 80 nm to about 100 nm thick.

Description

METHOD OF MULTI - LAYER LI THOGRAPHY

Field of t he i nvention :

The present invention relates to a lithography method using a multi-layer

resist ("MLR') in a semiconductor device.

Backgrou nd of t he i nvention :

A general problem in the fabrication of semiconductor devices is maintaining

etch resolution as feature sizes progressively decrease.

A basic conventional approach is to pattern a single-layer resist to form an

etch mask (not illustrated). I n general, a single resist layer is formed on an

underlying substrate. A pattern is formed in the resist layer by selectively exposing

the layer in correspondence with the desired pattern (such as by way of illumination

through a mask). The exposed resist layer is then developed so that (depending on

the resist material being used) the exposed parts of the resist are either hardened

and left in place during development or are made soluble and are removed during

developing. The patterned resist is thus used as a mask for etching a desired

pattern thereunder according to known practice. The resist layer in this case is

generally relatively thick, which requires more processing and limits the resolution of

an obtainable pattern.

Figure 1 comparatively illustrates some additional conventional resist

patterning approaches (a) - (d), plus an example sequence of steps (5000) in

accordance with an embodiment of the present invention at (e). As can be seen in

Figure 1 , the various methods illustrated use some combination of exposure (plus

post-etch bake), a wet develop step, a silylation (for generally, functionalizing with silicon) step, and a dry develop step (such as plasma treatment). The illustrated

processes are to be considered in sequence from top to bottom, using whichever

steps are applicable thereto, as described hereinbelow.

Top surface imaging ("TSI") 1000 is a known alternative approach (illustrated

at sequence (a)) to using a single layer resist as described above. I n TSI , an organic

resist 100 layer is deposited on a substrate 102 and is selectively exposed (as

represented by 104) according to a desired pattern. Before developing the resist

layer 100, a silicon-containing solvent is applied (108) to the surface of the exposed

resist layer 100, which reacts preferentially with the several exposed portions 100' of

the resist layer so that only the exposed areas 100" become silicon-containing (e.g.,

silylated). The silylated portions 100" then act as a mask in a dry plasma (e.g.,

oxygen plasma) developing step 1 10 to leave a patterned resist 100'" remaining.

More particularly, the silicon-containing areas 100" are selectively reacted or

"oxidized" during the plasma development step 110 so as to form etch barriers that

protect the underlying resist and substrate thereunder and leave a pattern in resist

layer 100. However, the TSI process has been shown to have a limited resolution.

A bi-layer resist ("BLR') patterning process 2000 is also generally known and

is generally illustrated at (b) in Figure 1. I n the BLR process, a first resist layer 200

(made from, for example, a cross-linked polymer/resist, or a CVD-deposited

amorphous carbon) is formed on a substrate 202, followed by a relatively thin silicon-

containing resist layer 204. Resist layer 204 contains, for example, about 2%-6% by

atomic weight of silicon. The thin silicon-containing resist layer 204 is then exposed

206 and wet developed 208 to obtain patterned thin resist layer 204'. Thereafter,

the first resist layer 200 is dry developed (210) (such as by plasma using anisotropic oxygen reactive ion etching) in accordance with the pattern formed in patterned thin

resist layer 204' to obtain a patterned first resist layer 200'. As in TSI , the patterned

silicon-containing thin resist layer 204' helps protect the protected parts of the first

resist layer from being etched in the dry develop step 210.

BLR patterning has several limitations, such as unwanted chemical interaction

between the thin silicon-containing resist layer and the underlying cross-linked

polymer/ resist 200, when the latter is used. This significantly limits process

capabilities and increases process complexity, while overall limiting the obtainable

patterning resolution.

If CVD-deposited amorphous carbon is instead used in the conventional BLR

approach, processing suffers because CVD is a relatively expensive and slow process,

requiring separate particular process equipment. This reduces production

throughput. I n addition, CVD processes use relatively high temperatures (for

example, 400°C to 500°C), which can damage circuit elements elsewhere on the chip

structure. Although it could be useful to try to reduce the temperature of the CVD

process to address this issue, doing so reduces the quality of the deposited layers.

Another known process is chemical amplification of resist lines ("CARL") 3000,

as generally illustrated at (c) in Figure 1. I n CARL, a thin imaging layer 304 is coated

on top of, for example, a cross-linked underlayer 300, which is in turn formed on a

substrate 302. Here, however, the imaging layer 304 does not contain silicon.

The imaging layer 304 is exposed 306 and wet-developed 308 using

conventional aqueous basic developers to obtain a patterned imaging layer 304'.

The patterned imaging layer 304' is then silylated (310), (for example, by way of a

solution of a bifunctional, oligomeric aminosiloxane). This creates a crosslinked, silicon-rich etch barrier 304". The image is then transferred down through the

underlayer 300 using oxygen RI E dry developing 312 to obtain a patterned

underlayer 300'.

Multi-layer resist ("MLR') resist patterning 4000 is somewhat similar to BLR

patterning 2000, but includes an additional inorganic layer 405 deposited separately

between a first resist layer 400 and a second resist layer 404. This thin inorganic

layer 405 acts as a hard mask during the etch pattern transfer step. This hard mask

layer 405 can be a silicon-containing, spin-coated or CVD oxide film. The second

resist layer 404 is typically an organic film.

Second resist layer 404 is exposed (406) and then wet developed (408) to

obtain a patterned second resist layer 404', leaving parts of mask layer 405 exposed.

During a dry develop step 410, the exposed parts of transfer layer 405 are etched

away, as are the corresponding portions of first resist layer 400 thereunder, but the

unexposed parts of transfer layer 405 serve as an etch stop barrier. Therefore, a

patterned first resist layer 400' is obtained. (The remaining parts of patterned

second resist layer 404' are removed in a conventional process, not shown.)

A disadvantage to the MLR approach is the complexity that arises from the

need for three separate layers 400, 404, 405 and the requirement to integrate the

processing steps for good imaging and pattern transfer. Also, the transfer layer 405

is still relatively thick, and is susceptible to deposition defects.

Su m m ary of t he i nvention :

The present invention provides a method as described in the accompanying

claims. Brief description of t he draw ings:

Figures 1 (a) to 1 (d) illustrate certain resist patterning techniques known in the

art; and

Figures 1 (e) and 2(a) to 2(f) illustrate several steps of a resist patterning

technique according to an embodiment of the present invention.

Detai led description of the preferred em bodi ments:

Figures 1 (e) and 2(a) to 2(f) illustrate several steps in a method of patterning

a multi-layer resist according to an embodiment of the present invention. Each

illustrated step is to be understood to be a fragmentary cross-sectional view of the

structure in question.

I n general, Figure 1 (e) corresponds to Figures 2(d), 2(e), and 2(f). Figure

1 (e) provides a relative comparison to conventional TSI , BLR, CARL, and MLR

approaches, as illustrated in Figures 1 (a)-1 (d) and discussed above.

I n Figure 2(a), a first resist layer 10 is formed on an underlying substrate 20.

The first resist layer preferably acts as an anti-reflective (i.e., optically absorbent)

coating. An example of an appropriate material for the first resist layer 10 is a

Novolac resin, applied (for example, by a spin-on process) to form a layer about 200

nm thick.

At Figure 2(b), the first resist layer 10 is at least partially pyrolyzed (for

example, at a temperature of about 120°C to about 250°C, for about 2 minutes to

about 10 minutes), using a UV light and/or a thermal treatment) to form a hard

mask layer 10'. The use of UV light treatment in this regard may be desirable

because it reduces processes time. For simplicity, reference will be made herein to first resist layer 10'. After

expected shrinkage of the first resist layer 10 during pyrolysis, the first resist layer

10' is, for example, about 140-150 nm thick.

Next, at Figure 2(c), the entire surface of the first resist layer 10' is

functionalized with a silicon-containing group to obtain a silicon-functionalized

pattern transfer layer 12.

For example, hexamethyldisilizane (HMDS) vapor or liquid can be applied

followed by a thermal treatment step, in a conventional manner, to carry out

silylation of a surface of first resist layer 10' and thereby form pattern transfer layer

12. Other means of silicon-functionalizing in accordance with the present invention,

for example and without limitation, applying other silicon containing substances by

appropriate means other than HMDS, such as silicon containing organic acids and the

like. However, for convenience of description, without being limitative as to other

forms of silicon-functionalizing, reference is made hereinafter to a silylated layer 12.

The silylation of the surface of the hard mask layer 10' is in contrast to, for

example, TSI in which only exposed parts of a resist layer are silylated (see, for

example, regions 100" in Figure 1 (a)). I n comparison, the silylation step of the

present invention is simple because it is generally applied to an entire surface of first

resist layer 10', and does not require comparable precision so as to be limited to a

given pattern. I n addition, silylation can be implemented on the same resist process

tool used for forming first resist layer 10' and may even be implemented using the

same sequence (coat, develop, etc.). Furthermore, silylation permits a much thinner

and better quality layer than, for example, depositing a separate layer, like in the

conventional MLR (4000) discussed hereinabove. The silylation illustrated in Figure 2(c) forms a silylation layer 12 at the surface

of the first resist layer 10'. Silylation layer 12 is, for example, about 10-20 nm thick.

As in TSI , the silylation layer 12 has a very high etch selectivity (on the order of

about 80: 1 ) in a subsequent dry develop step.

I n Figure 2(d), a thin second resist layer 14 is formed on silylation layer 12

and is then exposed (indicated at 16 in Figure 1 (e)) according to a desired pattern.

The second resist layer 14 is, for example, about 80-100 nm thick. The second resist

layer 14 is then, for example, wet developed (indicated at 18 in Figure 1 (e)) in a

conventional manner (as illustrated at Figure 2(e)) in order to obtain a patterned

resist layer 14'.

Finally, portions of the silylated layer 12 (which acts as a pattern transfer

layer) left exposed by patterned resist layer 14' (as seen in Figure 2(e)) are etched in

a short oxide etch step using conventional etch chemistry, such as Cf₄IO₂ to thereby

pattern the silylated layer 12 (not shown). Because of the thinness of the silylated

layer 12, the etch step can be perform rapidly so that image resolution does not

suffer as it might under a longer or more aggressive etch necessitated by a thicker

layer.

Thereafter, the first resist layer 10' is dry developed (19) using the patterned

silylated layer as a mask to obtain a patterned first resist layer 10". The patterned

resist layer 14' may be simultaneously removed during the dry develop step 19, until

the patterned silylated layer is reached (which acts as an etch barrier). See Figure

2(f).

It is noted that the patterned silylated layer may be removed during a

subsequent step of etching the substrate 20. It is of course noted that the "pattern" formed as illustrated in Figure 2 is

purely by way of example and in no way is limitative.

It is contemplated, but not required, according to the present invention, to

perform all of the steps of the present invention on a single track, avoiding complex

and operationally slow process equipment such as CVD reaction equipment. For

example, the present invention can be advantageously implemented entirely on a

single lithographic system tool using standard available processing steps in one

sequence, i.e., resist coat, bake (to cross-link, partially pyrolyze), HMDS silylation,

resist coat, bake, expose and wet develop. This can result in significant cost and

cycle time reduction and improved process control compared to conventional MLR

resist patterning processes.

Although the present invention has been described above with reference to

certain particular preferred embodiments, it is to be understood that the invention is

not limited by reference to the specific details of those preferred embodiments.

More specifically, the person skilled in the art will readily appreciate that

modifications and developments can be made in the preferred embodiments without

departing from the scope of the invention as defined in the accompanying claims.

Claims

CLAI MS:

1. A method of patterning a resist, comprising:

forming a first resist layer (10') on a substrate (20);

functionalizing a surface of the first resist layer (10') with a silicon-containing

group to obtain a silicon-functionalized surface layer (12) at a surface of the first

resist layer (10');

forming a patterned second resist layer (14') on the silicon-functionalized

surface layer (12) of the first resist layer (10'); and

forming a pattern in the first resist layer (10') in correspondence with the

pattern provided in the patterned second resist layer (14'),

characterized in that the patterned second resist layer (14') is not more than

about 100 nm thick.

2. A method according to claim 1 , wherein forming a first resist layer (10')

comprises spinning-on a first resist material (10) on the substrate, and at least

partially pyrolizing the spun-on first resist material (10).

3. A method according to claim 1 , wherein forming the patterned second

resist layer (14') comprises:

depositing a second resist material (14) on the silicon-functionalized surface

(12) of the first resist layer (10');

exposing (16) predetermined regions of the deposited second resist material

(14) to define a pattern; and

developing (18) the exposed regions of the deposited second resist material.

4. A method according to claim 3, wherein developing (18) the exposed

regions of the deposited second resist material comprises wet developing the

exposed regions of the deposited second resist material.

5. A method according to claim 2, wherein:

at least partially pyrolizing the first resist material comprises at least partially

pyrolizing the first resist material using at least one of a thermal treatment and an

ultraviolet light treatment; and

forming a pattern in the first resist layer comprises:

etching back portions of the silicon-functionalized surface layer (12) left

exposed by the patterned second resist layer (14') to obtain a patterned silicon-

functionalized surface layer, and

dry-developing (19) the at least partially pyrolized first resist layer (10')

according to the patterned silicon-functionalized surface layer.

6. A method according to claim 5, further comprising etching back the

patterned second resist layer (14').

7. A method according to claim 5, wherein dry-developing (19) the at least

partially pyrolized first resist layer (10') comprises plasma etching the at least

partially pyrolized first resist layer (10').

8. A method according to claim 1 , wherein functionalizing a surface of the

first resist layer (10') comprises silylating a surface of the first resist layer (10').

9. A method according to claim 1 , wherein the silicon-functionalized

surface (12) of the first resist layer (10') is between about 10 nm and about 20 nm

thick.

10. A method according to claim 8, wherein silylating the surface of the first

resist layer comprises silylating the surface of the first resist layer with

hexamethyldisilazane.

11. A method according to claim 10, wherein the hexamethyldisilazane is in

one of liquid and vapor form.

12. A method according to claim 2, wherein the first resist material (10) is a

polymeric resin.

13. A method according to claim 12, wherein the polymeric resin is a

Novolac resin.