WO2007147826A1 - Système de traitement de disposition - Google Patents

Système de traitement de disposition Download PDF

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Publication number
WO2007147826A1
WO2007147826A1 PCT/EP2007/056091 EP2007056091W WO2007147826A1 WO 2007147826 A1 WO2007147826 A1 WO 2007147826A1 EP 2007056091 W EP2007056091 W EP 2007056091W WO 2007147826 A1 WO2007147826 A1 WO 2007147826A1
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WO
WIPO (PCT)
Prior art keywords
layout
integrated circuit
equations
printable
printed image
Prior art date
Application number
PCT/EP2007/056091
Other languages
English (en)
Inventor
Alexandre Anatolievich Arkhipov
Yefim Belenky
Martinus Maria Berkens
Linard Karklin
Kuang-Hao Lay
Christinus Werner Hubertus Strolenberg
Jeroen Pieter Frank Willekens
Original Assignee
Sagantec Israel Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sagantec Israel Ltd filed Critical Sagantec Israel Ltd
Publication of WO2007147826A1 publication Critical patent/WO2007147826A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level

Definitions

  • the invention relates to a layout processing system configured to adapt an integrated circuit layout comprising integrated circuit objects being a representation of the integrated circuit layout substantially corrected for local process variations in a manufacturing process of the integrated circuit.
  • the invention further relates to a method of adapting an integrated circuit layout, and to a computer program product for adapting an integrated circuit layout.
  • Layout processing systems for processing an integrated circuit layout which represents an integrated circuit are known in the art.
  • the known layout processing systems scan objects from the integrated circuit layout.
  • the scanned objects in the integrated circuit layout must comply with a set of rules, so called design rules.
  • Design rules are specific to a particular semiconductor manufacturing process.
  • a set of design rules specifies certain geometric and connectivity restrictions between objects of the integrated circuit layout to account for variability in semiconductor manufacturing processes.
  • Different manufacturing processes typically comprise different sets of design rules.
  • Compliance of the objects to a specific set of design rules ensures that the integrated circuit layout can be manufactured using a specific manufacturing process.
  • the known layout processing system verifies compliance of the scanned objects to the design rules. In a case when non-compliance with the design rules is detected, the layout processing system processes the objects in the integrated circuit layout, for example, by changing positions and/or altering dimensions of the object to obtain a processed integrated circuit layout which complies with the design rules.
  • the known layout processing system may be used as a design- rule fixing system.
  • the design-rule fixing system checks the integrated circuit layout for compliance with a set of design rules. In case a non-compliance with the design-rules is detected, the integrated circuit layout is changed.
  • the known layout processing system may be used as a migration engine.
  • the migration engine migrates an integrated circuit layout from a first manufacturing process which is defined by a first set of design rules to a second manufacturing process which is defined by a second set of design rules distinct from the first set of design rules.
  • the known layout processing system may be used as a compaction engine.
  • the compaction engine rearranges the objects in the integrated circuit layout to reduce an area, also referred to as footprint, occupied by the integrated circuit layout on a silicon wafer. The footprint is reduced while complying with the set of design rules.
  • patterning processes for example, optical or electron beam lithography and etching processes
  • the patterned wafer layout comprises an image of the objects of the integrated circuit layout or, if the integrated circuit layout is processed using the known layout processing system, of a processed integrated circuit layout (e.g., design rule generated equations added to integrated circuit layout equations).
  • a processed integrated circuit layout e.g., design rule generated equations added to integrated circuit layout equations.
  • known optical lithography processes the integrated circuit layout or the processed integrated circuit layout is transferred to a mask layout which is projected via a projection system onto a photo-resist layer.
  • the photo-resist layer is developed and subsequently the developed photo-resist layer is used as a mask for etching the integrated circuit layout or the processed integrated circuit layout into the wafer using an etching process or for implanting ions into the wafer according to the integrated circuit layout using an implant process.
  • This results in the patterned wafer layout which is a printed image layout of the integrated circuit layout or of the processed integrated circuit layout. Due to, for example, non-linearities in the lithography and etching processes, the patterned wafer layout may deviate from the integrated circuit layout or from the processed integrated circuit layout. These deviations due to manufacturing effects are typically registered and used in a further processing step of the integrated circuit layout or the processed integrated circuit layout via the layout processing system.
  • a drawback of the known layout processing system is that the processing time for the layout processing system to account for deviations due to manufacturing effects is too long.
  • the object is achieved with a layout processing system as claimed in claim 1.
  • the object is achieved with a method of adapting an integrated circuit layout as claimed in claim 9.
  • the object is achieved with computer program product for adapting an integrated circuit layout as claimed in claim 10.
  • the layout processing system in accordance with the first aspect of the invention generates a set of equations.
  • Each equation comprises a mathematical representation of a design rule applied to groups of integrated circuit objects.
  • the layout processing system further comprises an equation adapter module which adapts the set of equations to obtain an adapted set of equations.
  • the equation adapter module is configured to adapt at least one of the set of equations associated with a local process value.
  • the local process value results from the local process variations and represents a local discrepancy between a printable circuit object of a printable circuit layout and a printed image object of a printed image layout.
  • the printable circuit layout is a representation of the integrated circuit layout which is manufacturable by the manufacturing process.
  • the printed image layout results from applying the manufacturing process to the printable circuit layout.
  • the layout processing system further comprises a layout adapter module.
  • the layout adapter module adapts the integrated circuit objects for complying with the adapted set of equations to obtain process corrected objects which constitute the process corrected layout.
  • the integrated circuit may be a miniaturized electrical circuit, also commonly known as a chip, and may be a miniaturized construction, also commonly known as nanostructures, comprising, for example, mechanical nanostructures, magnetic nanostructures, chemical nanostructures and biological nanostructures.
  • the adaptations of the integrated circuit objects comprises altering the outer dimensions of the integrated circuit objects, and comprises moving the integrated circuit objects relative to each other.
  • the effect of the layout processing system in accordance with the invention is that only specific equations from the set of equations are adapted to obtain the adapted set of equations. These specific equations are associated with the local process values representing the local discrepancies.
  • the adaptation of only a limited number of equations from the set of equations reduces the processing time of the layout processing system for implementing local variations of the manufacturing process in the set of equations.
  • the known layout processing systems typically new equations are added to the existing equations to account for local errors in the patterned wafer layout.
  • the set of equations is substantially re-used.
  • the layout processing system adapts existing equations rather than generate a new set of equations. Because the generation of a new set of equations typically is time consuming, re-using part of the existing set of equations and only adapting the equations associated with the local process value saves processing time of the layout processing system.
  • a mask layout used in optical lithography to produce the printed image layout on a wafer may be less complex compared to mask layouts produced with known layout processing systems.
  • corrections to account for local process variations are done by adding optical proximity correction structures to the mask layout.
  • These added structures are often referred to as optical proximity correction structures and are typically substantially smaller than the smallest dimensions of the printable circuit objects which must be patterned on the wafer.
  • These added structures typically should not be patterned on the wafer but should only alter the optical image produced from the mask by an imaging system to correct for local variations in the pattern due to non- linearity in the imaging system.
  • the addition of these optical proximity structures often leads to a mask layout which is too difficult to manufacture using current manufacturing techniques, or which is simply too expensive.
  • the process corrected layout according to the invention is obtained by adapting the integrated circuit layout.
  • the layout processing system locally adapts the integrated circuit layout to correct for local process variations.
  • These adaptations for example, comprise moving individual integrated circuit objects or comprise altering a shape of the individual integrated circuit object, for example, using a redundancy in the integrated circuit layout.
  • Altering the integrated circuit layout generally, reduces or even omits the need to use optical proximity correction structures which reduces the complexity of the mask layout and reduces the cost of the required mask.
  • the inventors have realized that known manufacturing processes demonstrate non-linear effects which vary across the printed image layout. These non-linear effects may, for example, result from the photo-resist processing used in the lithographic process or may, for example, result from limitations in the lithographic patterning tools, or may, for example, result from limitations in the etch process. Due to these non-linear effects the printed image layout may locally differ from the printable circuit layout.
  • the local process value represents local discrepancies between the printable circuit objects and the corresponding printed image objects due to the manufacturing process used to produce the printed image objects. Using the local process value when adapting the integrated circuit layout to obtain the process corrected layout, non-linearities in the manufacturing process which result in local discrepancies are accounted for, improving the manufacturability of the integrated circuit.
  • a process simulator receives a representation of a target layout for the integrated circuit from a layout creation system.
  • the simulator simulates the effects of the manufacturing process on the target layout to produce a simulated printed image.
  • the known system identifies problem areas in the simulated printed image that do not meet a specification.
  • the known system subsequently provides information regarding the problem areas into a layout optimizer by generating additional constraints and add them to the layout optimizer.
  • the layout optimizer moves corresponding shapes in the target layout to produce a new target layout for the integrated circuit.
  • the new target layout is optimized to have improved process latitude.
  • the new target layout is subsequently simulated and checked resulting in an iterative process which continues until the new target layout meets the specifications.
  • the layout processing system according to the invention comprises the equation adapter for adapting already existing equations. Furthermore, the layout processing system according to the invention only adapts those equations from the set of equations which are associated with the local process value to obtain the adapted set of equations. The adaptation of only a limited number of equations saves processing time of the layout processing system, while the use of the equations ensures compliance of the adapted solution with the design rules.
  • the printable circuit layout is the integrated circuit layout, or is a design-rule corrected layout which is a representation of the integrated circuit layout corrected for compliance with the design rules, or is the process corrected layout.
  • the printable circuit layout is the integrated circuit layout
  • local deviations between the integrated circuit layout and the printed image layout which result from applying the manufacturing process to the integrated circuit layout are used to obtain the adapted set of equations.
  • the layout processing system adapts the integrated circuit layout to comply with the set of design rules and simultaneously to correct for local variations in the printed image layout due to the manufacturing process which reduces a need for an iterative process, resulting in reduced processing time of the layout processing system.
  • the printable circuit layout is the design-rule corrected layout
  • an iterative process is used in which in a first step the integrated circuit layout is corrected for the design rules which results in the design-rule corrected layout. Subsequently, in a second step, a correction for the local variations in the manufacturing process is applied.
  • the iteration step would result in substantially doubling the processing time of the layout processing system.
  • only those equations from the set of equations which are associated with the local process value are adapted to account for the local variations in the manufacturing process.
  • the layout processing system adapts those equations from the adapted set of equations associated with discrepancies between the process corrected layout and the printed image layout which results from applying the manufacturing process to the process corrected layout.
  • the layout processing system substantially fine-tunes the corrections for local variations in an additional iteration step.
  • the layout processing system further comprises an image analyzing module.
  • the image analyzing module is arranged to compare the printed image object with the printable circuit object to obtain the local process value.
  • the set of equations generated by the layout processing system are related to the printable circuit objects which represent the integrated circuit objects.
  • the local process value which corresponds with a particular printable circuit object can directly be related to those equations from the set of equations which are associated with the particular printable circuit object. No conversion of coordinate systems from the image analyzing module to the layout processing system is necessary, again reducing the processing time of the layout processing system.
  • the equation adapter module is arranged to receive a rating parameter assigned to a sub-group of the integrated circuit objects.
  • the rating parameter is used for rating an importance of adapting the integrated circuit layout to correct for the local process value.
  • the equation adapter module may use the rating parameter to disregard the local process value when the rating parameter is below a predetermined level.
  • the predetermined level may, for example, be set by a user.
  • a benefit of this embodiment is that disregarding the local process value when the rating is below the level results in less adapted equations. When less equations are adapted, the processing time to adapt the equations and to adapt the integrated circuit objects according to the adapted set of equations is reduced.
  • the local process value comprises an edge placement error.
  • the edge placement error is a difference between an edge location of the printable circuit object and a corresponding edge location of the corresponding printed image object.
  • a benefit of this embodiment is that the edge placement error can easily be determined using known analysis algorithms.
  • a further benefit of using the edge placement error as local process value is that the edge placement error can directly be inserted in the equations to account for the local variations resulting from the manufacturing process, which results in a relatively simple adaptation of the associated equations.
  • the local process value comprises a mask error factor.
  • the mask error factor is a ratio between a mask- variation of an edge location of the printable circuit object and a wafer-variation of a corresponding edge location of the corresponding printed image object in response to the mask-variation.
  • a benefit of this embodiment is that the mask error factor indicates what the effect is of a variation in the printable circuit object in the corresponding printed image object. This enables a correction of the printable circuit object to obtain substantial compliance between the process corrected layout and an adapted printed image layout which results from applying the manufacturing process to the process corrected layout.
  • the adapted set of equations comprises moving an individual integrated circuit object in the integrated circuit layout, or comprises altering of a shape of the individual integrated circuit object.
  • a benefit of this embodiment is that these embodiments enable to use a redundancy in the integrated circuit layout to move or reshape the individual integrated circuit object such that local process variations are corrected.
  • the printed image layout is a simulated printed image layout.
  • the simulated printed image layout results from simulating a manufacturing process applied to the printable circuit layout.
  • a benefit of this embodiment is that the use of a simulated printed image layout enables a relatively quick and cost effective method of producing a printed image layout to obtain the local process values.
  • Fig. 1 shows a flowchart of a layout processing system according to the invention
  • Fig. 2 shows a flowchart indicating the relation between the printable circuit layout and the printed circuit layout
  • Figs. 3A, 3B, 3C, 3D and 3E show manipulations of objects in a integrated circuit layout to obtain a process-corrected layout using edge placement errors
  • Figs. 4A and 4B show the determination of a mask error factor.
  • the figures are purely diagrammatic and not drawn to scale. Particularly for clarity, some dimensions are exaggerated strongly. Similar components in the figures are denoted by the same reference numerals as much as possible.
  • Fig. 1 shows a flowchart of a layout processing system 100 according to the invention.
  • the layout processing system 100 comprises a scanner module 82.
  • the scanner module 82 scans integrated circuit objects 12, 14 (see Fig. 3A) of the integrated circuit layout 10 and, using the set of design rules 19, identifies groups of integrated circuit objects 12, 14 for which a specific design rule 19 should be valid, identifying so called instances of design rule 19.
  • a particular design rule 19 may define a minimum distance between two integrated circuit objects 12, 14.
  • the scanner module 82 scans the integrated circuit layout 10 and identifies all instances of the particular design rule 19 by identifying groups of integrated circuit objects 12, 14 between which the particular design rule 19 should be valid.
  • the layout processing system 100 further comprises an equation adapter module 102.
  • the equation adapter module 102 is arranged for adapting the set of equations to obtain an adapted set of equations by using a local process value 104.
  • the local process value 104 represents a local discrepancy between an object in a printable circuit layout 30 and a corresponding object in a printed image layout 40.
  • the printable circuit layout 30 is a representation of the integrated circuit layout 10 which is arranged to be manufactured by a manufacturing process 60, 70 (see Fig. 2) of the integrated circuit.
  • the printed image layout 40 results from applying the manufacturing process to the printable circuit layout 30.
  • the equation adapter module 102 only adapts from the set of equations, those equations which are associated with the local process value 104.
  • the equations not associated with the local process value 104 and as such not associated with local discrepancies between objects in the printable circuit layout 30 and corresponding objects in the printed image layout 40 are preferably not adapted.
  • the adapted set of equations is subsequently solved by a solver module 86.
  • the solution found by the solver module 86 provides instructions how the integrated circuit layout 10 should be altered such that a process-corrected layout 50 is obtained. These instructions are provided to the layout-adapter module 88 which subsequently adapts the integrated circuit layout 10 and creates the process-corrected layout 50.
  • the local process value 104 is, for example, obtained by comparing the printable circuit layout 30 and the printed image layout 40 using an image analyzer 1 10.
  • the printed image layout 40 is obtained, for example, by patterning the printable circuit layout 30 using the patterning process 60 (see Fig. 2) or, for example, by modeling the printed circuit layout 30 using the patterning model 70 (see Fig. 2).
  • To some extend local process values 104 may be predicted and manually provided to the equation adapter module 102.
  • This manual input 1 12 is, for example, provided by a designer of the integrated circuit or by an operator of the layout processing system 100.
  • the layout processing system 100 in accordance with the invention only adapts those equations from the set of equations which are associated with the local process value 104.
  • the adaptation of only a limited number of equations from the set of equations reduces the processing time of the layout processing system 100 when correcting the integrated circuit layout 10 for local variations in the manufacturing process 60, 70.
  • Known manufacturing processes generally demonstrate non-linear effects which vary across the printed image layout 30. These non-linear effects may, for example, result from the step of layout imaging 62 (see Fig. 2) using, for example, a patterning tool, or may, for example, result from the step of resist process 64 (see Fig. 2), or may, for example, result from an etching step 66 (see Fig.
  • the local process value 104 represents local discrepancies between objects of the printable circuit layout 30 and associated objects in the corresponding printed image layout 40 due to the patterning process 60 used to produce the printed image objects.
  • a model of the patterning process 60, indicated with patterning model 70 may be used to determine the printed image layout 40 and by comparing the modeled printed image layout 40 with the printable circuit layout 30 the local process value 104 may be determined.
  • Using the local process value 104 when adapting the integrated circuit layout 10 to obtain the process corrected layout 50 non-linearities in the pattering process 60 are accounted for, improving the manufacturability of the integrated circuit.
  • the equation adapter module 102 is arranged for receiving a rating parameter 106, for example assigned to a selection of the objects of the integrated circuit layout 10.
  • the rating parameter 106 indicates an importance of the objects in the selection of objects.
  • the rating parameter 106 may, for example, distinguish between critical objects in the integrated circuit layout 10 and non-critical objects in the integrated circuit layout 10.
  • the equation adapter module 102 may, for example, disregard the local process values 104 associated with the objects of the first selection of objects.
  • the rating parameter 106 may, for example, be manually set by the designer of the integrated circuit layout 10 or by the operator of the layout processing system 100, for example, to manually prevent that a particular selection of objects of the integrated circuit layout is altered by the layout processing system 100.
  • the rating parameter 106 may, for example, also result from the image analyzer 1 10 in which, for example, the image analyzer 1 10 assigns the relatively low rating parameter 106 to a further selection of objects of the integrated circuit layout 10 where the local discrepancy between the object of the printable circuit layout 30 and the associated object of the printed image layout 40 is below a predetermined level.
  • Fig. 2 shows a flowchart indicating the relation between the printable circuit layout 30 and the printed image layout 40.
  • the printable circuit layout 30 is a representation of the integrated circuit layout 10 which can be manufactured using the manufacturing process, which comprises, for example, the patterning process 60 or comprises the patterning model 70 for simulating the pattering process 60.
  • the printable circuit layout 30 may, for example, be the integrated circuit layout 10 in an embodiment where the integrated circuit layout 10 is manufacturable by the manufacturing process.
  • the printable circuit layout 30 may, for example, also be a design-rule-corrected layout 20, which is a representation of the integrated circuit layout 10 corrected for compliance with a set of design rules 19.
  • the printable circuit layout 30 may also be the process- corrected layout 50.
  • the layout processing system 100 is used in an iterative process flow.
  • the layout processing system 100 adapts the integrated circuit layout 10 using, for example, a first set of local process values 104 to generate a first process-corrected layout 50, being a first printable circuit layout 30.
  • the first printable circuit layout 30 is used to obtain a first printed image layout 40, for example, by using the patterning model 70.
  • the first printable circuit layout 30 is compared with the first printed image layout 40 in the image analyzer 1 10 providing a second set of local process values 104.
  • This second set of local process values 104 is subsequently used to generate a second process-corrected layout 50, being a second printable circuit layout 30.
  • the second printable circuit layout 30 is subsequently used to obtain a second printed image layout 40, for example, using the patterning process 60 to obtain a second printed image layout 40.
  • This second printed image layout 40 for example, is processed on the wafer and, for example, results in the integrated circuit.
  • the printable circuit layout 30 may be patterned on a silicon wafer using the patterning process 60.
  • the patterning process 60 comprises, for example, a step of layout imaging 62 during which the printable circuit layout 30 is imaged into a resist layer (not shown) arranged on a surface of the silicon wafer.
  • the patterning of the printable circuit layout 30 may, for example, be done using the wafer-stepper (not shown), or, for example, using an electron-beam patterning tool (not shown).
  • the pattern is fixed in the resist layer by developing the resist during a step of resist process 64 to create a resist image (not shown) of the printable circuit layout 30.
  • the resist image of the printable circuit layout 30 is used as a mask, for example, for an etching step 66 and/or an ion-implanting step 66. Finally, the remaining resist is removed from the silicon wafer, resulting in the printed image layout 40 on the silicon wafer.
  • the printed image layout 40 is simulated from the printable circuit layout 30 using a patterning model 70.
  • the patterning model 70 for example, comprises a lithography model 72, a resist model 74 and an etch and/or implant model 76.
  • the lithography model 72 simulates the influence of the layout imaging step 62
  • the resist model 74 simulates the influence of the resist process 64 step
  • the etch and/or implant model 76 simulates the influence of the etching step and/or ion- implanting step 66 on the printable circuit layout 30.
  • Figs. 3A, 3B, 3C, 3D and 3E show manipulations of objects 12, 14 in a integrated circuit layout 10 to obtain a process-corrected layout 50 using edge placement errors ⁇ L1 , ⁇ L2, ⁇ L3.
  • Fig. 3A shows a first integrated circuit object 12 and a second integrated circuit object 14 of the integrated circuit layout 10.
  • the layout processing system 100 receives the integrated circuit layout 10 and a design rule 19 as input.
  • the dashed double arrow 19 indicates the design rule 19 which should apply to the objects 12, 14 in the integrated circuit layout 10.
  • design rules 19 specify certain geometric and connectivity restrictions to ensure sufficient margins to account for variability in a specific semiconductor manufacturing processes.
  • the design rule 19 indicated in Fig. 3A requires a minimum distance between two objects in the integrated circuit layout 10.
  • the solver module 82 (see Fig. 1 ) of the layout processing system 100 according to the invention scans the integrated circuit layout 10 to find groups of integrated circuit objects 12, 14 for which the design rule 19 should be valid. Finding a group of integrated circuit objects 12, 14 where the design rule 19 should be valid results in an instance of a design rule 19. In the example shown in Fig. 3A the instance of the design rule 19 is found between the first integrated circuit object 12 and the second integrated circuit object 14. The actual distance d1 between the first integrated circuit object 12 and the second integrated circuit object 14 is smaller than a distance prescribed by the design rule 19.
  • This information is passed from the solver module 82 to the equation generator module 84 which generates an equation comprising a mathematical representation of the design rule 19 applied to the group of integrated circuit objects 12, 14.
  • Such equation may, for example, be: F(X12, X13) > DR, (eq1 )
  • X12 is an edge location of the first integrated circuit object 12 facing the second integrated circuit object 14
  • X13 is an edge location of the second integrated circuit object 14 facing the first integrated circuit object 12
  • DR indicates the required minimum distance between two edge locations as prescribed by the design-rule 19.
  • the solver module 86 subsequently finds a solution for the set of equations including the equation eq1 and provides the layout adapter module 88 with information how to adapt the integrated circuit layout 10 to obtain the design-rule corrected layout 20.
  • Fig. 3B shows the design-rule corrected layout 20, where a distance d2 between a first design-rule corrected object 22 (being associated with the first integrated circuit object 12) and the second design-rule corrected object 24 (being associated with the second integrated circuit object 14) is equal to the distance required by the design rule 19.
  • the design-rule corrected layout 20 is subsequently used to generate the printed image layout 40, for example, using the patterning model 70 simulating the patterning process 60 of the manufacturing process of the integrated circuit. Both the design-rule corrected layout 20 and the printed image layout 40 are compared in the image analyzer 1 10 (see Fig. 1 ).
  • Fig. 3C shows a first printed image object 42 (associated with the first design- rule corrected object 22) and a second printed image object 44 (associated with the second design-rule corrected object 24) of the printed image layout 40.
  • Fig. 3C indicates a difference between the printed image layout 40 and the design-rule corrected layout 20.
  • a first edge-placement error ⁇ L1 is identified between an edge of the first printed image object 42 indicated with X41 and an edge of the first design-rule corrected object 22 indicated with X21.
  • a second edge-placement error ⁇ L2 is identified between an edge of the second printed image object 44 indicated with X43 and an edge of the second design-rule corrected object 24 indicated with X23.
  • a third edge- placement error ⁇ L3 is identified between an edge of the second printed image object 44 indicated with X44 and an edge of the second design-rule corrected object 24 indicated with X24.
  • the first, second and third edge-placement errors ⁇ L1 , ⁇ L2, ⁇ L3 represent three local process values 104 (see Fig. 1 ) which represent local discrepancies between printable circuit objects (being the objects 22, 24 of the design- rule corrected layout 20) and printed image objects 42, 44.
  • the local equation adapter module 102 comprises a rating parameter 106 (see Fig. 1 ) indicating the importance of adapting the integrated circuit layout 20 to correct for the local process values 104.
  • the rating parameter of adapting an edge-placement error between objects where an instance of a design rule 19 is violated due to the edge-placement error has a high rating compared to the remaining edge-placement errors.
  • the first and third edge-placement errors ⁇ L1 , ⁇ L3 may be disregarded and the second edge-placement error ⁇ L2 should be corrected for.
  • the equation adapter module 102 subsequently adapts from the set of equations only the equation eq1 which represents the instance of the design rule 19 which is violated by the second edge-placement error ⁇ L2 to obtain the adapted set of equations. This, for example, results in an adapted equation: F(X12, X13 - ⁇ L2) > DR, (eq2).
  • the solver module 86 subsequently finds a solution for the adapted set of equations including the adapted equation eq2 and provides the layout adapter module 88 with information to adapt the integrated circuit layout 10 to obtain the process-corrected layout 50 which is shown in Fig. 3D.
  • the distance between a first process-corrected object 52 (associated with the first integrated circuit object 12) and a second process- corrected object 54 (associated with the second integrated circuit object 14) is larger than required by the design rule 19.
  • Fig. 3E shows a further printed image layout 140 which results from applying the manufacturing process including the patterning process 60 to the process-corrected layout 50. In the further printed image layout 140 there is no remaining edge-placement error between the further printed image objects 142, 144.
  • the different steps in the Figs. 3A to 3E show that using edge-placement errors ⁇ L1 , ⁇ L2, ⁇ L3 as local process value 104 to correct only the equations from the set of equations associated with the local process value 104, results in a process corrected layout 50 which subsequently can be used to manufacture the integrated circuit avoiding critical local discrepancies.
  • These critical local discrepancies may, for example, result from non-linearities in the manufacturing process 60, 70.
  • the set of equations used in the layout processing system 100 may by any suitable equation, for example, linear equations.
  • Figs. 4A and 4B show a determination of a mask error factor (further also referred to as MEF) being a further example of a local process value 104.
  • the mask error factor MEF is a ratio between a mask-variation ⁇ M of an edge location Y26A, Y26B of a printable circuit object 26A, 26B and a variation ⁇ W of a corresponding edge location Y46A, Y46B of a corresponding printed image object 46A, 46B in response to the variation ⁇ M of the edge location Y26A, Y26B of the printable circuit object 26A, 26B.
  • 4A shows an initial printable circuit object 26A of an initial printable circuit layout (not shown), for example, a line on an optical lithography mask (not shown). Patterning the initial printable circuit object 26A either via the patterning process 60 or via the patterning model 70 results in an initial printed image object 46A.
  • Fig. 4B shows a further printable circuit object 26B in which a further edge location Y26B has been altered with respect to an initial edge location Y26A in the initial printable circuit object 26A.
  • a difference between the initial edge location Y26A and the further edge location Y26B represents an induced variation in the printable circuit object, for example, a variation of the optical lithography mask, and is indicated as a mask-variation ⁇ M.
  • Patterning the further printable circuit object 26B using the same pattering process 60, or using the same pattering model 70 results in a further printed image object 46B.
  • a difference between an initial edge location Y46A of the initial printed image object 46A and the further edge location Y46B of the further printed image object 46B represents a resulting variation in the printed image object, for example a variation in the image printed on the silicon wafer, and is indicated as a wafer-variation ⁇ W.
  • the wafer-variation ⁇ W results from the induced mask-variation ⁇ M.
  • the mask error factor MEF predicts how the dimensions of an object in a printed image layout 40 change when the corresponding object in the printable circuit layout 20 is altered.
  • Using the mask error factor MEF when applying a correction to an object of a printable circuit layout 20 to correct for a local discrepancy for example, enables layout processing system 100 according to the invention to predict what correction of an object in the printable circuit layout 20 should be applied such that the resulting object in the printed image layout 40 substantial complies with the required dimensions. Because the required correction of the object to substantially comply with the required dimensions can be predicted using the mask error factor MEF, iteratively applying the layout processing step to a integrated circuit layout 10 is reduced.
  • any reference to objects in layouts such as in the integrated circuit layout, the printable circuit layout, or the printed image layout may refer to polygons being defined by edges or may refer to lines having a predetermined width.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • Use of the verb "comprise” and its conjugations does not exclude the presence of elements or steps other than those stated in a claim.
  • the article "a” or “an” preceding an element does not exclude the presence of a plurality of such elements.
  • the invention may be implemented by means of hardware comprising several distinct elements. In the device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

La présente invention concerne un système de traitement de disposition pour adapter une disposition de circuit intégré ayant des objets de circuit intégré constituant un circuit intégré, pour obtenir une disposition corrigée de traitement, une représentation de la disposition du circuit intégré étant sensiblement corrigée pour les variations de traitement local dans un procédé de fabrication. Le système de traitement de disposition comprend un module adaptateur d'équation pour adapter un ensemble d'équations afin d'obtenir un ensemble adapté d'équations. Chaque équation de l'ensemble d'équations comprend une représentation mathématique d'une règle de conception appliquée aux groupes d'objets de circuit intégré. Le module adaptateur d'équation adapte le jeu d'équations associées à une valeur de traitement local. Les valeurs de traitement local représentent les divergences locales entre un objet d'une disposition de circuit imprimable qui peut être fabriqué par le procédé de fabrication et un objet correspondant d'une disposition d'image imprimée naissant de l'application du procédé de fabrication sur la disposition du circuit imprimable.
PCT/EP2007/056091 2006-06-23 2007-06-19 Système de traitement de disposition WO2007147826A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US81611306P 2006-06-23 2006-06-23
US60/816,113 2006-06-23
US83314106P 2006-07-25 2006-07-25
US60/833,141 2006-07-25

Publications (1)

Publication Number Publication Date
WO2007147826A1 true WO2007147826A1 (fr) 2007-12-27

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8756048B2 (en) 2011-04-15 2014-06-17 Stmicroelectronics S.R.L. Method for technology porting of CAD designs, and computer program product therefor
US10216890B2 (en) 2004-04-21 2019-02-26 Iym Technologies Llc Integrated circuits having in-situ constraints

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002044699A2 (fr) * 2000-11-30 2002-06-06 Sigma-C Gmbh Procede et dispositif pour la determination de proprietes d'un circuit integre
US20030192013A1 (en) * 2002-04-05 2003-10-09 Numerical Technologies, Inc. Method and apparatus for facilitating process-compliant layout optimization

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002044699A2 (fr) * 2000-11-30 2002-06-06 Sigma-C Gmbh Procede et dispositif pour la determination de proprietes d'un circuit integre
US20030192013A1 (en) * 2002-04-05 2003-10-09 Numerical Technologies, Inc. Method and apparatus for facilitating process-compliant layout optimization

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10216890B2 (en) 2004-04-21 2019-02-26 Iym Technologies Llc Integrated circuits having in-situ constraints
US10846454B2 (en) 2004-04-21 2020-11-24 Iym Technologies Llc Integrated circuits having in-situ constraints
US10860773B2 (en) 2004-04-21 2020-12-08 Iym Technologies Llc Integrated circuits having in-situ constraints
US8756048B2 (en) 2011-04-15 2014-06-17 Stmicroelectronics S.R.L. Method for technology porting of CAD designs, and computer program product therefor

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