WO2007146665A2 - Système de distribution d'énergie pour circuits intégrés - Google Patents

Système de distribution d'énergie pour circuits intégrés Download PDF

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Publication number
WO2007146665A2
WO2007146665A2 PCT/US2007/070401 US2007070401W WO2007146665A2 WO 2007146665 A2 WO2007146665 A2 WO 2007146665A2 US 2007070401 W US2007070401 W US 2007070401W WO 2007146665 A2 WO2007146665 A2 WO 2007146665A2
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WIPO (PCT)
Prior art keywords
network
integrated circuit
shunt
interposer
series
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PCT/US2007/070401
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English (en)
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WO2007146665A3 (fr
Inventor
Steve Weir
Scott Mcmorrow
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Teraspeed Consulting Group, Llc
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Priority claimed from US11/757,265 external-priority patent/US7773390B2/en
Priority claimed from US11/757,269 external-priority patent/US20070279882A1/en
Priority claimed from US11/757,261 external-priority patent/US7886431B2/en
Application filed by Teraspeed Consulting Group, Llc filed Critical Teraspeed Consulting Group, Llc
Publication of WO2007146665A2 publication Critical patent/WO2007146665A2/fr
Publication of WO2007146665A3 publication Critical patent/WO2007146665A3/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0231—Capacitors or dielectric substances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/049—PCB for one component, e.g. for mounting onto mother PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array

Definitions

  • the present invention relates to power distribution for integrated circuits (ICs). More specifically, the present invention relates to power distribution for ICs connected to printed circuit boards (PCBs).
  • ICs integrated circuits
  • PCBs printed circuit boards
  • the basic power distribution task can be simply stated as: the power distribution must support load current across the load signal spectrum while maintaining the load voltage within acceptable limits for reliable operation. If the supply voltage substantially changes, the electronic circuit, including ICs, can be unable to maintain normal operation, and the output voltage of the electronic circuit can change, making it impossible to provide normal output signals. The change of output voltage can be interpreted as noise in the output signals. If the noise is large, the electronic circuit can even malfunction.
  • the power distribution system and the power wiring system are designed to have a low impedance.
  • These systems are designed not only to have a low direct current (DC) resistance, but also to have a low impedance with respect to alternating current (AC) or high frequency signals. If the impedance of the power distribution system and power wiring system is low, even when the consumption current of the circuit fluctuates, the fluctuation of the supply voltage is small and the noise of the circuit is also small.
  • the electronic circuit can operate normally, and therefore, the device, including the electronic circuit, operates normally.
  • a noise voltage V n is represented by, where k is a coefficient of 0 to 1 :
  • High loss dielectric is an insulator material used in power wiring that absorbs energy by way of the work done by a changing electric field turning molecular dipoles in the high loss dielectric material. It appears as a frequency dependent resistance across the power rails, absorbing more energy at high frequency than at low frequencies. This is discussed, for example, in Novak '258 (U.S. Patent 6,104,258) and Novak 774 (U.S. Patent No. 6,727,774), discussed below.
  • High skin loss increases the power wiring impedance. On the one hand, this decreases the power distribution system's ability to deliver current, locally increasing the noise amplitude. On the other hand, because high skin loss is dissipative, it suppresses resonance in the power wiring network and suppresses noise propagation.
  • High ESR capacitors flatten the impedance of a given capacitor and provide dissipative shunt loss. For a signal spectrum with a flat maximum amplitude, a network with a constant impedance ideally results in peak to peak noise one half of a network with the same high frequency impedance, but where the impedance at middle or low signal frequencies is much lower, for example, at a ratio of 5:1 , than at high frequencies.
  • the relationship of lower impedance at low frequency(s) versus higher frequency gives rise to a noise high-pass function.
  • the application of a pulse to a high pass filter where the pulse is substantially longer than the filter's time constant affects proximate differentiation of the noise pulse.
  • the noise consists of an impulse at the leading edge, and an impulse at the trailing edge, each of similar magnitude set by the high frequency shunt impedance.
  • the leading impulse recovers close to zero prior to the opposing impulse.
  • the impedance is constant, the response is simply that of a scalar, deflecting from zero for the duration of the pulse and recovering to zero at the end of the pulse.
  • the ESR of a capacitor is high, the ESR dominates capacitor impedance over a broad frequency range and makes it easier to avoid the high pass noise filter characteristic common to filters made with low ESR capacitors.
  • a bypass capacitor is a capacitor of substantial capacity connected between two power wires. Power is always supplied on two or more wires, such as 5 V (volts) and ground; the bypass capacitor is connected between the two wires. If three or more wires, such as 5 V, 3 V, and ground, are used, the bypass capacitor is connected between two wires such as the 5 V wire and ground or the 3 V wire and ground. The bypass capacitor is often connected between ground and other wires, but it is not necessary to provide for all combinations of wires.
  • a theoretical capacitor which by its nature has an impedance that decreases as frequency increases, has an effect of reducing the impedance of the power distribution system in alternating current or high frequency signal situations.
  • a theoretical inductor which by its nature has an impedance that increases as frequency increases, has an effect of increasing the impedance of the power distribution system in alternating current or high frequency signal situations. Therefore, at equal cost and complexity, it is desirable to construct the power distribution system so as to not exhibit any significant inductive characteristic within the load current spectrum.
  • a voltage regulator unit alternatively, a voltage regulator module (VRM)
  • VRM voltage regulator module
  • FIG. 1 A typical arrangement of the power distribution system is shown in Fig. 1 1.
  • An IC package 10 and a voltage regulator module 13 are mounted on a PCB 12.
  • the IC package 10 includes a die 1 1.
  • a power distribution system impedance for an alternating current or high frequency situation viewed from the electronic circuit increases because of the inductance of the wiring connecting the electronic circuit and the power distribution system. Then, when a bypass capacitor is connected near the electronic circuit, the power distribution system impedance viewed from the electronic circuit decreases. Particularly, for high speed electronic circuits, the high frequency characteristic of the power distribution system impedance must be low.
  • a bypass capacitor typically is located very near the electronic circuit for decreasing the inductance between the electronic circuit and the bypass capacitor.
  • bypass capacitor typically is provided sufficiently close to each electronic circuit or for each group of a small number of electronic circuits.
  • This power distribution system impedance reduction technique using bypass capacitors reduces the power distribution system impedance for alternating current or high frequency signals as viewed from the electronic circuit, although the impedance of the wiring connecting the electronic circuit and the power distribution system remains unchanged and in many cases dominates the power distribution impedance.
  • Another power distribution system impedance reduction technique is to increase a cross-section of the power distribution wiring in order to reduce power distribution wiring inductance and power distribution system impedance.
  • the power distribution wiring is often made wide, specifically, in the shape of a plane.
  • a multilayer structure is adopted to provide a power distribution layer, and the power distribution wiring in this power distribution layer is made flat.
  • through holes are required for connecting parts and wires, and the plane of the power distribution layer is perforated like a mesh.
  • ground is also contained in the power distribution wiring.
  • the inductance of the power distribution wiring in the circuit board and that of the power distribution wiring between the bypass capacitor and electronic circuit can be lowered drastically, enabling reduction of the power distribution system impedance for alternating current or high frequency signals.
  • Another technique is to reduce the spacing between the power distribution wires (vertical separation in the case of planar wires) to reduce the inductance, which is similar to the technique of reducing the inductance by increasing the width of the power distribution wires.
  • the two power distribution system impedance reduction techniques, increasing the cross-section of the power wiring and reducing spacing between power distribution wiring, described above can be used in combination and often are used in combination. These techniques are compatible with each other for reducing the power distribution system impedance.
  • Prior art techniques also include gross application of distributed R-L-C networks that attempt to realize a net flat to low-pass noise transfer function for power distribution systems that rely upon power planes.
  • Baudendistel (“Power Bus Decoupling on Multilayer Printed Circuit Boards," TR94-8-023, University of Missouri-Rolla Electromagnetic Compatibility Laboratory, May 1994) discloses how to determine values of damping elements used to suppress power distribution system resonances, which cause high impedances within the power distribution bandwidth. For low frequencies where the impedance of the power plane cavities (L PLN ) is low and where the resistance of the plane (R PLN ) is also low, Baudendistel uses a simple one-dimensional approximation to estimate power distribution system behavior up to the resonance between the bypass capacitor network and any power plane cavity.
  • Baudendistel's model consists of n parallel RLC branches as shown in Fig. 1.
  • the relationship between the frequency and the impedance, Z, based upon this model is shown in Fig. 2.
  • Each branch represents the parallel aggregate for a particular capacitor value.
  • Each parameter, R VAU , L VALI , and C VALI , where i 1 , ..., n, represents the parallel equivalent of the respective value from each device. For example, given ten instances of 1 ⁇ F, 2 m ⁇ , 1 nH capacitors, the branch is represented by a 10 ⁇ F, 0.2 m ⁇ , 0.1 nH capacitor.
  • the parallel plate capacitance of the power/ground wiring cavity is represented by a single capacitor, C PLN -
  • Baudendistel reduces the peaks of the resonances by increasing the magnitude of the resistance, Rx, with respect to the corresponding inductance, Lx, where x is one of 1 , ... , n, so as to flatten the impedance transitions from the region in which the impedance is dominated by the (n-1 ) th inductor (the region that has an upward slope approximated by j ⁇ L V ALn-i) to the region in which the impedance is dominated by the n th capacitor (the region that has a downward slope approximated by 1/(j ⁇ C V ALn))- [0028] Baudendistal enumerates impedance equations for each branch and branches in parallel.
  • each branch exhibits a series resonant frequency, SRF.
  • the VRM interacts primarily with the branch that has the lowest SRF.
  • the inductive reactance j ⁇ L VRM crosses R VRM , as seen on the left side of Fig. 2.
  • the residual impedance at this zero is R VALI - This is best understood by examining the following equation for a given component:
  • ⁇ equivalent Requivalent + j(wL-equ ⁇ valent - 1 /OJUequivalent)
  • Z ⁇ q u ⁇ vended is the total equivalent impedance
  • R ⁇ qU ⁇ V ending is the equivalent resistance
  • Uquivending is the equivalent inductance
  • V ai ⁇ nt is the equivalent capacitance
  • j is the imaginary number V- 1
  • ⁇ is the angular frequency in radians/second.
  • Lee et al. ("Modeling and Analysis of Multichip Module Power Supply Planes," IEEE Transaction on Components, Packaging and Manufacturing Technology; Part B, Vol. 18, No 4, November 1995) refines the model of Baudendistel by including the distributed effects of the power plane cavities and by including the modal resonances, which are shown on the right hand side of Fig. 7, of the power plane cavities that result from wave reflections at the cavity's boundaries.
  • Lee et al. discretizes the power planar cavity into an array of cells as seen in Figs. 4, 5A-5D, and 6. The cell size is selected to be small compared to the wavelength of the highest frequency of interest
  • the cell is then represented either by an equivalent network of resistances, inductances, and capacitance as shown in Figs. 5A-5D or by a square formed by four intersecting transmission lines as shown in Fig. 6.
  • Lee et al. further suppresses resonances by using thin film materials that exhibit high capacitance and significant distributed damping resistance, i.e., the resistance is distributed over the spatial extent of the structure, as opposed to contained in a localized region or discrete component.
  • Lee et al. first offers a model using R-L-C equivalents as shown in Fig. 4. Lee et al. derives the inductance and capacitance values from the complaininger's Equations.
  • Lee et al. defines three types of cells: interior, edge, and corner as seen in Figs. 5A-5C.
  • Lee et al. utilizes transmission lines with an impedance of Z
  • NT V2 * (L/C) 0 5 inside the outer perimeter and transmission lines with twice the Z
  • ZcoRNER 4 * Z
  • NT_JUNC H/X * (2 ⁇ / ⁇ ) .
  • Novak '258 discloses that the impedance depends on the geometry, permittivity, and permeability of the cavity alone. However, Novak '258 does not account for the loading of the bypass and/or the active components. In situations where the board level components substantially load the power cavity impedance or where the frequency is above the first modal resonance, the method taught by Novak '258 does not match the impedance and will allow substantial reflections. [0040] Instead of the edge termination method taught by Novak '258, Yamamura et al. (U.S. Patent 5,844,762) discloses a distribution of damping elements 14 connected to transmission lines 15 substantially throughout the entire printed circuit assembly, as seen in Figs. 8A and 8B. Yamamura et al.
  • Yamamura et al. can successfully address branch resonances taught by Baudendistel by merely following Baudendistal's teachings. It can be seen from Lee et al. that Yamamura et al. fails to address the root cause of modal resonances of the power/ground cavity(s): mismatched impedance at the edge boundaries. It can also be seen from Lee et al. that Yamamura et al. can successfully suppress modal resonances in cases where the damping element impedance is both substantially less than the characteristic impedance of the meshed transmission lines and substantially resistive.
  • Novak '258 and Novak 774 (U.S. Patent No. 6,727,774) teach that to suppress modal resonances, it is sufficient to add termination networks substantially along the PCB boundary so as to match the peripheral impedance to the internal impedance of the plane cavity(s). In doing so, Novak '258 and Novak '774 suppress modal resonances with far fewer components and expense than Yamamura et al.
  • ⁇ 0 is the permeability of free space (approximately 31.9 x 10 "9 webers/ampere)
  • P R is the relative permeability of the conductors (generally 1.0 webers/ampere or very close to 1.0 webers/ampere)
  • H is the dielectric thickness within the plane cavity.
  • the mounted inductance of each capacitor could be about 1 nH, requiring about 160 components.
  • the mounted inductance of each capacitor can be twice as high, requiring double the number of capacitors.
  • a dissipative element 17 with resistive impedance of ZEDG_TERM ZEDG_JUNC (where Z E DG_TERM is the impedance of the dissipative element located on the boundary edge, but not at the corner) is connected to the edge of the transmission lines 18 and nominally reduces the impedance along the boundary edge by half, and thereby matches Z
  • the dissipative element 16 is connected to the corner of the transmission lines 18 and must assume a value that is not only substantively lower than the characteristic impedance of the corner itself, but also lower than the impedance in the center of each adjoining edge.
  • the impedance of the dissipative element 16 located at the corner Z C ORNER_TERM
  • NT _JUNC 1/3 * H/X * (2 ⁇ / ⁇ ) 05
  • This formula is derived by solving for the parallel impedance in the corner required to maintain a uniform impedance along the boundary.
  • any bypass components create frequency dependent alterations in the power distribution system impedance.
  • the distributed bypass and wiring networks can be modeled as simpler one-dimensional branches, similar to the model of Baudendistel.
  • the most troublesome resonance is the transition between the highest frequency R-L-C branch and the lumped power/ground cavity capacitance.
  • power/ground cavity capacitance is very limited and set by:
  • C is the capacitance in Farads
  • Area is the plane cavity surface area
  • Height is the plane cavity thickness
  • ⁇ 0 is the permittivity of free space
  • ⁇ R is the relative permittivity of the dielectric material in the plane cavity.
  • a cavity height of 0.040" is typical for low cost four or six layer construction. Cavity heights of 0.004" are typical for processing of complex fiberglass reinforced PCBs. [0055] Given a uniform or nearly uniform distribution throughout a network of bypass capacitors exhibiting a fixed mounted inductance, the transition frequency between the bypass capacitor network and the power/ground cavity of the PCB depends on the following parameters:
  • ZRES a LcAP_MOUNTED / (RcAP_MOUNTED * CPLN_SQ_IN) ; where F RES is the resonant frequency, Z CHAR is the characteristic impedance of the reactive network consisting of the mounted bypass capacitors and the lumped representation of the power wiring capacitance, and Z RE s is the peak impedance at the pole formed from the bypass capacitor network and the lumped power wiring capacitance.
  • Lee et al. enumerates distributed element modeling of a power distribution system using a two dimensional grid of either discrete R-L-C-G element cells or meshed transmission lines.
  • the aggregate bypass capacitor network aggregates to a single R-L-C branch for each value of capacitor used.
  • the value for R is the parallel mounted ESR of all capacitors of the particular value forming the branch.
  • the value for L is similarly the parallel mounted capacitor inductance.
  • C is the parallel capacitance of the capacitors in the branch.
  • interposer does not use the interposer to reduce power system impedance, to detune power system resonance, and to redistribute input/output (I/O) to reduce noise injection into the PCB power wiring network caused by discontinuous return paths.
  • the decoupling of the Alexander et al. interposer simply provides some non-specific amount of capacitance.
  • the resonant impedance of two parallel branches is theoretically unaffected by the capacitance of the lower frequency branch. Increasing the capacitance of that branch does not help reduce the troublesome resonance. Adding capacitance to the interposer is only beneficial in reducing resonance between the next lower frequency branch and the interposer.
  • a final problem not recognized or addressed in the prior art is the loading effects of bypass devices and IC loads on the power distribution system.
  • the prior art relies upon a presumption that the power distribution system impedance is low compared to the devices served. As device performance increases in frequency and power, establishing such a distribution system becomes difficult and costly, if not impossible.
  • the preferred embodiments of present invention provide isolation of the reactive impedance interdependencies of multiple ICs connected to a common power distribution system, match impedance to IC loads, and effect lower power distribution impedances across wider frequency ranges than currently available.
  • the preferred embodiments of the present invention extend beyond Novak '258 and 774 by loading a cavity boundary with dissipative elements such that the impedance at the boundary remains substantively uniform with the impedance well within the boundary.
  • the preferred embodiments of the present invention provide methods to damp resonance between a bypass capacitor network and a power/ground cavity of the PCB that:
  • the preferred embodiments of the present invention are capable of achieving one or more of the following: 1. Isolating the reactive impedance interdependencies of multiple integrated circuits connected to a common power distribution system;
  • FIGs. 1 -1 1 illustrate prior art techniques.
  • Fig. 12 illustrates an interposer according to a preferred embodiment of the present invention.
  • Fig. 13 illustrates various inductance loops in a PCB.
  • Fig. 14 illustrates an interposer according to a preferred embodiment of the present invention.
  • Fig. 15 illustrates half wave resonators according to a preferred embodiment of the present invention.
  • Fig. 16 illustrates an interposer according to a preferred embodiment of the present invention.
  • FIG. 17A illustrates a known power distribution system.
  • Fig. 17B is a close-up sectional view of signal traces of the known power distribution system illustrated in Fig. 17A.
  • Figs. 18A illustrates a power distribution system according to a preferred embodiment of the present invention.
  • Fig. 18B is a close-up sectional view of signal traces of the known power distribution system according to a preferred embodiment of the present invention illustrated in Fig. 18A.
  • Fig. 19A illustrates a power distribution system according to a preferred embodiment of the present invention.
  • Fig. 19B is a close-up sectional view of signal traces of the known power distribution system according to a preferred embodiment of the present invention illustrated in Fig. 19A.
  • Fig. 2OA illustrates a known possible arrangement of z-axis interconnects.
  • Fig. 2OB illustrates a circuit diagram of the arrangement illustrated in Fig. 2OA.
  • Fig. 2OC illustrates possible z-axis interconnects according to a preferred embodiment of the present invention.
  • Fig. 2OD illustrates a circuit diagram of the arrangement illustrated in Fig. 2OC according to a preferred embodiment of the present invention.
  • Figs. 21 A and 21 B are circuit diagrams of an arrangement of an interposer according to a preferred embodiment of the present invention illustrated, respectively, in
  • the pairs of power and ground planes 1 1 1 of the PCB 1 10 can be paired together to take advantage of mutual inductance and interplane capacitance.
  • the mutual inductance of the power and ground planes 1 1 1 of the PCB 1 10 reduces overall the inductance of the power distribution path. The reduction of inductance of the power distribution path increases the power distribution bandwidth.
  • the interplane capacitance of the power and ground planes 1 1 1 of the PCB 1 10 provides a small amount of energy storage, but interacts with the other parallel inductances in the power distribution system 100. This is a critical parameter at high frequencies.
  • Capacitors 1 12 on the PCB 1 10 provide for energy storage in the power distribution system 100.
  • Capacitors 1 12, 122, and 132 can be mounted on a substrate, including the PCB 1 10, the interposer 120, and the IC package 130, or can be embedded in a substrate.
  • Capacitors 1 12, 122, and 132 can also be mounted on the top or the bottom of the PCB 1 10, the interposer 120, or the IC package 130.
  • Capacitors 1 12, 122, and 132 inherently have some amount of inductance and resistance, along with capacitance, associated with their designs. The inherent inductances and resistances of the mounted capacitors must be taken into account when optimizing power distribution.
  • Capacitors 1 12, 122, and 132 are generally mounted to substrates with metal pads and vias. Capacitors 112, 122, and 132 have inductance associated with the method used for attachment to the substrate. This inductance reduces the power distribution bandwidth and causes interactions with other power distribution elements, including other capacitors and planar capacitance. These interactions must be accounted for in optimizing the power distribution system 100. Capacitors can also be created using planar substrate structures (embedded capacitors (not shown)) for use in high frequency tuning.
  • Tuned planar metal structures within one or more of the substrates can be used to tune the frequency response of the power distribution system. These structures can be used to extend power system bandwidth. These structures include embedded capacitors, embedded inductors, embedded transmission lines, embedded resonators (quarter and half wave), and embedded resistors. Additional resistive elements can be added, either as embedded structures, material property controlled attach structures, or external discrete components, for the purpose of controlling the dampening properties (Q factor) of resonant structures.
  • Plane position can be optimized in the IC package 130, the interposer 120, or the PCB 1 10. Preferably, the plane position is optimized across the entire power distribution system 100. Plane size can also be optimized in the IC package 130, the interposer 120, or the PCB 1 10. The reduction of plane size is used to increase the parallel resonant frequency (PRF) of the power distribution system.
  • the planar metal structures that are used for resonance tuning/detuning can be located in the IC package 130, the interposer 120, or the PCB 110.
  • Internal metal structures can be fabricated so as to perform electrical compensation, i.e., form equivalent lumped network parasitics and/or quarter/half wave resonant structures designed as compensating elements, and automatically track the substrate material and fabrication process.
  • Any structure used as a compensating element that is formed from a portion of another larger structure that also contains a third structure being compensated exhibits the same electrical property changes as the third element in response to manufacturing variations, as well as the operating environment.
  • a capacitor formed from one portion of a plane that is used as a compensating element to a resonant pole formed by a larger portion of the same plane and discrete components will proportionately track the capacitance of the larger plane section.
  • Resistors can be used for termination, i.e., resistive elements in any form can be used to match the impedance of a transmission structure and can be used for resonance Q factor reduction techniques. Resistors can be disposed as discrete devices on the top or the bottom of the IC package 130, the interposer 120, or the PCB 1 10 or can be embedded in the IC package 130, the interposer 120, or the PCB 1 10. Resistors can be formed as embedded substrate elements, utilizing standard embedded resistors processes. Resistors can be formed using other materials, such as controlled resistance attachment solders and epoxies. These materials can include epoxy adhesives that include a combination of conductive and/or semiconductive materials suspended in a colloid prior to curing. Exemplary materials include, but are not limited to: copper, aluminum, silver, iron, tin, nickel, gold, carbon, silicon, combinations and alloys thereof.
  • inductance loops can be optimized as discussed below.
  • the inductance through a capacitor 200 can be optimized by device selection and pad attachment design or by location of the closer power or ground plane 205 of the PCB 208 that the capacitor attaches to.
  • the inductance through capacitor vias 201 can be optimized by the design of the vias 204, by via separation, by the location of the further power or ground plane 205, or by the use of additional vias.
  • the inductance caused by ground and power plane spreading 202 can be optimized by the separation of plane 205 pairs or by the distance between the capacitor 207 and the IC package 206.
  • the inductance through IC attach 203 can be optimized by the design of vias 204, by via separation, or by the use of additional vias.
  • Optimization methods for the power distribution system include one or more of gross impedance reduction, planar inductance reduction, and delivered power inductance reduction.
  • Gross impedance reduction can be achieved by increasing the capacitance relative to the inductance with discrete or internal planar capacitors, decreasing the mounted capacitor inductance, and/or by optimized mounting solutions, which include through the measurement of the impedance, through the electromagnetic field simulation of the power distribution system, or through the optimized positioning of the components, and optimizing the power wiring inductance.
  • Planar inductance reduction can be achieved by reducing the separation between power/ground planes, (cavity height), and/or use of multiple plane sets in parallel.
  • Inductance between the bypass capacitors and the power wiring can be achieved by selection of the Z-axis plane location with respect to the capacitor mounting locations. Additionally, the geometry and quantity of the Z axis interconnects between the power wiring structure, typically planes, and any given capacitor and/or capacitor groups impacts the effective inductance of such an interconnect. [0099] Similarly, inductance between the power wiring and any given IC is subject to the distance between the power wiring plane(s) and the IC die. As with the bypass capacitors, the geometry and quantity of interconnects between the power wiring structure and the die determines the total inductance. In both cases, because it is desirable to minimize inductance materials with the lowest relative permeability, 1.0 is assumed. Non-ferrous metals such as copper, silver, and other suitable metals have relative permeabilities of about 1.0. Interconnects include PCB vias, traces, polygon fills, and other suitable interconnects.
  • Optimization methods for the power distribution system can include one or more of the following impedance reduction methods: 1. Pole/Zero Compensation Method; 2. Pole/Pole Compensation Method;
  • each pole pair results from the parallel resonance between the inductance of a first network branch with the capacitance of a second network branch.
  • a branch includes one or more elements.
  • the first network branch consists of the equivalent transfer function of a voltage regulator module connected to the power system wiring as a first shunt branch.
  • Additional shunt branches typically include a quantity of capacitors of a single value in each branch also connected across the power wiring network as shown, for example, in Figure 1.
  • Each branch N exhibits a higher self-resonant frequency than the preceding branch N-1.
  • the characteristic impedance defined by the ratio of the mounted inductance to the capacitance, of all branches is equal. As demonstrated by Baudendistal, with sufficient resistive impedance in each branch, impedance variations of the power distribution system can be suppressed.
  • Each branch results in a complex admittance (the inverse of impedance) that shunts the power wiring network.
  • Most reactive interaction occurs between branches in pairs determined by the self-resonant frequency of each branch. This can be expressed in a simplified view as the inductance of branch N-1 interacting with the capacitance of branch N, for example, branches C va n and C va i 2 shown in Figure 1.
  • branch SRFs are tightly spaced significant interaction occurs between more diverse branches.
  • the power wiring networks exhibit self impedances very similar to bypass capacitors. From DC to a frequency defined by the structure geometry, the insulator effective permittivity (dielectric constant), and the location within the network, the power wiring network self-impedance decreases with increasing frequency and the phase remains close to -90 Q . At the defined frequency, a zero singularity occurs. The minimum impedance is reached at the zero as the phase quickly transitions from nearly -90 Q through 0 Q and to nearly +90 Q , where it remains up to the first half wave modal resonance associated with an impedance peak. Locations near the center of the power wiring network exhibit the highest frequency zero, while those closest to the power wiring network edges exhibit the lowest frequency zero.
  • F Z ERO 2,400MHz / (Width
  • F ZERO 1600MHz / (Inches * ⁇ R 05 ), where Inches is the length of a full side of the plane.
  • This optimization method includes the suppression and the outright elimination of the resonant behavior by altering the net phase characteristics of the loaded power wiring structure.
  • the optimal variation is a practical balance that depends substantively on the zero frequencies of the power wiring structure.
  • the shunt network can be designed with a series of branches each with its own zero such that the self impedance of the composite network remains within 135 Q electrical of the power wiring network self-impedance phase at any point in the power wiring network.
  • the shunt network can include one or more planar capacitors formed into the same or additional substrates as the power wiring network.
  • This optimization method can include the steps of, among others: 1. Determine the maximum tolerable high frequency self impedance of the power wiring network; 2. Determine from the physical size of the power wiring network required whether the power wiring network must meet the stipulated impedance at or above the half wave mode represented by a structure with a nominal ⁇ R for the preferred dielectric cavity material, typically 4.0;
  • additional shunt network(s) is(are) arranged such that the phase response between the IC die and the power distribution system is controlled by a third shunt element.
  • the third shunt network has a series resonant frequency at or near the parallel resonant frequency of the first and second components/networks, has a Q factor of about 2 or less, and has a characteristic impedance of the reactive elements that is not more than about 2.0 x V(Lf irst /C S ⁇ cond), where L f ⁇ rst is the inductance of the first element or network and C S ⁇ CO nd is the capacitance of the second element or network.
  • the Q factor and the SRF of the third shunt network can be set by using any of the techniques discussed above.
  • the third shunt network can be arranged to be included in the PCB 1 10, in the interposer 120, or the IC package 130 as shown in Fig. 12. It is possible that the third shunt network can be arranged to be included on more than one of the PCB 1 10, the interposer 120, and the IC package 130.
  • the interposer 120' can include top 123a and bottom 123b tiers on wings 123, where the bottom tier 123b elevates the top tier 123a above the components 1 13 such that the interposer 120' can have a greater area compared to the interposer 120 of Fig. 12 without an elevating bottom tier 123b.
  • the additional area of the top tier 123a allows for the placement of additional components, including capacitors 122, on the interposer
  • interposer 120, 120' include one or more of the following:
  • the capacitance of the third shunt network can be set, for example, by dividing the planes embedded in the PCB 1 10.
  • the divided planes of the third shunt network can form an island such that the remaining portion of the planes completely surround the divided planes of the third shunt network, or the divided planes of the third shunt network can include at least one edge of the PCB 1 10 such that the remaining portion of the planes of the PCB 1 10 do not completely surround the divided planes of the third shunt network.
  • the third shunt network can also include a resistive component that is formed from a planar structure formed in a PCB 1 10.
  • the third shunt network is inserted in series between the first network and the second network.
  • the third series network when loaded by the first network, has a parallel resonant frequency at or near the parallel resonant frequency of the first and second networks, has a Q factor of about 2 or less, and has a characteristic impedance of the reactive elements of not more than about 2.0 x V(Lf irst /C S ⁇ cond), where L f ⁇ rst is the inductance of the first element or network and C S ⁇ CO nd is the capacitance of the second element or network.
  • the third series network described can include a resistive component formed from a planar structure formed in a printed circuit structure.
  • the capacitive and inductive reactances of the third series network can be formed by the combination of a discrete surface mount capacitor and printed-circuit etch features.
  • the surface mount capacitor can be of an X2Y® design, feedthrough capacitor, or transmission line capacitor such as NEC® Proadlizer®.
  • a refinement of the pole-zero optimization method and the pole-pole optimization method is when the individual resonant networks are formed from groups of networks, where at least one of the networks can be composed of a plurality of capacitors where:
  • the capacitances within the at least one network can span a narrow range using multiple successive E12 series values. For example, use of 1 nF,
  • the mounting structure can include variations in via diameter, via to via spacing, and geometry of via to component pad etch.
  • the resulting network has a greatly lowered Q factor compared with a network composed of a single discrete capacitor value, and in many cases obviates the need for a discrete resistance element in order to achieve a low Q factor response.
  • An additional optimization method includes providing a first series of quarter- wave resonator stubs 302 that emanate from the power distribution vias 301 of each IC as shown in Fig. 15.
  • the vias 301 can be located in the PCB 1 10, the interposer 120, or the IC package 130.
  • the frequencies of the first series of quarter-wave resonator stubs 302 are selected to correspond to the half wave resonances of the uncompensated power distribution system.
  • the impedances of the first series of quarter-wave resonator stubs 302 are selected in linearly ascending values with frequency to minimize the negative impact of the half-wave resonance modes that result from each the first series of quarter-wave resonator stubs 302.
  • a second series of quarter-wave resonator stubs can also be provided to compensate the half-wave modes resulting from the first series of quarter-wave resonator stubs, resulting in an overall frequency response that has a much flatter impedance than achievable with a like planar area and layer count.
  • the second series of quarter-wave resonator stubs can be located in the same plane as the first series of quarter-wave resonator stubs or can be located in a different plane.
  • the second series of quarter-wave resonator stubs can be located in a different device from the first series of quarter-wave resonator stubs 302.
  • the first series of quarter-wave resonator stubs 302 can be located in the PCB 1 10
  • the second series of quarter-wave resonator stubs can be located in the interposer 120 or 120'.
  • This optimization method is most applicable when the compensation structure is in IC packages or interposers. However, this optimization method can also be used when the compensation structure is in PCBs. Thin dielectrics, with or without high dielectric constant materials, can be used with this optimization method because these materials exhibit much lower inherent Q factors because of the higher ratio of the resistive skin loss to the inductance.
  • Another optimization method minimizes the cost of power distribution elements by optimizing the transition frequency from the discrete PCB level bypass capacitors to either the capacitance within the IC or to the planar bypass elements (power planes), by setting the transition frequency to a value from between about 1.8 times, but no more than about 2.2 times the non-return-to-zero (NRZ) bit frequency of the highest frequency noise generating source of any substantial power.
  • the transition frequency is a function of the following parameters:
  • Thickness of planar cavity insulator material H;
  • This optimization method minimizes the integral of the product of combined IC/PCB/bypass network impedance and noise source energy.
  • the NRZ energy exhibits a frequency spectra with a "comb" shape where the peaks decline on a linear slope from half the bit repetition rate to the highest odd multiple of half the bit repetition rate within approximately 0.5 divided by the signal rise-time, beyond which signal energy drops much more rapidly. Between the impedance peaks are substantial impedance nulls.
  • This optimization method places a resonance within one of the nulls above the third harmonic of the highest possible data rate, typically between the third and fifth harmonics at 1.8 to 2.2 times the clock rate. This placement of the resonance guarantees that for an arbitrary data pattern, the ninth harmonic is the lowest bit rate harmonic that can align to the transition frequency. Values as low as 1.65 can be used with the impairment that the seventh harmonic of a low frequency bit pattern excites 1.75-times the maximum bit rate.
  • An optimization technique consists of selecting a bypass capacitor areal density such that the resulting resonance between the bypass capacitor network combined with the shunt impedance of any other devices, such as ICs, occurs at a frequency that can be practically damped with the use of one of the aforementioned compensation techniques.
  • the above described optimization methods can be used for a single IC on a PCB or multiple ICs on a PCB.
  • the optimization methods can be used separately or in combination with one another.
  • the pole-zero optimization method will be used, either separately or in combination with the other optimization methods.
  • An interposer 120, 120' that can include discrete bypass capacitors 122 can be placed between an IC package 130 and an application PCB 1 10.
  • the interposer 120, 120' may preferably include a series of metallic layer planes 121 , e.g., copper, laminated between organic dielectric materials.
  • An IC package 130 can be mounted to the top of the interposer 120, 120' in a normal solder reflow or adhesive cure process. Any other suitable method can also be used to mount the IC package 130.
  • the interposer 120, 120' outline is substantially larger than the attached IC package 130 to allow for attachment of discrete bypass capacitors 122 and other discrete components as required by the application.
  • the interposer 120, 120' can include one or more power supply functions implemented with linear or switch mode methods. [0123] The interposer 120, 120' typically attaches to the application PCB 1 10 using normal solder reflow or conductive adhesive cure process. Other suitable methods of attaching the interposer 120,120' can also be used.
  • the interposer power distribution cavities are typically each composed of thin, less than or equal to about 35 ⁇ m or about 1 mil, dielectric cavities. The thickness and the dielectric constant of each cavity is selected according to the needs of the IC package 130 for which the interposer 120, 120' is designed.
  • Discrete bypass capacitors 122 are typically attached to the upper surface of the interposer 120, 120' (IC package 130 mounting side), but can also attach to the bottom surface of the interposer 120, 120'.
  • the power distribution for a single power rail can consist of (1 ) a cavity over substantially the entire extent of the interposer 120, 120', (2) multiple such cavities, or (3) a subsection of such a cavity, as determined by the power requirements of the die 133 and the IC package 130 that the interposer 120, 120' is designed to interface.
  • the interposer 120, 120' can include the use of resistive elements in any and/or all forms, including discrete surface mount components, planar resistors such as Ohmega, and/or vertical contact resistors formed from a cured epoxy/carbon and/or copper or silver matrix.
  • Resistive elements can occur in any combination of (1 ) in series between the power cavity(s) and the application PCB attachment on the interposer bottom side, (2) in series with the discrete bypass capacitors 122 mounted on the interposer 120, 120', (3) in series with the cavity subsections on the interposer 120, 120', and (4) in series between the interposer power cavity(s) and the IC package 130.
  • the interposer 120, 120' can include one or more pole-zero cancellation networks to suppress the resonance between the discrete bypass capacitors 122 and the power cavity(s) in the interposer 120, 120'.
  • the interposer 120, 120' can include one or more pole-zero cancellation networks to reject the propagation of energy that occurs at or near resonances within the attached IC package 130 to and from the application PCB 1 10.
  • the interposer 120, 120' can include one or more pole-zero cancellation networks to suppress the resonance between the attached IC package 130 and the interposer power cavity(s) and the discrete bypass capacitors 122. [0129] The interposer 120, 120' can include one or more pole-pole cancellation networks to suppress the resonance between the discrete bypass capacitors 122 and the power cavity(s) in the interposer 120, 120'.
  • the interposer 120, 120' can include one or more pole-pole cancellation networks to suppress the resonance between the interposer 120, 120' and the attached
  • the interposer 120, 120' can be constructed such that the resonance on a given voltage rail between the discrete bypass capacitors 122 and the interposer power cavity(s) lies from about 1.8 times to about 2.2 times the clock frequency of the highest
  • the interposer 120, 120' can be constructed such that the resonance on a given voltage rail between the composite interposer 120, 120' and attached IC package
  • the interposer 120, 120' can include one or more quarter wave resonating structures, as shown in Fig. 15, to suppress the modal resonances of any given power cavity(s) in the interposer 120, 120'.
  • the interposer 120, 120' can include one or more low pass filter structures to limit the high frequency content of the IC I/O signals.
  • the interposer 120, 120' can include one or more transient suppression devices to provide protection to one or more IC pins.
  • the interposer 120, 120' can include one or more linear or switching power supply circuits to regulate power to the IC package 130.
  • the interposer 120, 120' can include a power cavity close to the top surface of the interposer 120, 120' and matching power cavity near the bottom of the interposer 120, 120' connected through a plurality of vertical interconnects, typically vias, so as to minimize the inductance between the bypass components attached to either side of the interposer 120, 120' and both the attached IC package 130 and PCB 1 10.
  • the benefit of such an arrangement is reduced power supply impedance presented to both the IC die 133 of the IC package 130 and the application PCB 1 10.
  • This reduced impedance in both directions serves to substantively reduce transmission path discontinuities that occur when a planar signal line in the PCB 1 10 references one or the other voltage nodes of the respective I/O power rail, while the vertical interconnects from the PCB 1 10 through the interposer 120, 120' and the IC package 130 references either the other respective voltage node or a combination of the two voltage nodes of the respective I/O voltage rail.
  • the interposer 120, 120' improves the return path into the IC package 130 (not shown in Fig. 21 C or 21 D) regardless of the I/O voltage plane, v d d or v ss , referenced by the application signal in the signal trace 1 14 on the PCB 1 10, as shown in Figs. 21 A and 21 C and in Figs. 21 B and 21 D.
  • This permits possible reduction of the number of plane layers required in the application PCB 1 10 and permits possible improvement in signal performance that cannot be matched by any known PCB construction.
  • the interposer 120, 120' can remap the connections from the IC package 130 to the application PCB 1 10 to any or any combination of purposes: a. Reduce crosstalk between I/O signals by more optimal arrangement than the original IC; and b. Simplify power interconnect on the application PCB.
  • the interposer 120, 120' can include attachment interconnects to the application PCB 1 10 outside the perimeter of the IC package 130. These interconnects can be used for any combination of purposes:
  • the interposer 120' can include wings 123, which extend beyond the portion of the interposer 120' having an array of IC package interconnects connected to the IC package 130, that provide locations for the bypass capacitors 122.
  • the interposer 120' can include one or more wings. Because the bypass capacitors 122 are located on the wings 123, neither the bypass capacitors 122 nor their respective vertical interconnects compete with the vertical IC package interconnects between the substrate of the interposer 120' and the PCB 1 10 (not shown in Fig. 16) or the horizontal interconnects between the vertical IC package interconnects and the IC package 130 or IC die 133 (neither shown in Fig. 16).
  • the wings 123 are formed to include a limited number of power and power return vertical interconnects 124 to join the substrate of the interposer 120' with the PCB 1 10. As a result, the following benefits are realized:
  • bypass capacitors 122, and their associated vertical interconnect are not required to be close to the substrate. Instead, the low density power interconnects 124 are readily traversed by signal traces 1 14 while maintaining generous overlap of signal traces 114 by the associated reflection plane. This is seen by comparing Figs. 17 and 18.
  • Prior Art Fig. 17 shows a conventional IC package 401 connected to a PCB 400.
  • Bypass capacitors 402 are attached to both surfaces of the PCB 400.
  • the bypass capacitor interconnects 404 perforate the PCB 400.
  • Signal traces 403 on reflection plane 405 must be routed around both the bypass capacitor interconnects 404 and the signal interconnects 406. Fig.
  • FIG. 18 shows a subassembly 41 1 , which can be an interposer or an IC package according to one of the preferred embodiments of the present invention, connected to a PCB 410.
  • Bypass capacitors 412 are attached to subassembly 41 1.
  • the bypass capacitor interconnects do not perforate the PCB 410 because they are located on the subassembly 41 1.
  • Signal traces 413 that reference reflection plane 414 must be routed around only the signal interconnects 416.
  • bypass capacitors 122 join to voltage nodes through planar interconnects.
  • Vertical signal interconnect 125 does not substantively compete with the bypass capacitor locations or interconnects. 3.
  • bypass capacitor 122 to bypass capacitor 122 inductance can be minimized, thus reducing the Q factor and the effects of parallel resonance between the bypass capacitors 122 of different values.
  • Fig. 19 shows a subassembly 421 , which can be an interposer or an IC package according to one of the preferred embodiments of the present invention, connected to a PCB 420.
  • Bypass capacitors 422 are attached to subassembly 421. The bypass capacitor interconnects do not perforate the PCB 420 because they are located on the subassembly 421.
  • the power interconnects 427 are located at the periphery of the subassembly 421 , the power interconnects 427 can be made less dense. Signal traces 423 on reflection plane 425 must be routed around both the power interconnects 427 and the signal interconnects 426. However, because the power interconnects 427 are less dense, the routing of the signal traces 423 is easier.
  • vertical interconnects consist of 10mil drill holes, with 20mil diameter capture pads and 28mil clearance diameters (anti-pads) on unconnected layers.
  • 4mil trace with 4mil space typically 50 Ohm over 4mil dielectric
  • a second trace would require at a minimum: 4mil trace, 4mil space, second 4mil trace, for 12mils total, slightly violating the anti-pads, and risking an electrical short.
  • the anti-pad raises the trace impedance.
  • the wings 123 of the interposer 120' can be populated at a lower density, such as about 78.7mil (2mm) pitch.
  • six traces can be routed, equivalent to three traces for each of the two columns. Additionally all six traces run over solid plane and so do not suffer significant impedance modulation as a result of traversing the additional vertical power interconnect.
  • the larger effective working radius of the interconnect substantially improves the inductance of the vertical interconnect between the interposer 120, 120' and the PCB 1 10 reduces the inductance between the interposer 120, 120' and the PCB 1 10 improving the noise filtering performance of the capacitors 122 included on the interposer 120, 120' with respect to the PCB 1 10.
  • the small inductance of the in-package power cavities can be manipulated to enhance high frequency noise rejection between the IC package 130 / die 133 and the PCB 1 10.
  • Fig. 2OA shows an array of interconnects that include v ss 501 and v d d 502 power interconnects and signal interconnects 503.
  • the distance between the v ss power interconnect 501 and the v dd power interconnect 502 is approximately 1.4 times the pitch between adjacent interconnects.
  • Signal interconnects couple 70% with the closest v d d 502 / v ss 501 power interconnect and 30% with the closest v ss 501 / v dd 502 power interconnect.
  • Fig. 2OC also shows an array of interconnects that include v ss 501 and v dd 502 power interconnects and signal interconnects 503.
  • the signal interconnects 503 are arranged in array with a plurality of v ss power interconnects 502 interspersed in the array of signal interconnects 503, and the v ss 501 and v dd
  • power interconnects are arranged outside of the array of signal interconnects 503.
  • the distance between adjacent v ss power interconnects 501 and v d d power interconnects arranged outside of the array of signal interconnects 503 is approximately the pitch between adjacent interconnects.
  • an IC package 130 can include discrete bypass capacitors 132 placed on the periphery of a packaged integrated circuit, where the IC package 130 has been extended beyond the boundaries normally required by its signal and power delivery pins.
  • the IC package 130 is typically composed of a series of metallic planes 131 , e.g. copper, laminated between organic dielectric materials, as part of a standard IC package process.
  • An IC die 133 can be mounted to the top of the IC package 130 in a normal solder reflow or adhesive cure process.
  • the IC die 133 can be mounted to the IC package 130 by any suitable method.
  • the IC package 130 outline is substantially larger than what would normally be required by the IC die 133 to allow for attachment of additional bypass capacitors 132 and other discrete components (not shown) as required by the application.
  • the IC package 130 can include one or more switch mode power supply functions.
  • the IC package 130 can attach to an interposer 120, 120' as shown in Figs. 12 and 14 or can be directly attached to the application PCB 1 10 using any suitable method, including using normal solder reflow, conductive adhesive cure process, pins, or land grid array structures, sockets, or other interposing structures.
  • the IC package power distribution cavities are typically each composed of thin, less than or equal to about 35 ⁇ m or about 1 mil, dielectric cavities. The thickness and the dielectric constant of each cavity is selected according to the needs of the IC for which the IC package 130 is designed.
  • Bypass capacitors 132 can be attached to the upper surface of the IC package 130 or can be embedded within the IC package 130.
  • the power distribution for a single power rail can include (1 ) a cavity over substantially the entire extent of the IC package, (2) multiple such cavities, or (3) a subsection of such a cavity, as determined by the power requirements of the IC die 133 and the IC package 130.
  • the IC package 130 can include the use of resistive elements in any and/or all forms, including discrete surface mount components, planar resistors such as Ohmega, and/or vertical contact resistors formed from a cured epoxy/carbon and/or copper or silver matrix.
  • Resistive elements can occur in any combination of (1 ) in series between the power cavity(s) and the application PCB 1 10, (2) in series with the discrete bypass capacitors 132 mounted on the IC package 130, (3) in series with the cavity subsections on the IC package 130, and (4) in series between the package power cavity(s) and the IC package 130.
  • the IC package 130 can include one or more pole-zero cancellation networks to suppress the resonance between the discrete capacitors and the power cavity(s) in the IC package 130.
  • the IC package 130 can include one or more pole-zero cancellation networks to reject the propagation of energy that occurs at or near resonances to and from the application PCB 1 10.
  • the IC package 130 can include one or more pole-zero cancellation networks to suppress the resonance between the attached die 133 and the IC package power cavity(s) and the bypass capacitors 132.
  • the IC package 130 can include one or more pole-pole cancellation networks to suppress the resonance between the discrete bypass capacitors 132 and the power cavity(s) in the IC package 130.
  • the IC package 130 can include one or more pole-pole cancellation networks to suppress the resonance between the IC package 130 and the attached IC die 133.
  • the IC package 130 can be constructed such that the resonance on a given voltage rail between the discrete bypass capacitors 132 and the package power cavity(s) lies from about 1.8 times to about 2.2 times the clock frequency of the highest
  • the IC package 130 can be constructed such that the resonance on a given voltage rail between the composite IC package 130 and the attached IC die 133 lies from about 1.8 times to about 2.2 times the clock frequency of the highest I/O frequency on a given power rail of the attached IC package 130.
  • the IC package 130 can include one or more quarter wave resonating structures to suppress the modal resonances of any given power cavity(s) in the IC package 130.
  • the IC package 130 can include one or more low pass filter structures to limit the high frequency content of the IC I/O signals passing to and from the power wiring of the application PCB 1 10.
  • the IC package 130 can include one or more transient suppression devices to provide protection to one or more IC pins.
  • the IC package 130 can include one or more linear or switching power supply circuits to regulate power to the IC package 130.
  • the IC package 130 can include a power cavity close to the top surface of the IC package 130 and a matching power cavity near the bottom of the IC package 130 connected through a plurality of vertical interconnects, typically vias, to minimize the inductance between the bypass components attached to the IC package 130 and the PCB 1 10. The benefit of such an arrangement is reduced power supply impedance presented to both the IC die 133 and the application PCB 1 10.
  • This reduced impedance in both directions serves to substantively reduce transmission path discontinuities that occur when a planar signal line in the PCB 1 10 references one or the other voltage nodes of the respective I/O power rail, while the vertical interconnects from the PCB 1 10 through the IC package 130 references either the other respective voltage node or a combination of the two voltage nodes of the respective I/O voltage rail.
  • this improves both I/O signal fidelity, and reduces the noise, including EMI that would otherwise propagate through the application PCB I/O power cavity(s).
  • the IC package 130 improves the return path into the IC die 133 regardless of the I/O voltage plane referenced by the application signal. This permits possible reduction of the number of plane layers required in the application PCB 1 10.
  • the IC package 130 can remap the usual connections from the IC die 133 to the application PCB 1 10 to any or any combination of purposes:
  • the IC package 130 can include attachment interconnects to the application PCB 1 10 outside the known perimeter of the IC package. These interconnects can be used for any combination of purposes:

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Abstract

Le système de distribution d'énergie pour circuits intégrés selon l'invention comprend des procédés d'atténuation de la résonance entre un réseau de condensateurs de dérivation et une cavité d'énergie/de terre de la carte de circuit imprimé qui (a) ne nécessite pas de quantités excessives de composants de dérivation/atténuation ou (b) ne nécessite pas de capacités de cavité plane élevée ou en variante peut assurer une Q inférieure à 1,4 à la transition depuis le réseau de dérivation vers le recouvrement d'impédance de la cavité plane.
PCT/US2007/070401 2006-06-06 2007-06-05 Système de distribution d'énergie pour circuits intégrés WO2007146665A2 (fr)

Applications Claiming Priority (12)

Application Number Priority Date Filing Date Title
US80408906P 2006-06-06 2006-06-06
US60/804,089 2006-06-06
US88714807P 2007-01-29 2007-01-29
US60/887,148 2007-01-29
US88714907P 2007-01-30 2007-01-30
US60/887,149 2007-01-30
US11/757,269 2007-06-01
US11/757,261 2007-06-01
US11/757,265 US7773390B2 (en) 2006-06-06 2007-06-01 Power distribution system for integrated circuits
US11/757,269 US20070279882A1 (en) 2006-06-06 2007-06-01 Power distribution system for integrated circuits
US11/757,261 US7886431B2 (en) 2006-06-06 2007-06-01 Power distribution system for integrated circuits
US11/757,265 2007-06-01

Publications (2)

Publication Number Publication Date
WO2007146665A2 true WO2007146665A2 (fr) 2007-12-21
WO2007146665A3 WO2007146665A3 (fr) 2008-12-04

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TW (1) TW200826753A (fr)
WO (1) WO2007146665A2 (fr)

Cited By (1)

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US9241400B2 (en) 2013-08-23 2016-01-19 Seagate Technology Llc Windowed reference planes for embedded conductors

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TWI842654B (zh) * 2023-12-01 2024-05-11 亞福儲能股份有限公司 用於複合電力系統的控制器以及電能管理方法

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US3414832A (en) * 1964-12-04 1968-12-03 Westinghouse Electric Corp Acoustically resonant device
US4096362A (en) * 1977-06-20 1978-06-20 Bell Telephone Laboratories, Incorporated Automatic cable balancing network
US6588005B1 (en) * 1998-12-11 2003-07-01 Hitachi, Ltd. Method of manufacturing semiconductor integrated circuit device
US6608259B1 (en) * 1999-11-26 2003-08-19 Nokia Mobile Phones Limited Ground plane for a semiconductor chip
US20050280146A1 (en) * 2004-06-17 2005-12-22 Cornelius William P Interposer containing bypass capacitors for reducing voltage noise in an IC device

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US3414832A (en) * 1964-12-04 1968-12-03 Westinghouse Electric Corp Acoustically resonant device
US4096362A (en) * 1977-06-20 1978-06-20 Bell Telephone Laboratories, Incorporated Automatic cable balancing network
US6588005B1 (en) * 1998-12-11 2003-07-01 Hitachi, Ltd. Method of manufacturing semiconductor integrated circuit device
US6608259B1 (en) * 1999-11-26 2003-08-19 Nokia Mobile Phones Limited Ground plane for a semiconductor chip
US20050280146A1 (en) * 2004-06-17 2005-12-22 Cornelius William P Interposer containing bypass capacitors for reducing voltage noise in an IC device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9241400B2 (en) 2013-08-23 2016-01-19 Seagate Technology Llc Windowed reference planes for embedded conductors

Also Published As

Publication number Publication date
TW200826753A (en) 2008-06-16
WO2007146665A3 (fr) 2008-12-04

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