WO2007145883A1 - Hybrid memory device with single interface - Google Patents
Hybrid memory device with single interface Download PDFInfo
- Publication number
- WO2007145883A1 WO2007145883A1 PCT/US2007/013127 US2007013127W WO2007145883A1 WO 2007145883 A1 WO2007145883 A1 WO 2007145883A1 US 2007013127 W US2007013127 W US 2007013127W WO 2007145883 A1 WO2007145883 A1 WO 2007145883A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory
- type
- controller
- data
- flash
- Prior art date
Links
- 230000015654 memory Effects 0.000 claims abstract description 160
- 239000000872 buffer Substances 0.000 claims description 15
- 230000003139 buffering effect Effects 0.000 claims description 3
- 230000009977 dual effect Effects 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 2
- 238000012546 transfer Methods 0.000 description 9
- 238000013507 mapping Methods 0.000 description 7
- 238000013461 design Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 4
- 238000007726 management method Methods 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006266 hibernation Effects 0.000 description 1
- 238000003032 molecular docking Methods 0.000 description 1
- 238000010397 one-hybrid screening Methods 0.000 description 1
- 238000011022 operating instruction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0638—Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/20—Employing a main memory using a specific memory technology
- G06F2212/202—Non-volatile memory
- G06F2212/2022—Flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/20—Employing a main memory using a specific memory technology
- G06F2212/205—Hybrid memory, e.g. using both volatile and non-volatile memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
Definitions
- DRAM dynamic random access memory
- Such devices include mobile phones, television set- top boxes, personal computer memory, and so forth.
- Increasingly computing devices are also including large amounts of relatively inexpensive nonvolatile NAND flash memory to store applications and data..
- a hybrid memory device that includes a first type of memory (e.g., volatile DRAM- type memory) and an interface corresponding to the first type of memory, and a second type of memory (e.g., nonvolatile flash-type memory) .
- the memory device includes a controller that is coupled to the interface, to the first type of memory and to the second type of memory. Based on information such as commands and/or memory addresses received at the interface, the controller determines whether a command such as an I/O request (e.g., a read or write) is directed to the first type of memory or to the second type of memory.
- a command such as an I/O request (e.g., a read or write) is directed to the first type of memory or to the second type of memory.
- a controller of the hybrid memory device by receiving commands, addresses and data at a controller of the hybrid memory device, different types of memory may be accessed by software (e.g., device firmware or a program) via a single interface defined for one type of memory.
- the controller includes logic that determines whether a command / address received on the interface of a first type of memory is directed to a second type of memory associated with the memory device, and if so, outputs signals to the second type of memory to communicate at least one command to the second type of memory and/or to perform at least one data input / output (I/O) operation on the second type of memory.
- I/O data input / output
- FIGURE 1 shows an illustrative example of a computing device into which various aspects of the present invention may be incorporated.
- FIG. 2 is a representation of an example hybrid memory device including a controller and two types of memory that are each accessible by a single interface defined for one of the memory types .
- FIG. 3A is a representation of an example hybrid memory device with an SDRAM interface with SDRAM and flash memory that is accessed via a designated block of memory in SDRAM addressable space .
- FIG. 3B is a representation of an example hybrid memory device with an SDRAM interface with SDRAM and flash memory that is accessed via a plurality of designated blocks of memory in SDRAM addressable space .
- FIG. 4 is a representation of addressable memory space corresponding to a first type of memory with sections used for communicating data and commands with a second type of memory.
- FIG. 5 is an example representation of one suitable type of SDRAM device that may be incorporated into a hybrid memory device .
- FIG. 6 is an example representation of a hybrid memory device with an SDRAM interface containing an SDRAM device such as the device of FIG. 5 and a flash device.
- FIG. 7 is an example representation of a timing diagram for controlling an SDRAM device and a flash device.
- FIG. 8 is a representation of example steps corresponding to how the controller may output flash data to a SDRAM device configured for burst data output .
- FIG. 9 is a representation of how flash may be added to a dual inline memory module (DIMMM) for adding flash to DRAM-based (including SDRAM) personal computer memory.
- DIMM dual inline memory module
- FIGURE 1 illustrates an example of some suitable functional components of a computing device 188, such as may be found in a handheld / pocket-sized / tablet-type personal digital assistant, appliance, mobile phone and so forth, including a processor 189, a memory 190, a display 192, and a keyboard 193 (which may be a physical or virtual keyboard) .
- the memory 190 generally includes both volatile memory (e.g., RAM) and nonvolatile memory (e.g., ROM, PCMCIA cards, and so forth) . Further, as described below, the exemplary memory 190 includes a hybrid memory device
- An operating system 193 may be resident in the memory 190 and executes on the processor 189, such as a Microsoft 0 Windows ® -based operating system, or another operating system.
- One or more application programs 194 and data 195 may be in the memory 190, e.g., with the programs 194 run on the operating system 193. Examples of applications include email programs, scheduling programs, PIM (personal information management) programs, word processing programs, spreadsheet programs, Internet browser programs, and so forth.
- the computing device 188 may also include other components 196 such as a notification manager loaded in the memory 190, which executes on the processor 189. The notification manager for example may handles notification request, e.g., from the application programs 195.
- the computing device 188 has a power supply 197, for example implemented as one or more batteries or a light- powered system.
- the power supply 197 may further include an external power source that overrides or recharges the built- in batteries, such as an AC adapter or a powered docking cradle.
- the exemplary computing device 188 represented in FIG. 1 is shown with three example types of external output devices, including the display 192, other output mechanisms 198 (e.g., one or more light emitting diodes, or LEDs) and an audio generator 199, e.g., coupled to integrated speakers and/or to an audio jack.
- output devices may be directly coupled to the power supply 197 so that when activated, it remains on for a duration dictated by a notification mechanism even though the processor 189 and other components might shut down to conserve battery power.
- an LED may remain on (as long as some power is available) until the user takes action.
- Others may be configured to turn off when the rest of the system does or at some finite duration after activation.
- Various aspects of the technology described herein are generally directed towards expanding a memory of a computing device (such as the device 188) with respect to having relatively large amounts of volatile and nonvolatile memory in the computing device, without requiring changes to an existing physical architecture of that computing device.
- the description herein provides examples of incorporating NAND flash memory into a SDRAM-based device by adding or substituting a hybrid memory device (e.g., comprising one or more chips) containing SDRAM and the NAND flash, in which the hybrid memory device has the same interface (including pinout, voltage protocol, and access protocol) as a conventional SDRAM component.
- DRAM dynamic random access memory
- DRAM dynamic random access memory
- SDRAM dynamic random access memory
- NOR-based flash memory may be mixed with SDRAM and/or with NAND-based flash
- static RAM (SRAM) or other types of RAM may be one of the types of memory, more volatile memory can be added in place of an existing volatile memory device, more nonvolatile memory can be added in place of an existing nonvolatile memory device, and so forth.
- incorporating of different memory types into a hybrid memory device typically adds overall memory to a device, but need not necessarily increase (and if desired by the designer can decrease) the amount of the original type of memory and/or the overall amount of memory.
- the concepts described herein are not limited to what are considered conventional computing devices (e.g., desktop, notebook, laptop, or tablet-based computer systems, personal digital assistants, pocket-sized personal computers, or the like), but rather may be used in any device that .has a need for storing data in volatile or non-volatile memory, including mobile phones, set-top-boxes, hybrid hard disks, television sets, remote controls, audiovisual devices, electrical appliances, household appliances and so forth. Each of these devices may add nonvolatile memory to a volatile memory design, or vice-versa, or increase memory, without costly and risky hardware redesigns .
- volatile or non-volatile memory including mobile phones, set-top-boxes, hybrid hard disks, television sets, remote controls, audiovisual devices, electrical appliances, household appliances and so forth.
- Each of these devices may add nonvolatile memory to a volatile memory design, or vice-versa, or increase memory, without costly and risky hardware redesigns .
- a device with volatile memory such as a mobile phone can now have large amounts of non-volatile storage included in it such as to store programs, music, images, and so forth, simply by replacing a memory chip ⁇ or multiple memory chips) , and updating some firmware to work with the non-volatile storage, as described below.
- FIG. 2 of the drawings there is shown a general example concept of a hybrid memory device 202 device including volatile memory 204 (e.g., SDRAM) and nonvolatile memory 206 (e.g., NAND flash) .
- volatile memory 204 e.g., SDRAM
- nonvolatile memory 206 e.g., NAND flash
- a controller 208 contains logic that determines which of the memories 204 or 206 to access, based on addresses and commands, e.g., originated at firmware / software and addressed through a a CPU.
- the controller 208 may include or otherwise be associated with a buffer set 210 comprising one or more buffers, which in one implementation is used for speed matching purposes.
- a buffer set 210 comprising one or more buffers, which in one implementation is used for speed matching purposes.
- the buffer set 210 typically comprises memory such as SDRAM or static RAM (SRAM) that is at least as fast as a given SDRAM chip and its protocol requires, otherwise the hybrid device at times would appear to external components to be bad memory.
- FIG. 3A shows an example concept of how one hybrid memory device 302A generally operates, in which flash memory 306 is arranged as some number of blocks (e.g., blocks F-I through F-n) and is accessed through an SDRAM interface.
- the hybrid memory device 302A also includes an SDRAM device 304.
- an on-chip controller 308A e.g., corresponding to the controller 208 of FIG. 2 determines which section of SDRAM 304 or flash to access with respect to a current address originated at the CPU 389.
- the controller 308A receives commands, data and addresses from the CPU 389 that are. output according to the conventional SDRAM protocol. Note that the CPU is not required to know anything about the different types of memory on the hybrid chip, and operates as normal over its existing SDRAM-based bus.
- the controller 308 includes logic that can detect addresses sent to the hybrid device's SDRAM address lines that are part of its interface. Some of the addresses in ' the addressable address range correspond to SDRAM, and for those addresses, the controller 308A allows the addresses, commands and data to be handled by the SDRAM device 304 (e.g., forwards the equivalent ones and zeros or does not disable the device from seeing the ones and zeros) . As a result for those addresses the hybrid device acts as a conventional SDRAM device.
- Certain addresses in the addressable range are known to the controller 308 to be associated with the flash, and essentially act as a window into the flash memory 306.
- the designated block may correspond to the flash block size, e.g.,' 128 KB in one type of flash device.
- the SDRAM device 304 is disabled (actually or effectively) by the controller 308.
- the controller 308 instead sends commands to the flash memory device 306, or controls the flow of read and write data to the flash memory device 306.
- the controller 308 may disable the SDRAM component 304 by changing an appropriate device input line (e.g., chip enable) of the device 304 to disable, by not forwarding received addresses to the device 304, and/or by forwarding the addresses (e.g., if needed for refresh) but not allowing data writes or returning any data for a read.
- an appropriate device input line e.g., chip enable
- the controller 308 may disable the SDRAM component 304 by changing an appropriate device input line (e.g., chip enable) of the device 304 to disable, by not forwarding received addresses to the device 304, and/or by forwarding the addresses (e.g., if needed for refresh) but not allowing data writes or returning any data for a read.
- the amount of flash 306 is not limited to the size of the designated block 320; rather there may be multiple flash blocks (or other arrangements of flash memory) , with the controller 308 accessing each block or the like according to additional mapping information that identifies which part (e.g., block) of the
- This additional mapping information may be written to other memory locations known to the controller 308, e.g., at the high end of addressable memory, (or possibly as a supplement to the designated block) .
- Firmware 330 already present on essentially all computing devices, may be updated to read and write this information in accordance with a suitable protocol via the CPU 389, (as represented in FIG. 3A by the dashed lines from the firmware 330 through the CPU 389 to the controller 308A; in this manner, commands, data and status information 332 may be communicated between the device firmware 330 (and/or other requesting code, hereinafter referred to as the firmware 330 for simplicity) and the hybrid memory device 302A.
- FIG. 3B is a representation of a similar concept to that of FIG.
- FIG. 3A except that in FIG. 3B the alternative controller 308B may have multiple buffers 310-1 and 310-2 corresponding to multiple windows 320A and 320B f separately mapped to multiple flash blocks (e.g., currently flash block Al and Flash block BO in FIG. 3B) .
- multiple flash blocks e.g., currently flash block Al and Flash block BO in FIG. 3B
- FIG. 3B any practical number may be used.
- mapping 4 shows a linearly-represented address range 440 corresponding to the range of a conventional SDRAM device, which in this example is 4 Mwords by 16 bits, ⁇ ox purposes of simplicity, the mapping will be described with respect to the single designated block 320 of FIG. 3A, however it can be readily understood that separate mapping may be performed in essentially the same manner.
- the last two blocks corresponding to the SDRAM address space are used by the controller 308 and firmware 330 as a command channel 444 and data channel 442 to the flash memory device 306.
- the mapping and other information 332 (FIG.
- the controller 308 may be read and written by the controller 308 via any suitable protocol understood by the controller 308 and the source of that additional information (e.g., firmware code 330) .
- additional information e.g., firmware code 330
- the controller 308 accessing the additional information 332 (or 333 in FIG. 3B) at the controller 308, e.g., the last two one kilobyte word blocks, command and . data paths for communicating with the flash device 306 are established. Other information may also be in these spaces.
- the device firmware 330 can use this section of memory to employ a bootstrapping protocol by which the firmware 330 can determine whether the memory device is truly a hybrid device, because in general the hybrid memory device 302A of FIG. 3 otherwise would be indistinguishable from a conventional SDRAM device.
- Other possible data communicated via these blocks may, for example, inform the controller 308A where the designated block 320 is (or blocks in FIG. 3B are) located within the addressable memory; e.g., in this manner, the designated blocks can move, including dynamically if desired.
- one suitable command protocol comprises a serial protocol used to transfer address block and command information (e.g., 332 in FIG. 3A) for the flash device.
- the protocol is configurable to access different types of flash devices; e.g., one type of NAND device uses a NOR SRAM interface, whereby the control logic accesses blocks of data, which are then be serialized to suit the SDRAM data delivery protocol.
- Write data to the flash 306 will likewise be converted by the controller 308A as required by the flash protocol, e.g., 2 KB is written at a time to one such flash device.
- the protocol includes a way for the controller 308A to signal to the firmware 330 when a flash read or write request is busy and when the request is ready.
- A- status register in the location 332 may be used.
- the firmware 330 sends a read or write command via the command block 332; the status, which may be a bit that is part of the command, is set by the controller upon receiving a flash request to zero to indicate busy.
- the controller 308A need not flip the status to busy if on a read request the controller 308A knows that the designated block already contains the correct data for the current mapping.
- the controller 308A sets the .status to busy and for a read, and begins filling the buffer 310 with the requested data.
- the controller 308A toggles the status to ready.
- the firmware 330 which is polling the status since it sends the request, then knows the requested data can be read, which the controller 308A then outputs from the buffer 310.
- the controller will output a single set of data (e.g., byte) for the requested address if a single output is requested, or a timed burst output of multiple sets of data starting with that address, with the number of sets output corresponding to the current burst mode .
- the current burst mode may be established via a hardwired setting, including a setting that indicates the burst mode is soft-controlled; in any event the mode is known to the controller 308A via the SDRAM-equivalent setup lines and/or a command (for soft- controlled burst) .
- the flash memory is overlaid in the SDRAM address space.
- a command protocol e.g., serial
- the buffer of a conventional disk drive may be replaced with a single chip upgrade that provides flash storage, whereby the flash storage can be used with new firmware to upgrade existing drives to hybrid drives .
- Further examples include adding nonvolatile storage to a set-top-box design, or a mobile phone design that was designed with no built-in mass storage at the time, but is now desirable, e.g., due to some new application or business model.
- FIGS. 5 and 6 demonstrate the use of actual SDRAM and NAND Flash devices, with the interface and internal components configured for one example SDRAM voltage protocol and SDRAM access protocol, whereby only software changes (e.g., in device firmware) are needed to now make use of the nonvolatile memory in the package.
- software changes e.g., in device firmware
- FIGS. 5 and 6 show the use of 16 bit data paths, which is a common application, although as can be readily appreciated, other data path widths work in the same manner.
- the SDRAM device 504 represented in FIG. 5 comprises a burst mode device (e.g., a Micron MT48LC4M16A2 device) supporting 1 byte, 2 byte, 8 byte, or page transfers, and for example, may be used in a hybrid memory device 602 (FIG. 6) that includes two gigabits of NAND Flash 606.
- a burst mode device e.g., a Micron MT48LC4M16A2 device
- FIG. 6 a hybrid memory device 602 (FIG. 6) that includes two gigabits of NAND Flash 606.
- the hybrid memory device accepts RAS/CAS (the well-known row access strobe and column access strobe) signals on the address lines (e.g., AO-AIl, BAO-BAl), and for other than single byte reads or writes, reads or writes data sequentially from the RAS/CAS starting address.
- RAS/CAS the well-known row access strobe and column access strobe
- the computing device that uses this type of memory buffers the serially accessed data, which is typically done by the onboard cache in many computing devices .
- the (relatively low latency) memory controller 308 between the host (e.g., CPU) and the SDRAM 504 is able to detect the addresses being sent to the chip. By detecting particular address ranges, the CE# (enable) for the SDRAM interface can be- used to place the device 504 into a refresh cycle, with data provided by another source.
- the control logic of the controller 308 detects addresses sent to the SDRAM. As described above, when addresses within the designated block are transferred, the controller knows the request is for the flash; note that in this example architecture, the SDRAM device is disabled by preventing CE# passing to the device.
- the controller's control logic can then either send commands to the flash device 606, or via data transfer logic control the flow of read and write data to the flash device.
- the command stream to the SDRAM device is not interrupted, and the initialization of the multi-chip package device requires only that the control logic detect the operating burst mode for the SDRAM to understand the data bursts to be used when transferring flash data to the memory data bus.
- the control logic detect the operating burst mode for the SDRAM to understand the data bursts to be used when transferring flash data to the memory data bus.
- the Flash device represented in FIG. 6 (e.g., a Micron"" MT29F2G16AABWP device) has a multiplexed bus, whereby data I/O, addresses, and commands share the same pins.
- I/O pins I/O [15: 8] are used only for data in the xl6 configuration, with addresses and commands supplied on I/O [7:0] .
- the command sequence normally includes a command latch cycle, an address latch cycle, and a data cycle, either read or write. Control Signals CE#, WE#, RE#, CLE, ALE and WP# control flash device read and write operations.
- CE# and CE2# each control independent 4Gb arrays.
- CE2# functions the same as CE# for its own array, and operations described for CE# also apply to CE2#.
- CE# is used to enable the device.. When CE# is low and the device is not in the busy state, the flash memory will accept command, data, and address information. When the device is not performing an operation, the CE# pin is typically driven high and the device enters standby mode. The memory will enter standby if CE# .goes high while data is being transferred and the device is not busy. This helps reduce power consumption.
- the CE# "Don't Care" operation allows the NAND Flash to reside on the same asynchronous memory bus as other flash or SRAM devices . Other devices on the memory bus can then be accessed while the NAND Flash is busy with internal operations. This capability is for designs that require multiple NAND devices on the same bus, e.g., one device can be programmed while another is being read.
- a HIGH CLE signal indicates that a command cycle is taking place.
- a HIGH ALE signal signifies that an address input cycle is occurring. Commands are written to the command register on the rising edge of W ⁇ # when CE# and ALE are LOW, and CLE is high and the device is not busy. Exceptions to this are the read status and reset commands .
- commands are transferred to the command register on the rising edge of WE#; commands are input on lines I/O [7:0] only.
- lines I/O [15: 8] need to be written with zeros when issuing a command.
- Addresses are written to the address register on the rising edge of WE# when CE# and CLE are low, and ALE is high and the device is not busy.
- Addresses are input on I/O [7:0] only,- for devices with a xl6 interface, I/O [15: 8] needs to be written with zeros when issuing an address. Generally all five address cycles are written to the device. An exception to this is the block erase command, which requires only three address cycles.
- the flash device exemplified herein is a multiplexed device, whereby the address, commands and data flow across a simple 16-bit interface in a serial fashion.
- FIG. 7 exemplifies the serial nature of the address command and data transfer protocol timing to the exemplified flash device. Note that address, commands and data are sent from the SDRAM interface (which is non-multiplexed) by writing sequentially to the command and data blocks. [0050] As described above, by detecting writes to the command block in the address space of the SDRAM, the data required can be transferred to the flash device by the controller 508. The address transfer shown above can be expanded to show the transfer of address information to the flash device.
- the address information for the flash memory is transferred by performing multiple writes to the command block address on the SDRAM. SDRAM data in this area is unavailable, since the device would be deselected for these writes. In this serial manner the address data and command information can be written and read from the Flash device .
- the control logic implements further command protocols as described above, e.g., to permit the flash device to be isolated from the SDRAM device speed considerations. For example, by buffering the status of the flash device in the control logic, additional command responses that indicate busy and execution status may be added to the serial protocol . Data and status returned from the flash device are buffered into a small block of SRAM in the data transfer' logic, so that the read and write speeds to flash match that of the SDRAM.
- FIG. 8 A typical example of serial transfer to the flash device is represented in FIG. 8, which represents example reads and writes by the firmware 330 to the SDRAM address space 332 (FIG. 3) that is reserved for- controlling the flash 306.
- the firmware sends a flash command at step 802 by writing an IDLE command to the address space 332 which the controller detects.
- the firmware sends a flash block address request, comprising five address writes that indicate which block to use and which address, along with one write command to the command address space .
- the controller then has the information it needs to perform the write.
- the firmware 330 polls for the status by issuing a write command an a burst read, looping via step 810 until the ready status is detected, and the flash read burst (step 812) is sent.
- a register-based protocol provides access to the flash by loading a series of registers, including writing a register with a busy word set to start the execution of the command. This allows a single page write to initiate the writing or fetching of flash block or blocks.
- the busy word is 'toggled by the controller when the command has been completed.
- Supported commands include fetch address/block (or fetch address range) , write address/block (or write address range) , and delete address/block (or delete address range) .
- FIG. 9 is an example representation of a dual- inline memory module (DIMM) 902, exemplifying how flash may be added to conventional personal computer system memory.
- DIMM dual- inline memory module
- the physical flash chips may be on the same side as the SDRAM chips, on the opposite side, or both.
- the controller may be on the DIMM itself, or alternatively may be external to it, with the ability to disable the SDRAM and substitute flash data as desired.
- the BIOS firmware tests for the presence of the hybrid DIMM memory, and if present, loads at least some of the SDRAM memory (its code) from the flash.
- the presence of the non-volatile flash memory enables boot or resume operations from data stored in flash. For example, data is accessed from the CPU memory cache which is mapped to blocks of memory and resolved from either SDRAM or flash. If sufficient flash is present, the entire SDRAM may be preserved for hibernation purposes, or the entire operating system loaded, without needing to access peripheral devices such as a hard disk drive .
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Memory System (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
- Dram (AREA)
Abstract
Description
Claims
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2007800212183A CN101473438B (en) | 2006-06-07 | 2007-06-01 | Hybrid memory device with single interface and method |
BRPI0711731-0A BRPI0711731A2 (en) | 2006-06-07 | 2007-06-01 | single-interface hybrid memory device |
EP07795704.1A EP2025001B1 (en) | 2006-06-07 | 2007-06-01 | Hybrid memory device with single interface |
MX2008014859A MX2008014859A (en) | 2006-06-07 | 2007-06-01 | Hybrid memory device with single interface. |
ES07795704T ES2718463T3 (en) | 2006-06-07 | 2007-06-01 | Hybrid memory device with a single interface |
KR1020087029847A KR101159400B1 (en) | 2006-06-07 | 2007-06-01 | Hybrid memory device with single interface |
JP2009514323A JP2009540431A (en) | 2006-06-07 | 2007-06-01 | Hybrid memory device with one interface |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/449,435 | 2006-06-07 | ||
US11/449,435 US7716411B2 (en) | 2006-06-07 | 2006-06-07 | Hybrid memory device with single interface |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2007145883A1 true WO2007145883A1 (en) | 2007-12-21 |
Family
ID=38823267
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2007/013127 WO2007145883A1 (en) | 2006-06-07 | 2007-06-01 | Hybrid memory device with single interface |
Country Status (11)
Country | Link |
---|---|
US (2) | US7716411B2 (en) |
EP (1) | EP2025001B1 (en) |
JP (2) | JP2009540431A (en) |
KR (1) | KR101159400B1 (en) |
CN (1) | CN101473438B (en) |
BR (1) | BRPI0711731A2 (en) |
ES (1) | ES2718463T3 (en) |
MX (1) | MX2008014859A (en) |
RU (1) | RU2442211C2 (en) |
TW (1) | TWI420302B (en) |
WO (1) | WO2007145883A1 (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100987332B1 (en) | 2008-11-07 | 2010-10-18 | 서울대학교산학협력단 | Memory management device according to memory hierarchy |
CN102326154A (en) * | 2008-12-23 | 2012-01-18 | 苹果公司 | Architecture for address mapping of managed non-volatile memory |
US8611123B2 (en) | 2010-09-15 | 2013-12-17 | Samsung Electronics Co., Ltd. | Complex semiconductor device for use in mobile equipment |
JP2014078231A (en) * | 2012-10-08 | 2014-05-01 | Hgst Netherlands B V | Device and method for low power, low delay and large capacity storage class memory |
WO2014139047A1 (en) * | 2013-03-14 | 2014-09-18 | Micron Technology, Inc. | Memory systems and methods including training,data organizing,and/or shadowing |
US9342402B1 (en) | 2014-01-28 | 2016-05-17 | Altera Corporation | Memory interface with hybrid error detection circuitry for modular designs |
US9658783B2 (en) | 2013-03-27 | 2017-05-23 | Hitachi, Ltd. | DRAM having SDRAM interface and flash memory consolidated memory module |
JP2017102943A (en) * | 2017-01-10 | 2017-06-08 | マイクロン テクノロジー, インク. | Memory system including training, data reconstruction, and/or shadowing, and method |
US9811263B1 (en) | 2014-06-30 | 2017-11-07 | Altera Corporation | Memory controller architecture with improved memory scheduling efficiency |
US9911477B1 (en) | 2014-04-18 | 2018-03-06 | Altera Corporation | Memory controller architecture with improved memory scheduling efficiency |
Families Citing this family (183)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8250295B2 (en) | 2004-01-05 | 2012-08-21 | Smart Modular Technologies, Inc. | Multi-rank memory module that emulates a memory module having a different number of ranks |
US20080082763A1 (en) | 2006-10-02 | 2008-04-03 | Metaram, Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
US8796830B1 (en) | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
US7392338B2 (en) | 2006-07-31 | 2008-06-24 | Metaram, Inc. | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits |
US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US8077535B2 (en) | 2006-07-31 | 2011-12-13 | Google Inc. | Memory refresh apparatus and method |
US7386656B2 (en) | 2006-07-31 | 2008-06-10 | Metaram, Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
US8327104B2 (en) | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
US8130560B1 (en) | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
US20080028136A1 (en) | 2006-07-31 | 2008-01-31 | Schakel Keith R | Method and apparatus for refresh management of memory modules |
US8041881B2 (en) | 2006-07-31 | 2011-10-18 | Google Inc. | Memory device with emulated characteristics |
US8619452B2 (en) | 2005-09-02 | 2013-12-31 | Google Inc. | Methods and apparatus of stacking DRAMs |
US8060774B2 (en) | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
US8438328B2 (en) | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
US8090897B2 (en) | 2006-07-31 | 2012-01-03 | Google Inc. | System and method for simulating an aspect of a memory circuit |
US8055833B2 (en) | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US8081474B1 (en) | 2007-12-18 | 2011-12-20 | Google Inc. | Embossed heat spreader |
US8089795B2 (en) | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
US9542352B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US8359187B2 (en) | 2005-06-24 | 2013-01-22 | Google Inc. | Simulating a different number of memory circuit devices |
US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
US7724589B2 (en) | 2006-07-31 | 2010-05-25 | Google Inc. | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits |
US7516293B2 (en) * | 2006-09-08 | 2009-04-07 | International Business Machines Corporation | Increased performance using mixed memory types |
US8745315B2 (en) | 2006-11-06 | 2014-06-03 | Rambus Inc. | Memory Systems and methods supporting volatile and wear-leveled nonvolatile physical memory |
US8135900B2 (en) * | 2007-03-28 | 2012-03-13 | Kabushiki Kaisha Toshiba | Integrated memory management and memory management method |
JP5032172B2 (en) * | 2007-03-28 | 2012-09-26 | 株式会社東芝 | Integrated memory management apparatus and method, and data processing system |
US8427891B2 (en) * | 2007-04-17 | 2013-04-23 | Rambus Inc. | Hybrid volatile and non-volatile memory device with a shared interface circuit |
US8301833B1 (en) | 2007-06-01 | 2012-10-30 | Netlist, Inc. | Non-volatile memory module |
US8904098B2 (en) | 2007-06-01 | 2014-12-02 | Netlist, Inc. | Redundant backup using non-volatile memory |
US8874831B2 (en) | 2007-06-01 | 2014-10-28 | Netlist, Inc. | Flash-DRAM hybrid memory module |
US8209479B2 (en) | 2007-07-18 | 2012-06-26 | Google Inc. | Memory circuit system and method |
DE102007038543B4 (en) * | 2007-08-16 | 2022-09-01 | Robert Bosch Gmbh | Companion chip for use in a motor controller |
US8080874B1 (en) | 2007-09-14 | 2011-12-20 | Google Inc. | Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween |
US9201790B2 (en) * | 2007-10-09 | 2015-12-01 | Seagate Technology Llc | System and method of matching data rates |
US8332572B2 (en) * | 2008-02-05 | 2012-12-11 | Spansion Llc | Wear leveling mechanism using a DRAM buffer |
US8352671B2 (en) * | 2008-02-05 | 2013-01-08 | Spansion Llc | Partial allocate paging mechanism using a controller and a buffer |
US8209463B2 (en) * | 2008-02-05 | 2012-06-26 | Spansion Llc | Expansion slots for flash memory based random access memory subsystem |
US8275945B2 (en) * | 2008-02-05 | 2012-09-25 | Spansion Llc | Mitigation of flash memory latency and bandwidth limitations via a write activity log and buffer |
JP2009211192A (en) * | 2008-02-29 | 2009-09-17 | Toshiba Corp | Memory system |
US8082384B2 (en) | 2008-03-26 | 2011-12-20 | Microsoft Corporation | Booting an electronic device using flash memory and a limited function memory controller |
US20090313416A1 (en) * | 2008-06-16 | 2009-12-17 | George Wayne Nation | Computer main memory incorporating volatile and non-volatile memory |
US10236032B2 (en) * | 2008-09-18 | 2019-03-19 | Novachips Canada Inc. | Mass data storage system with non-volatile memory modules |
US8599625B2 (en) | 2008-10-23 | 2013-12-03 | Marvell World Trade Ltd. | Switch pin multiplexing |
CN101510174B (en) * | 2008-11-07 | 2012-05-02 | 慧帝科技(深圳)有限公司 | Quickflashing remember data updating management method and related memory card |
US20140325129A1 (en) * | 2008-12-31 | 2014-10-30 | Micron Technology, Inc. | Method and apparatus for active range mapping for a nonvolatile memory device |
US8327087B1 (en) * | 2008-12-31 | 2012-12-04 | Micron Technology, Inc. | Method and apparatus for an always open write-only register based memory mapped overlay interface for a nonvolatile memory |
KR101583002B1 (en) * | 2009-02-23 | 2016-01-21 | 삼성전자주식회사 | Computing system booting method and code/data pinning method thereof |
WO2010144624A1 (en) | 2009-06-09 | 2010-12-16 | Google Inc. | Programming of dimm termination resistance values |
CN102063939B (en) * | 2009-11-18 | 2015-01-28 | 中兴通讯股份有限公司 | Method and device for implementing electrically erasable programmable read-only memory |
CN102110057B (en) * | 2009-12-25 | 2013-05-08 | 澜起科技(上海)有限公司 | Memory module and method for exchanging data in memory module |
US8612809B2 (en) | 2009-12-31 | 2013-12-17 | Intel Corporation | Systems, methods, and apparatuses for stacked memory |
WO2011106049A1 (en) | 2010-02-23 | 2011-09-01 | Rambus Inc. | Time multiplexing at different rates to access different memory types |
US8924645B2 (en) | 2010-03-08 | 2014-12-30 | Hewlett-Packard Development Company, L. P. | Data storage apparatus and methods |
US20110255335A1 (en) * | 2010-04-20 | 2011-10-20 | Alessandro Grossi | Charge trap memory having limited charge diffusion |
US20120026802A1 (en) * | 2010-07-30 | 2012-02-02 | Emanuele Confalonieri | Managed hybrid memory with adaptive power supply |
KR101670055B1 (en) * | 2010-08-30 | 2016-11-09 | 삼성전자 주식회사 | Method for controlling the digital image processing appratus, digital image processing appratus, communication system |
JP2012063874A (en) * | 2010-09-14 | 2012-03-29 | Toshiba Corp | Selector changing over chip select signal, storage device, and electronic apparatus |
EP2453377A1 (en) * | 2010-11-15 | 2012-05-16 | Gemalto SA | Method of loading data into a portable secure token |
US10817502B2 (en) | 2010-12-13 | 2020-10-27 | Sandisk Technologies Llc | Persistent memory management |
US9208071B2 (en) | 2010-12-13 | 2015-12-08 | SanDisk Technologies, Inc. | Apparatus, system, and method for accessing memory |
US10817421B2 (en) | 2010-12-13 | 2020-10-27 | Sandisk Technologies Llc | Persistent data structures |
WO2012116369A2 (en) * | 2011-02-25 | 2012-08-30 | Fusion-Io, Inc. | Apparatus, system, and method for managing contents of a cache |
US9176671B1 (en) | 2011-04-06 | 2015-11-03 | P4tents1, LLC | Fetching data between thread execution in a flash/DRAM/embedded DRAM-equipped system |
US9158546B1 (en) | 2011-04-06 | 2015-10-13 | P4tents1, LLC | Computer program product for fetching from a first physical memory between an execution of a plurality of threads associated with a second physical memory |
US9170744B1 (en) | 2011-04-06 | 2015-10-27 | P4tents1, LLC | Computer program product for controlling a flash/DRAM/embedded DRAM-equipped system |
US8930647B1 (en) | 2011-04-06 | 2015-01-06 | P4tents1, LLC | Multiple class memory systems |
US9164679B2 (en) | 2011-04-06 | 2015-10-20 | Patents1, Llc | System, method and computer program product for multi-thread operation involving first memory of a first memory class and second memory of a second memory class |
US10838646B2 (en) | 2011-07-28 | 2020-11-17 | Netlist, Inc. | Method and apparatus for presearching stored data |
US10380022B2 (en) | 2011-07-28 | 2019-08-13 | Netlist, Inc. | Hybrid memory module and system and method of operating the same |
US10198350B2 (en) | 2011-07-28 | 2019-02-05 | Netlist, Inc. | Memory module having volatile and non-volatile memory subsystems and method of operation |
US9417754B2 (en) | 2011-08-05 | 2016-08-16 | P4tents1, LLC | User interface system, method, and computer program product |
US11048410B2 (en) | 2011-08-24 | 2021-06-29 | Rambus Inc. | Distributed procedure execution and file systems on a memory interface |
WO2013028854A1 (en) | 2011-08-24 | 2013-02-28 | Rambus Inc. | Methods and systems for mapping a peripheral function onto a legacy memory interface |
US9098209B2 (en) | 2011-08-24 | 2015-08-04 | Rambus Inc. | Communication via a memory interface |
US8700834B2 (en) | 2011-09-06 | 2014-04-15 | Western Digital Technologies, Inc. | Systems and methods for an enhanced controller architecture in data storage systems |
US8713357B1 (en) | 2011-09-06 | 2014-04-29 | Western Digital Technologies, Inc. | Systems and methods for detailed error reporting in data storage systems |
US9195530B1 (en) | 2011-09-06 | 2015-11-24 | Western Digital Technologies, Inc. | Systems and methods for improved data management in data storage systems |
US8707104B1 (en) | 2011-09-06 | 2014-04-22 | Western Digital Technologies, Inc. | Systems and methods for error injection in data storage systems |
WO2013043602A2 (en) | 2011-09-19 | 2013-03-28 | SanDisk Technologies, Inc. | High endurance non-volatile storage |
KR20130032772A (en) * | 2011-09-23 | 2013-04-02 | 삼성전자주식회사 | Hybrid memory device, computer system including the same, and method of reading and writing data in the hybrid memory device |
US9053008B1 (en) | 2012-03-26 | 2015-06-09 | Western Digital Technologies, Inc. | Systems and methods for providing inline parameter service in data storage devices |
US20130318276A1 (en) | 2012-05-22 | 2013-11-28 | Xockets IP, LLC | Offloading of computation for rack level servers and corresponding methods and systems |
US20130318269A1 (en) | 2012-05-22 | 2013-11-28 | Xockets IP, LLC | Processing structured and unstructured data using offload processors |
US9183910B2 (en) | 2012-05-31 | 2015-11-10 | Samsung Electronics Co., Ltd. | Semiconductor memory devices for alternately selecting bit lines |
US9252996B2 (en) | 2012-06-21 | 2016-02-02 | Micron Technology, Inc. | Apparatuses and methods to change information values |
KR20130143210A (en) * | 2012-06-21 | 2013-12-31 | 삼성전자주식회사 | Memory expanding device |
US20140108705A1 (en) | 2012-10-12 | 2014-04-17 | Sandisk Technologies Inc. | Use of High Endurance Non-Volatile Memory for Read Acceleration |
EP2915049B1 (en) | 2012-10-30 | 2020-03-04 | Hewlett-Packard Enterprise Development LP | Smart memory buffers |
CN105103234A (en) * | 2012-11-20 | 2015-11-25 | 查尔斯·I·派德尔 | Solid state drive architectures |
US9147461B1 (en) | 2012-11-28 | 2015-09-29 | Samsung Electronics Co., Ltd. | Semiconductor memory device performing a refresh operation, and memory system including the same |
US9280497B2 (en) * | 2012-12-21 | 2016-03-08 | Dell Products Lp | Systems and methods for support of non-volatile memory on a DDR memory channel |
US9348638B2 (en) | 2013-01-17 | 2016-05-24 | Xockets, Inc. | Offload processor modules for connection to system memory, and corresponding methods and systems |
US9378161B1 (en) | 2013-01-17 | 2016-06-28 | Xockets, Inc. | Full bandwidth packet handling with server systems including offload processors |
CN103970219B (en) * | 2013-01-30 | 2018-03-20 | 鸿富锦精密电子(天津)有限公司 | Storage device and the mainboard for supporting the storage device |
US8812744B1 (en) | 2013-03-14 | 2014-08-19 | Microsoft Corporation | Assigning priorities to data for hybrid drives |
US10372551B2 (en) | 2013-03-15 | 2019-08-06 | Netlist, Inc. | Hybrid memory system with configurable error thresholds and failure analysis capability |
WO2014155593A1 (en) * | 2013-03-27 | 2014-10-02 | 株式会社日立製作所 | Dram with sdram interface, and hybrid flash memory module |
US9552176B2 (en) * | 2013-04-12 | 2017-01-24 | Microsoft Technology Licensing, Llc | Block storage using a hybrid memory device |
US9626126B2 (en) | 2013-04-24 | 2017-04-18 | Microsoft Technology Licensing, Llc | Power saving mode hybrid drive access management |
US9946495B2 (en) | 2013-04-25 | 2018-04-17 | Microsoft Technology Licensing, Llc | Dirty data management for hybrid drives |
US9436600B2 (en) | 2013-06-11 | 2016-09-06 | Svic No. 28 New Technology Business Investment L.L.P. | Non-volatile memory storage for multi-channel memory system |
WO2014203383A1 (en) * | 2013-06-20 | 2014-12-24 | 株式会社日立製作所 | Memory module having different types of memory mounted together thereon, and information processing device having memory module mounted therein |
US9129674B2 (en) * | 2013-06-27 | 2015-09-08 | Intel Corporation | Hybrid memory device |
EP3020047A1 (en) * | 2013-07-09 | 2016-05-18 | Hewlett Packard Enterprise Development LP | Write flow control for memory modules that include or interface with non-compliant memory technologies |
US9921980B2 (en) | 2013-08-12 | 2018-03-20 | Micron Technology, Inc. | Apparatuses and methods for configuring I/Os of memory for hybrid memory modules |
JP6090057B2 (en) * | 2013-08-15 | 2017-03-08 | 富士ゼロックス株式会社 | Status information recording apparatus and program |
US10185515B2 (en) | 2013-09-03 | 2019-01-22 | Qualcomm Incorporated | Unified memory controller for heterogeneous memory on a multi-chip package |
JP6072661B2 (en) * | 2013-09-30 | 2017-02-01 | ルネサスエレクトロニクス株式会社 | Data processing device, microcontroller, and semiconductor device |
KR20160083926A (en) * | 2013-11-07 | 2016-07-12 | 넷리스트 인코포레이티드 | Hybrid memory module and system and method of operating the same |
US11182284B2 (en) | 2013-11-07 | 2021-11-23 | Netlist, Inc. | Memory module having volatile and non-volatile memory subsystems and method of operation |
US10248328B2 (en) | 2013-11-07 | 2019-04-02 | Netlist, Inc. | Direct data move between DRAM and storage on a memory module |
KR102195896B1 (en) * | 2014-01-10 | 2020-12-28 | 삼성전자주식회사 | Device and method of managing disk cache |
US9237670B2 (en) | 2014-02-26 | 2016-01-12 | Samsung Electronics Co., Ltd. | Socket interposer and computer system using the socket |
CN103942159A (en) * | 2014-03-19 | 2014-07-23 | 华中科技大学 | Data read-write method and device based on mixed storage device |
US20150347151A1 (en) * | 2014-05-28 | 2015-12-03 | Diablo Technologies Inc. | System and method for booting from a non-volatile memory |
US10430092B1 (en) * | 2014-07-28 | 2019-10-01 | Rambus Inc. | Memory controller systems with nonvolatile memory for storing operating parameters |
US9715453B2 (en) * | 2014-12-11 | 2017-07-25 | Intel Corporation | Computing method and apparatus with persistent memory |
US10318340B2 (en) * | 2014-12-31 | 2019-06-11 | Ati Technologies Ulc | NVRAM-aware data processing system |
KR102355436B1 (en) * | 2015-01-09 | 2022-01-26 | 에스케이하이닉스 주식회사 | Data storage device |
KR102076196B1 (en) * | 2015-04-14 | 2020-02-12 | 에스케이하이닉스 주식회사 | Memory system, memory module and operation method of the same |
CN107710175B (en) * | 2015-04-20 | 2021-12-14 | 奈特力斯股份有限公司 | Memory module and operating system and method |
US10339081B2 (en) | 2015-05-09 | 2019-07-02 | Medtronic, Inc. | Methods and devices that utilize hardware to move blocks of operating parameter data from memory to a register set |
US10261697B2 (en) | 2015-06-08 | 2019-04-16 | Samsung Electronics Co., Ltd. | Storage device and operating method of storage device |
US9904490B2 (en) * | 2015-06-26 | 2018-02-27 | Toshiba Memory Corporation | Solid-state mass storage device and method for persisting volatile data to non-volatile media |
US10078448B2 (en) | 2015-07-08 | 2018-09-18 | Samsung Electronics Co., Ltd. | Electronic devices and memory management methods thereof |
US20170060434A1 (en) * | 2015-08-27 | 2017-03-02 | Samsung Electronics Co., Ltd. | Transaction-based hybrid memory module |
KR102367512B1 (en) | 2015-09-08 | 2022-02-24 | 삼성전자주식회사 | System on package |
US10031674B2 (en) * | 2015-10-07 | 2018-07-24 | Samsung Electronics Co., Ltd. | DIMM SSD addressing performance techniques |
US10331586B2 (en) | 2015-10-30 | 2019-06-25 | Samsung Electronics Co., Ltd. | Nonvolatile memory device for providing fast booting and system including the same |
US20180225059A1 (en) * | 2015-11-03 | 2018-08-09 | Hewlett-Packard Development Company, L.P. | Operating mode memory migration |
US9971511B2 (en) | 2016-01-06 | 2018-05-15 | Samsung Electronics Co., Ltd. | Hybrid memory module and transaction-based memory interface |
US20170220252A1 (en) * | 2016-01-29 | 2017-08-03 | Faraday&Future Inc. | Flash emulated eeprom wrapper |
US10146704B2 (en) * | 2016-02-16 | 2018-12-04 | Dell Products L.P. | Volatile/non-volatile memory device access provisioning system |
US10163508B2 (en) * | 2016-02-26 | 2018-12-25 | Intel Corporation | Supporting multiple memory types in a memory slot |
US10534619B2 (en) | 2016-02-26 | 2020-01-14 | Smart Modular Technologies, Inc. | Memory management system with multiple boot devices and method of operation thereof |
US10621119B2 (en) | 2016-03-03 | 2020-04-14 | Samsung Electronics Co., Ltd. | Asynchronous communication protocol compatible with synchronous DDR protocol |
US10592114B2 (en) | 2016-03-03 | 2020-03-17 | Samsung Electronics Co., Ltd. | Coordinated in-module RAS features for synchronous DDR compatible memory |
US10310547B2 (en) * | 2016-03-05 | 2019-06-04 | Intel Corporation | Techniques to mirror a command/address or interpret command/address logic at a memory device |
US10810144B2 (en) * | 2016-06-08 | 2020-10-20 | Samsung Electronics Co., Ltd. | System and method for operating a DRR-compatible asynchronous memory module |
US10186309B2 (en) | 2016-06-29 | 2019-01-22 | Samsung Electronics Co., Ltd. | Methods of operating semiconductor memory devices and semiconductor memory devices |
US10692555B2 (en) | 2016-06-29 | 2020-06-23 | Samsung Electronics Co., Ltd. | Semiconductor memory devices enabling read strobe mode and related methods of operating semiconductor memory devices |
KR102554496B1 (en) | 2016-07-14 | 2023-07-13 | 에스케이하이닉스 주식회사 | Data Processing System including a plurality of memory modules |
US10282108B2 (en) * | 2016-08-31 | 2019-05-07 | Micron Technology, Inc. | Hybrid memory device using different types of capacitors |
US9916256B1 (en) | 2016-09-12 | 2018-03-13 | Toshiba Memory Corporation | DDR storage adapter |
KR20180030329A (en) * | 2016-09-13 | 2018-03-22 | 에스케이하이닉스 주식회사 | Memory system and operation method for the same |
US10552053B2 (en) | 2016-09-28 | 2020-02-04 | Seagate Technology Llc | Hybrid data storage device with performance mode data path |
DE102017105155B4 (en) | 2016-11-11 | 2023-09-07 | Sandisk Technologies Llc | INTERFACE FOR A NON-VOLATILE MEMORY |
CN108121664A (en) * | 2016-11-28 | 2018-06-05 | 慧荣科技股份有限公司 | data storage device and operation method thereof |
KR20180078512A (en) | 2016-12-30 | 2018-07-10 | 삼성전자주식회사 | Semiconductor device |
US10977057B2 (en) | 2017-01-23 | 2021-04-13 | Via Labs, Inc. | Electronic apparatus capable of collectively managing different firmware codes and operation method thereof |
US11175853B2 (en) * | 2017-05-09 | 2021-11-16 | Samsung Electronics Co., Ltd. | Systems and methods for write and flush support in hybrid memory |
US10496584B2 (en) * | 2017-05-11 | 2019-12-03 | Samsung Electronics Co., Ltd. | Memory system for supporting internal DQ termination of data buffer |
US10403342B2 (en) * | 2017-06-20 | 2019-09-03 | Aspiring Sky Co. Limited | Hybrid flash memory structure |
US10845866B2 (en) * | 2017-06-22 | 2020-11-24 | Micron Technology, Inc. | Non-volatile memory system or sub-system |
EP3447636B1 (en) * | 2017-08-21 | 2020-09-30 | Carrier Corporation | Fire and security system including addressable loop and automatic firmware upgrade |
KR102412609B1 (en) | 2017-11-03 | 2022-06-23 | 삼성전자주식회사 | A memory device for storing and outputting an address accroding to an internal command and operating method thereof |
KR102101622B1 (en) * | 2017-12-06 | 2020-04-17 | 주식회사 멤레이 | Memory controlling device and computing device including the same |
US11216370B2 (en) * | 2018-02-20 | 2022-01-04 | Medtronic, Inc. | Methods and devices that utilize hardware to move blocks of operating parameter data from memory to a register set |
KR20190105337A (en) | 2018-03-05 | 2019-09-17 | 삼성전자주식회사 | Memory device |
US10534731B2 (en) | 2018-03-19 | 2020-01-14 | Micron Technology, Inc. | Interface for memory having a cache and multiple independent arrays |
US10705963B2 (en) | 2018-03-21 | 2020-07-07 | Micron Technology, Inc. | Latency-based storage in a hybrid memory system |
TWI668575B (en) * | 2018-07-26 | 2019-08-11 | 慧榮科技股份有限公司 | Data storage device and control method for non-volatile memory |
US10977198B2 (en) * | 2018-09-12 | 2021-04-13 | Micron Technology, Inc. | Hybrid memory system interface |
CN111512374B (en) | 2018-10-16 | 2022-11-11 | 华为技术有限公司 | Hybrid storage device and access method |
US11048654B2 (en) * | 2018-10-24 | 2021-06-29 | Innogrit Technologies Co., Ltd. | Systems and methods for providing multiple memory channels with one set of shared address pins on the physical interface |
CN111399750B (en) * | 2019-01-03 | 2023-05-26 | 慧荣科技股份有限公司 | Flash memory data writing method and computer readable storage medium |
US11199991B2 (en) | 2019-01-03 | 2021-12-14 | Silicon Motion, Inc. | Method and apparatus for controlling different types of storage units |
KR20210017109A (en) | 2019-08-07 | 2021-02-17 | 삼성전자주식회사 | Storage device |
RU2757659C1 (en) * | 2020-06-16 | 2021-10-19 | Александр Георгиевич Носков | Magnetic drive with divided areas |
KR20220029914A (en) | 2020-09-02 | 2022-03-10 | 삼성전자주식회사 | A memory device, a memory controller and memory system including them for generating data strobe signal based on pulse amplitude modulation |
US20220083252A1 (en) * | 2020-09-14 | 2022-03-17 | Micron Technology, Inc. | Indication-based avoidance of defective memory cells |
CN112199045A (en) * | 2020-10-12 | 2021-01-08 | 长江存储科技有限责任公司 | Storage device and data operation method |
KR20220077400A (en) | 2020-12-02 | 2022-06-09 | 삼성전자주식회사 | Nonvolatile memory device, memory system and operationg method thereof |
US11803326B2 (en) * | 2021-04-23 | 2023-10-31 | Macronix International Co., Ltd. | Implementing a read setup burst command in 3D NAND flash memory to reduce voltage threshold deviation over time |
KR102483906B1 (en) * | 2021-07-14 | 2022-12-30 | 서울시립대학교 산학협력단 | Nas memory cell combined with nand flash memory and static random access memory and nas memory array using the same |
CN116955241B (en) * | 2023-09-21 | 2024-01-05 | 杭州智灵瞳人工智能有限公司 | Memory chip compatible with multiple types of memory media |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5581505A (en) * | 1989-05-15 | 1996-12-03 | Dallas Semiconductor Corp. | Ram/ROM hybrid memory architecture |
US6418506B1 (en) | 1996-12-31 | 2002-07-09 | Intel Corporation | Integrated circuit memory and method for transferring data using a volatile memory to buffer data for a nonvolatile memory array |
US6496854B1 (en) * | 1996-07-01 | 2002-12-17 | Sun Microsystems, Inc. | Hybrid memory access protocol in a distributed shared memory computer system |
US6804146B2 (en) * | 1995-04-21 | 2004-10-12 | Mark B. Johnson | Hybrid semiconductor—magnetic spin based memory |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05299616A (en) * | 1992-04-16 | 1993-11-12 | Hitachi Ltd | Semiconductor storage device |
JPH06195258A (en) * | 1992-07-08 | 1994-07-15 | Nec Corp | Semiconductor memory |
US5696917A (en) | 1994-06-03 | 1997-12-09 | Intel Corporation | Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory |
US5634112A (en) * | 1994-10-14 | 1997-05-27 | Compaq Computer Corporation | Memory controller having precharge prediction based on processor and PCI bus cycles |
US5701433A (en) * | 1994-10-14 | 1997-12-23 | Compaq Computer Corporation | Computer system having a memory controller which performs readahead operations which can be aborted prior to completion |
US6850995B1 (en) * | 1999-01-25 | 2005-02-01 | Canon Kabushiki Kaisha | Control unit selectively connected with a first bus and a second bus for controlling a displaying process in parallel with a scanning process |
US6380581B1 (en) | 1999-02-26 | 2002-04-30 | Micron Technology, Inc. | DRAM technology compatible non volatile memory cells with capacitors connected to the gates of the transistors |
KR100313514B1 (en) * | 1999-05-11 | 2001-11-17 | 김영환 | Hybrid memory device |
KR100383774B1 (en) | 2000-01-26 | 2003-05-12 | 삼성전자주식회사 | Memory strcutre for improving bus efficiency of system adopting common interface |
US7073014B1 (en) | 2000-07-28 | 2006-07-04 | Micron Technology, Inc. | Synchronous non-volatile memory system |
JP3871853B2 (en) | 2000-05-26 | 2007-01-24 | 株式会社ルネサステクノロジ | Semiconductor device and operation method thereof |
JP2002259443A (en) * | 2001-02-28 | 2002-09-13 | Ricoh Co Ltd | Document control system, document search method and document search program |
US6327207B1 (en) * | 2001-04-09 | 2001-12-04 | Lsi Logic Corporation | Synchronizing data operations across a synchronization boundary between different clock domains using two-hot encoding |
TWI240864B (en) | 2001-06-13 | 2005-10-01 | Hitachi Ltd | Memory device |
JP4059002B2 (en) * | 2001-06-13 | 2008-03-12 | 株式会社日立製作所 | Memory device |
JP2003006041A (en) | 2001-06-20 | 2003-01-10 | Hitachi Ltd | Semiconductor device |
US6670234B2 (en) | 2001-06-22 | 2003-12-30 | International Business Machines Corporation | Method of integrating volatile and non-volatile memory cells on the same substrate and a semiconductor memory device thereof |
US7533214B2 (en) * | 2002-02-27 | 2009-05-12 | Microsoft Corporation | Open architecture flash driver |
US6799231B2 (en) * | 2002-10-22 | 2004-09-28 | Asix Electronics Corp. | Virtual I/O device coupled to memory controller |
US7613880B2 (en) | 2002-11-28 | 2009-11-03 | Renesas Technology Corp. | Memory module, memory system, and information device |
US7752380B2 (en) | 2003-07-31 | 2010-07-06 | Sandisk Il Ltd | SDRAM memory device with an embedded NAND flash controller |
US6859068B1 (en) * | 2003-08-08 | 2005-02-22 | Sun Microsystems, Inc. | Self-correcting I/O interface driver scheme for memory interface |
US7171526B2 (en) | 2003-11-07 | 2007-01-30 | Freescale Semiconductor, Inc. | Memory controller useable in a data processing system |
US6862206B1 (en) * | 2003-12-19 | 2005-03-01 | Hewlett-Packard Development Company, L.P. | Memory module hybridizing an atomic resolution storage (ARS) memory and a magnetic memory |
KR101085406B1 (en) | 2004-02-16 | 2011-11-21 | 삼성전자주식회사 | Controller for controlling nonvolatile memory |
US20050204091A1 (en) | 2004-03-11 | 2005-09-15 | Kilbuck Kevin M. | Non-volatile memory with synchronous DRAM interface |
US20060184710A1 (en) * | 2005-02-17 | 2006-08-17 | Nokia Inc. | Bridge between a single channel high speed bus and a multiple channel low speed bus |
US20060294295A1 (en) * | 2005-06-24 | 2006-12-28 | Yukio Fukuzo | DRAM chip device well-communicated with flash memory chip and multi-chip package comprising such a device |
US7360022B2 (en) * | 2005-12-29 | 2008-04-15 | Intel Corporation | Synchronizing an instruction cache and a data cache on demand |
US8427891B2 (en) * | 2007-04-17 | 2013-04-23 | Rambus Inc. | Hybrid volatile and non-volatile memory device with a shared interface circuit |
-
2006
- 2006-06-07 US US11/449,435 patent/US7716411B2/en active Active
-
2007
- 2007-04-13 TW TW096113112A patent/TWI420302B/en not_active IP Right Cessation
- 2007-06-01 JP JP2009514323A patent/JP2009540431A/en active Pending
- 2007-06-01 WO PCT/US2007/013127 patent/WO2007145883A1/en active Application Filing
- 2007-06-01 KR KR1020087029847A patent/KR101159400B1/en active IP Right Grant
- 2007-06-01 EP EP07795704.1A patent/EP2025001B1/en active Active
- 2007-06-01 BR BRPI0711731-0A patent/BRPI0711731A2/en not_active Application Discontinuation
- 2007-06-01 ES ES07795704T patent/ES2718463T3/en active Active
- 2007-06-01 CN CN2007800212183A patent/CN101473438B/en active Active
- 2007-06-01 MX MX2008014859A patent/MX2008014859A/en active IP Right Grant
- 2007-06-01 RU RU2008148129/08A patent/RU2442211C2/en active
-
2010
- 2010-04-30 US US12/771,670 patent/US8423700B2/en active Active
-
2011
- 2011-05-18 JP JP2011111408A patent/JP5613103B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5581505A (en) * | 1989-05-15 | 1996-12-03 | Dallas Semiconductor Corp. | Ram/ROM hybrid memory architecture |
US6804146B2 (en) * | 1995-04-21 | 2004-10-12 | Mark B. Johnson | Hybrid semiconductor—magnetic spin based memory |
US6496854B1 (en) * | 1996-07-01 | 2002-12-17 | Sun Microsystems, Inc. | Hybrid memory access protocol in a distributed shared memory computer system |
US6418506B1 (en) | 1996-12-31 | 2002-07-09 | Intel Corporation | Integrated circuit memory and method for transferring data using a volatile memory to buffer data for a nonvolatile memory array |
Non-Patent Citations (1)
Title |
---|
See also references of EP2025001A4 |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100987332B1 (en) | 2008-11-07 | 2010-10-18 | 서울대학교산학협력단 | Memory management device according to memory hierarchy |
CN102326154A (en) * | 2008-12-23 | 2012-01-18 | 苹果公司 | Architecture for address mapping of managed non-volatile memory |
US8862851B2 (en) | 2008-12-23 | 2014-10-14 | Apple Inc. | Architecture for address mapping of managed non-volatile memory |
US8611123B2 (en) | 2010-09-15 | 2013-12-17 | Samsung Electronics Co., Ltd. | Complex semiconductor device for use in mobile equipment |
JP2014078231A (en) * | 2012-10-08 | 2014-05-01 | Hgst Netherlands B V | Device and method for low power, low delay and large capacity storage class memory |
US10664171B2 (en) | 2013-03-14 | 2020-05-26 | Micron Technology, Inc. | Memory systems and methods including training, data organizing, and/or shadowing |
WO2014139047A1 (en) * | 2013-03-14 | 2014-09-18 | Micron Technology, Inc. | Memory systems and methods including training,data organizing,and/or shadowing |
US9645919B2 (en) | 2013-03-14 | 2017-05-09 | Micron Technology, Inc. | Memory systems and methods including training, data organizing, and/or shadowing |
US11487433B2 (en) | 2013-03-14 | 2022-11-01 | Micron Technology, Inc. | Memory systems and methods including training, data organizing, and/or shadowing |
US9658783B2 (en) | 2013-03-27 | 2017-05-23 | Hitachi, Ltd. | DRAM having SDRAM interface and flash memory consolidated memory module |
US9342402B1 (en) | 2014-01-28 | 2016-05-17 | Altera Corporation | Memory interface with hybrid error detection circuitry for modular designs |
US9911477B1 (en) | 2014-04-18 | 2018-03-06 | Altera Corporation | Memory controller architecture with improved memory scheduling efficiency |
US10268392B2 (en) | 2014-06-30 | 2019-04-23 | Altera Corporation | Memory controller architecture with improved memory scheduling efficiency |
US9811263B1 (en) | 2014-06-30 | 2017-11-07 | Altera Corporation | Memory controller architecture with improved memory scheduling efficiency |
JP2017102943A (en) * | 2017-01-10 | 2017-06-08 | マイクロン テクノロジー, インク. | Memory system including training, data reconstruction, and/or shadowing, and method |
Also Published As
Publication number | Publication date |
---|---|
EP2025001B1 (en) | 2019-01-23 |
RU2442211C2 (en) | 2012-02-10 |
EP2025001A4 (en) | 2010-07-28 |
TW200745848A (en) | 2007-12-16 |
TWI420302B (en) | 2013-12-21 |
RU2008148129A (en) | 2010-06-10 |
US20100217924A1 (en) | 2010-08-26 |
CN101473438A (en) | 2009-07-01 |
EP2025001A1 (en) | 2009-02-18 |
US7716411B2 (en) | 2010-05-11 |
US8423700B2 (en) | 2013-04-16 |
US20070288683A1 (en) | 2007-12-13 |
JP2011181098A (en) | 2011-09-15 |
BRPI0711731A2 (en) | 2011-11-29 |
JP5613103B2 (en) | 2014-10-22 |
CN101473438B (en) | 2012-06-13 |
ES2718463T3 (en) | 2019-07-02 |
KR101159400B1 (en) | 2012-06-28 |
JP2009540431A (en) | 2009-11-19 |
KR20090026276A (en) | 2009-03-12 |
MX2008014859A (en) | 2008-12-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP2025001B1 (en) | Hybrid memory device with single interface | |
KR100281432B1 (en) | Main memory based on flash memory | |
US9645746B2 (en) | Systems and methods for support of non-volatile memory on a DDR memory channel | |
US8151036B2 (en) | Memory controller, memory system, and access control method of flash memory | |
US9772803B2 (en) | Semiconductor memory device and memory system | |
EP3441885B1 (en) | Technologies for caching persistent two-level memory data | |
US10559335B2 (en) | Method of training drive strength, ODT of memory device, computing system performing the same and system-on-chip performing the same | |
US20080010419A1 (en) | System and Method for Issuing Commands | |
KR20200114212A (en) | Data storage device and operating method thereof | |
WO2007116486A1 (en) | Memory apparatus, control method thereof, control program thereof, memory card, circuit board and electronic device | |
US20230273668A1 (en) | Semiconductor memory device, electronic device and method for setting the same | |
US8745363B2 (en) | Bootable volatile memory device, memory module and processing system comprising bootable volatile memory device, and method of booting processing system using bootable volatile memory device | |
US12056390B2 (en) | Memory controller, storage device, and host device | |
WO2007116483A1 (en) | Memory apparatus, its control method, its control program, memory card, circuit board, and electronic device | |
US20230103797A1 (en) | Memory controller and method of operating the same | |
JPH1185617A (en) | Computer system | |
TW202403556A (en) | Memory system and operating method thereof | |
KR20230038971A (en) | Storage device and operating method thereof | |
US7805567B2 (en) | Chipset and northbridge with raid access |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200780021218.3 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 07795704 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2007795704 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 6301/CHENP/2008 Country of ref document: IN |
|
WWE | Wipo information: entry into national phase |
Ref document number: MX/a/2008/014859 Country of ref document: MX |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2008148129 Country of ref document: RU Ref document number: 1020087029847 Country of ref document: KR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2009514323 Country of ref document: JP |
|
ENP | Entry into the national phase |
Ref document number: PI0711731 Country of ref document: BR Kind code of ref document: A2 Effective date: 20081126 |