WO2007145864B1 - Apparatus and method that provides active pull-up and logic translation from one signal mode to another signal mode - Google Patents
Apparatus and method that provides active pull-up and logic translation from one signal mode to another signal modeInfo
- Publication number
- WO2007145864B1 WO2007145864B1 PCT/US2007/013034 US2007013034W WO2007145864B1 WO 2007145864 B1 WO2007145864 B1 WO 2007145864B1 US 2007013034 W US2007013034 W US 2007013034W WO 2007145864 B1 WO2007145864 B1 WO 2007145864B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal
- mode
- output
- node
- input
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
Abstract
Described is an integrated circuit that causes an input signal having one signal mode with a high state, a low state and a transition state to be dynamically level shifted to another signal mode with a respective high and low state, while minimizing a duration of the transition state of the output signal, wherein the one signal mode and the another signal mode have respectively different high and low state levels.
Claims
received by the International Bureau on 14 April 2008 (14.04.2008)
1. A circuit connected between a supply voltage and ground that operates upon an input signal to generate an output signal comprising: an input node; an output node; a signal path disposed between the input node and the output node, whereby the input node; the output node and the signal path are part of a common bus; a pass transistor disposed within the signal path; an impedance control circuit coupled to the input node and which controls the pass transistor, a comparator that compares a voltage on the output node to a reference voltage, and produces a comparator output signal on a comparator output line; a pull-down transistor coupled between the input node and the ground, and being controlled by the comparator output signal on the comparator output line; a switch coupled to the supply voltage, and controlled by the comparator signal; and wherein: the pass transistor, and the impedance control circuit together operate to cause the input signal having one signal mode with a high and a low state on the input node to be level shifted to the output signal having another signal mode with a respective high and low state on the output node; and the comparator, tie pull-down transistor and the switch together operate to cause dynamic pull-up and pull-down of the level shifted output signal.
2. The circuit according to claim 1 wherein the input node, the output node, the signal path, me.pass transistor, the comparator the pull-down transistor and the switch are formed on a single integrated circuit.
3 The circuit according to claim 2 wherein the one signal mode is a CMOS mode and the another signal mode is an I2C mode.
4, The circuit according to claim 3 wherein the input signal is a 10OkHz signal.
5. A circuit connected between a supply voltage and ground comprising: an input node; an output node; and
means for causing an input signal having one signal mode with a high state, a low state and a transition state to be dynamically level shifted to another signal mode with a respective high and low state, while minimizing a duration of the transition state of the output signal, wherein the one signal mode and the another signal mode have respectively different high and low state levels.
C6. The circuit according to claim 5 wherein the input node, the output node, and the means for causing are formed on a single integrated circuit. n57. The circuit according to claim 6 wherein the one signal mode is a CMOS mode and the another signal mode is an I2C mode.
8. The circuit according to claim 7 wherein the input signal is a 10OkHz signal.
9. A method of operating upon an input signal that is transmitted along a single bus to result in. an output signal comprising the steps of: v . translating the input signal from one signal mode with a high state, a low state and a transition state to an output signal having another signal mode with a respective high and low state; and minimizing a duration of the transition state of the output signal, wherein the one signal mode and the another signal mode have respectively different high and low state levels.
10. A method according to claim 9 wherein the minimizing step includes controlling a pull- up circuit and a pull-down circuit.
11. A method according to claim 9 wherein the minimizing step include controlling the rise time of the output signal.
12%' A method according to claim 10 wherein the rise time of the output signal is controlled using an active pull-up circuit.
'ran.
13.'% " A method according to claim 9 or claim 11 wherein the minimizing step include controling the fall time of the output signal.
]#tu] The method according to claim 13 wherein the fall time is controlled by a field effect transistor.
10
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP07795654.8A EP2039006A4 (en) | 2006-06-15 | 2007-05-31 | Apparatus and method that provides active pull-up and logic translation from one signal mode to another signal mode |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/424,533 US7446565B2 (en) | 2006-06-15 | 2006-06-15 | Apparatus and method that provides active pull-up and logic translation from one signal mode to another signal mode |
| US11/424,533 | 2006-06-15 | ||
| US11/424,535 US7321241B1 (en) | 2006-06-15 | 2006-06-15 | Bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control |
| US11/424,535 | 2006-06-15 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| WO2007145864A2 WO2007145864A2 (en) | 2007-12-21 |
| WO2007145864A3 WO2007145864A3 (en) | 2008-04-17 |
| WO2007145864B1 true WO2007145864B1 (en) | 2008-06-19 |
Family
ID=38832301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2007/013034 WO2007145864A2 (en) | 2006-06-15 | 2007-05-31 | Apparatus and method that provides active pull-up and logic translation from one signal mode to another signal mode |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP2039006A4 (en) |
| TW (1) | TWI346457B (en) |
| WO (1) | WO2007145864A2 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6597197B1 (en) * | 1999-08-27 | 2003-07-22 | Intel Corporation | I2C repeater with voltage translation |
| US6781415B2 (en) * | 2001-11-27 | 2004-08-24 | Fairchild Semiconductor Corporation | Active voltage level bus switch (or pass gate) translator |
| JP3746273B2 (en) * | 2003-02-12 | 2006-02-15 | 株式会社東芝 | Signal level conversion circuit |
| US7098693B2 (en) * | 2004-08-31 | 2006-08-29 | International Business Machines Corporation | Bi-directional voltage translator |
-
2007
- 2007-05-31 WO PCT/US2007/013034 patent/WO2007145864A2/en active Application Filing
- 2007-05-31 EP EP07795654.8A patent/EP2039006A4/en not_active Withdrawn
- 2007-06-05 TW TW096120134A patent/TWI346457B/en active
Also Published As
| Publication number | Publication date |
|---|---|
| TW200830715A (en) | 2008-07-16 |
| EP2039006A2 (en) | 2009-03-25 |
| EP2039006A4 (en) | 2013-10-09 |
| WO2007145864A2 (en) | 2007-12-21 |
| TWI346457B (en) | 2011-08-01 |
| WO2007145864A3 (en) | 2008-04-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8934642B2 (en) | No pop switch | |
| US9124264B2 (en) | Load driver | |
| KR101638531B1 (en) | Apparatus and methods for self-biasing differential signaling circuitry having multimode output configurations for low voltage applications | |
| US6586974B1 (en) | Method for reducing short circuit current during power up and power down for high voltage pad drivers with analog slew rate control | |
| US9806716B2 (en) | Output signal generation circuitry for converting an input signal from a source voltage domain into an output signal for a destination voltage domain | |
| US5905389A (en) | Methods, circuits and devices for improving crossover performance and/or monotonicity, and applications of the same in a universal serial bus (USB) low speed output driver | |
| MXPA06011865A (en) | Break before make predriver and level-shifter. | |
| WO2017007559A1 (en) | Input/output (i/o) driver | |
| US20090289668A1 (en) | Output driver circuit for an integrated circuit | |
| US20030141894A1 (en) | Switched capacitor piecewise linear slew rate control methods for output devices | |
| US6265896B1 (en) | Level transfer circuit for LVCMOS applications | |
| CN101123427A (en) | Grid drive circuit | |
| JP4097149B2 (en) | Differential drive circuit and electronic device incorporating the same | |
| US8089259B2 (en) | Integrated circuit and a method for recovering from a low-power period | |
| US10777257B1 (en) | Output buffer circuit with non-target ODT function | |
| EP1454414B1 (en) | High-speed output circuit with low voltage capability | |
| US9264043B2 (en) | Low power level shifter with output swing control | |
| US7471113B1 (en) | Low crowbar current slew rate controlled driver | |
| WO2007145864B1 (en) | Apparatus and method that provides active pull-up and logic translation from one signal mode to another signal mode | |
| US7547995B1 (en) | Dynamic over-voltage protection scheme for interface circuitry | |
| JP6452981B2 (en) | Transmission drive circuit and semiconductor integrated circuit device | |
| KR101362248B1 (en) | High speed and low power level shifter | |
| KR101067330B1 (en) | Apparatus for high-speed rf signal switching | |
| US9041438B2 (en) | Output buffer and signal processing method | |
| US20080042723A1 (en) | Junction field effect transistor input buffer level shifting circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 07795654 Country of ref document: EP Kind code of ref document: A2 |
|
| NENP | Non-entry into the national phase in: |
Ref country code: DE |
|
| WWE | Wipo information: entry into national phase |
Ref document number: 2007795654 Country of ref document: EP |
|
| NENP | Non-entry into the national phase in: |
Ref country code: RU |