WO2007143220A3 - Reconfigurable scan array structure - Google Patents

Reconfigurable scan array structure Download PDF

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Publication number
WO2007143220A3
WO2007143220A3 PCT/US2007/013428 US2007013428W WO2007143220A3 WO 2007143220 A3 WO2007143220 A3 WO 2007143220A3 US 2007013428 W US2007013428 W US 2007013428W WO 2007143220 A3 WO2007143220 A3 WO 2007143220A3
Authority
WO
WIPO (PCT)
Prior art keywords
scan
array structure
programmable
cell segments
configurations
Prior art date
Application number
PCT/US2007/013428
Other languages
French (fr)
Other versions
WO2007143220A2 (en
Inventor
Xinghao Chen
Original Assignee
Xinghao Chen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xinghao Chen filed Critical Xinghao Chen
Publication of WO2007143220A2 publication Critical patent/WO2007143220A2/en
Publication of WO2007143220A3 publication Critical patent/WO2007143220A3/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G01R31/318538—Topological or mechanical aspects

Abstract

A reconfigurable scan array structure (60) for providing greater flexibility in customizing scan configurations for post-manufacturing applications. The structure (60) includes multiple scan cell segments (62), programmable scan-mode control switches (66), and programmable scan configuration switches (72). The multiple scan cell segments (62) are arranged in an array (64). The programmable scan-mode control switches (66) are placed between same scan cells (68) on two neighboring scan cell segments (70) and enable fine-tuning custom scan configurations to maximize effectiveness and efficiency for individual applications and designs. The programmable scan configuration switches (72) are placed between two scan cell segments (62) on a same row (74) as well as the left and right sides (76,78) of the scan array structure (60) and provide access points into the array structure (60) by SIs, SOs, or MISRs, and other manufacturing-critical components as well as enabling many scan configurations.
PCT/US2007/013428 2006-06-08 2007-06-07 Reconfigurable scan array structure WO2007143220A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US81206406P 2006-06-08 2006-06-08
US60/812,064 2006-06-08

Publications (2)

Publication Number Publication Date
WO2007143220A2 WO2007143220A2 (en) 2007-12-13
WO2007143220A3 true WO2007143220A3 (en) 2008-10-23

Family

ID=38802140

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/013428 WO2007143220A2 (en) 2006-06-08 2007-06-07 Reconfigurable scan array structure

Country Status (1)

Country Link
WO (1) WO2007143220A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107464207A (en) * 2017-07-17 2017-12-12 南京华磊易晶微电子有限公司 3D graphics based on reconfigurable data streaming system chip array renders acceleration system

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103440359B (en) * 2013-07-18 2016-03-02 北京空间飞行器总体设计部 A kind of FPGA parallel computation circuit automatic generation method realizing iterative algorithm
US11105853B1 (en) 2020-02-28 2021-08-31 International Business Machines Corporation Empirical LBIST latch switching and state probability determination

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5909453A (en) * 1997-07-02 1999-06-01 Xilinx, Inc. Lookahead structure for fast scan testing
US7137053B2 (en) * 2001-09-04 2006-11-14 Verigg Ipco Bandwidth matching for scan architectures in an integrated circuit
US7139950B2 (en) * 2004-01-28 2006-11-21 International Business Machines Corporation Segmented scan chains with dynamic reconfigurations

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5909453A (en) * 1997-07-02 1999-06-01 Xilinx, Inc. Lookahead structure for fast scan testing
US7137053B2 (en) * 2001-09-04 2006-11-14 Verigg Ipco Bandwidth matching for scan architectures in an integrated circuit
US7139950B2 (en) * 2004-01-28 2006-11-21 International Business Machines Corporation Segmented scan chains with dynamic reconfigurations

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107464207A (en) * 2017-07-17 2017-12-12 南京华磊易晶微电子有限公司 3D graphics based on reconfigurable data streaming system chip array renders acceleration system
CN107464207B (en) * 2017-07-17 2020-06-02 南京华磊易晶微电子有限公司 3D (three-dimensional) graphics rendering acceleration system based on reconfigurable data stream system chip array

Also Published As

Publication number Publication date
WO2007143220A2 (en) 2007-12-13

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