WO2007143220A2

WO2007143220A2 - Reconfigurable scan array structure

Info

Publication number: WO2007143220A2
Application number: PCT/US2007/013428
Authority: WO
Inventors: Xinghao Chen
Original assignee: Xinghao Chen
Priority date: 2006-06-08
Filing date: 2007-06-07
Publication date: 2007-12-13
Also published as: WO2007143220A3

Abstract

A reconfigurable scan array structure (60) for providing greater flexibility in customizing scan configurations for post-manufacturing applications. The structure (60) includes multiple scan cell segments (62), programmable scan-mode control switches (66), and programmable scan configuration switches (72). The multiple scan cell segments (62) are arranged in an array (64). The programmable scan-mode control switches (66) are placed between same scan cells (68) on two neighboring scan cell segments (70) and enable fine-tuning custom scan configurations to maximize effectiveness and efficiency for individual applications and designs. The programmable scan configuration switches (72) are placed between two scan cell segments (62) on a same row (74) as well as the left and right sides (76,78) of the scan array structure (60) and provide access points into the array structure (60) by SIs, SOs, or MISRs, and other manufacturing-critical components as well as enabling many scan configurations.

Description

RECONFIGURABLE SCAN ARRAY STRUCTURE

Background of the Invention

Field of the Invention:

The present invention relates to a scan structure, and more particularly, the present invention relates to a reconfigurable scan array structure.

Description of the Prior Art:

Various scan design methodologies¹ have been successfully used in LSI and VLSI products in the last four decades. Built-in scan structures provide access points for controllability and observability enhancements. Built-in scan structures are also essential to many test and test data compression techniques, such as STUMPS,² the Illinois Scan

¹ E. B. Eichelberger and T.W. Williams, "A Logic Design Structure for LSI Testing, " in the Proceedings of the 14^th Design Automation Conference, pp. 462-468, June, 1977; E.B. Eichelberger and T.W. Williams, "A Logic Design Structure for LSI Testability, " Journal of Design Automation & Fault-Tolerance Computing, Vol. 2, No. 2, pp. 165-178, May, 1978; E.B. Eichelberger, T.W. Williams, E.I. Muchldorf, and R.G. Walther, "A Logic Design Structure for Testing Interna/ Array, " in the Proceedings of the 3^rd USA-JAPAN Computer Conference, pp. 266-272, October, 1978; A. Kobayashi, S. Matsue, and H. Shiba, "Flipflop Circuit with FLT (Fault-Location-Technique) Capability, " (in Japanese) in the Proceedings of the IECEO Conference, pp. 962, 1968; Y. Miyagi, A. Kobayashi, and K. Kitano, "Hardware System of NEAC Series 2200 Model 700, " (in Japanese) Paper Technology Group, IECE, Japan, TGOEC71 -3, April 1971.

² PH. Bardell and W.H. McAnney, "Self-Testing of Multiple Logic Modules, " in the Digest of Papers of the International Test Conference, pp. 200-204, November 1982; P.H. Bardell and W.H. McAnney, "Parallel Pseudorandom Sequences for Built-in Test. " in the Proceedings of the International Test Conference, pp. 302-308. October 1984; P.H. Bardell and W.H. McAnney, "Simultaneous Self-Testing Svslem, " U.S. Patent No. 4,513,4 18, April 23, 1985. Architecture,³ and SmartBIST.⁴ Studies with dynamic scan chain⁵ indicate that reconfigurable scan structures can effectively reduce the cost of a test.

Scan designs have been successfully used in microprocessor and other complex digital integrated circuit designs, and have been credited with improved testability, reduced cost of test and diagnosis, reduced time for process and system debugging, better system maintenance and serviceability, etc., among many manufacturing-critical metrics monitoring IC and digital system engineering objectives.⁶ Scan structures used by individual designs are typically customized on the silicon. These scan structures cannot be changed for many post-manufacturing processes, such as test, often resulting in poor process efficiency. Some specific scan methods were proposed.⁷

³ I. Hamzaoglu and J. H. Patel, "Reducing Test Application Time for Full Scan Embedded Cores, " in the Proceedings of the IEEE International Symposium on Fault Tolerant Computing, 1999, pp. 260-267; I. Hamzaoglu and J. H. Patel, "Reducing Test Application Time for Built-in Self-Test Test Pattern Generators, " in the Proceedings of the IEEE VLSI Test Symposium, pp. 369-375, 2000.

⁴ B. Koenemann et al. , "Logic DFT and Test Resource Partitioning for I OOM Gate ASICs, " presentation at the Test Resource Partitioning Workshop (TRP), 2000; B. Koenemann, C. Barnhart, B. Keller, T. Snethen, O. Farnsworth, and D. Wheater, "A SmartBIST Variant with Guaranteed Encoding, " in the Proceedings of the 10^th Asian Test Symposium, pp. 325-332, 2001.

⁵ S. Narayanan and M. Breuer, "Optimal Configuring of Multiple Scan Chains, " IEEE Transactions on Computers, Vol. 42, No. 9, pp. 1 121 -1 13 I , September 1993; S. Narayanan and M. Breuer, "Reconfiguration Techniques for a Single Scan Chain, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, No. 6, pp. 750-765, 1995; A.R. Pandey and

J. H. Patel, "Reconfiguration Techniques for Reducing Test Time and Test Data Volume in Illinois Scan Structure Based Designs, " in the Proceedings of the I EEE VLSI Test Symposium, pp. 9- 15, 2002; S. Samaranayake, N. Sitchinava, R. Kapur, M. B. Amin, and T. W. Williams, "Dynamic Scan: Driving Down the Cost of Test, " IEEE Computer, pp. 63-68, October 2002; S. Samaranayake, E. Gizdarski, N. Sitchinava, F. Neuveux, R. Kapur, M. B. Amin, and T. W. Williams, "A Reconfigurable Shared Scan-in Architecture, " in the Proceedings of the IEEE VLSI Test Symposium, pp. 9rl4,.2003.

⁶ S. DasGupta, R G. Walther, and T. W. Williams, "An Enhancement to LSSD and Some Applications of LSSD in Reliability, Availability, and Serviceability, " in the Digest of Papers of the 1 1 "¹ Annual International Symposium on Fault-Tolerant Computing, pp. 32-34, June 1981 ; W. C. Carter, H. C. Montgomery, R.J. Presis, and H.J. Reinheimer, " Design of Serviceability Features for the IBM System/360, " IBM Journal of Research & Development, pp. 1 15-126, 1964; K. Maling and E. L. Allen, "A Computer Organization and Programming System for Automated Maintenance, " IEEET-EC: 63, pp. 887-895; J. H. Stewart, "Application of Scan/Set for Error Detection and Diagnostics, " in the Digest of Papers of the Semiconductor Test Conference, pp. 152- 158, 1978.

⁷ M.S. Abadir and M. A. Breuer, "Scan Path with Look Ahead Shifting, " in the Proceedings of the International Test Conference, pp. 165-170, June, 1985; M.S. Abadir, "Efficient Scan Path Testing Using Sliding Parity Response Compaction, " in the Proceedings of the International Conference on Computer Aided Design, pp. 332-335, November, 1987; K. T. Cheng and V.D. Agrawal, "An Economical Scan Design for Sequential Logic Test Generation, " in the Proceedings of the 19^th International Symposium on Fault-Tolerant Computing, pp. 28-35, June 1989; S. DasGupta, P. Goel, R.G. Walther, and T.W. Williams, "A Variation of LSSD and Its Implications on Design and Test Pattern Generation in VLSI, " in the Proceedings of the International Test Conference, pp. 63-66, November 1982; S P. Morley and R.A. Malett, "Selectable Length Partial Scan: A Method to Reduce Vector Length, " in the Proceedings of the International Test Conference, pp. 385-392, 1991. To overcome the inflexibility of existing scan structures, dynamic scan⁸ was proposed for generating efficient tests. With dynamic scan, a MUX is placed at the output of a scan cell. When selected, the MUX can by-pass a scan cell. To reduce the use of the MIUX blocks, a MUX may be used to by-pass a segment of the scan chain. Dynamic scan can also be applied to parallel scan chains.

S. Narayanan and M. Breuer, "Reconfiguration Techniques for a Single Scan Chain, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, No. 6, pp. 750-765, 1995; A R. Pandey and J. H. Patel, " Reconfiguration Techniques for Reducing Test Time and Test Data Volume in Illinois Scan Structure Based Designs, " in the Proceedings of the IEEE VLSI Test Symposium, pp. 9-15, 2002; S. Samaranayake, N. Sitchinava, R. Kapur, M. B. Amin, and T. W. Williams, "Dynamic Scan: Driving Down the Cost of Test, " IEEE Computer, pp. 63-68, October 2002; S. Samaranayake, E. Gizdarski, N. Sitchinava, F. Neuveux, R. Kapur, M. B. Amin, and T. W. Williams, "A Reconfigurable Shared Scan-in Architecture, " in the Proceedings of the IEEE VLSI Test Symposium, pp. 9- 14, 2003. Summary of the Invention

Thus, an object of the present invention is to provide a reconfigurable scan array structure that avoids the disadvantages of the prior art.

Briefly stated, another object of the present invention is to provide a reconfigurable scan array structure for providing greater flexibility in customizing scan configurations for post-manufacturing applications. The structure includes multiple scan cell segments, programmable scan-mode control, switches, and programmable scan configuration switches. The multiple scan cell segments are arranged in an array. The programmable scan-mode control switches are placed between same scan cells on two neighboring scan cell segments and enable fine-tuning custom scan configurations to maximize effectiveness and efficiency for individual applications and designs. The programmable scan configuration switches are placed between two scan cell segments on a same row as well as the left and right sides of the scan array structure and provide access points into the array structure by SIs, SOs, or MlSRs, and other manufacturing- critical components as well as enabling many scan configurations.

The novel features which are considered characteristic of the present invention are set forth in the appended claims. The invention itself, however, both as to its construction and its method of operation and together with additional objects and advantages thereof will be best^' understood from the following description of the specific embodiments when read and understood in connection with the accompanying drawing.

Brief Description of the Drawing

The figures of the drawing are briefly described as follows: FIGURE IA is a block diagram of a reconfigurable scan chain architecture; FIGURE IB is a schematic diagram of an inverter-based D-latch with pass-through; FIGURE 2 is a block diagram of reconfigurable parallel scan chains; FIGURE 3 is a block diagram of reconfigurable parallel scan chains; FIGURE 4A is a block diagram of a fixed-length multi-row scan chain; FIGURE 4B is a block diagram of a reconfigurable scan structure; FIGURE 4C are block diagrams of programmable scan configuration switches; FIGURE 5A is a block diagram of a reconfigurable multi-row single scan chain structure wherein S₃ and S₄ are programable scan configuration switches; FIGURE 5B is a block diagram of a reconfigured multi-row scan chain; and FIGURE 6 is a block diagram of reconfigurable scan array structures.

List of Reference Numerals Utilized in the Drawing

Reconfigurable Scan Chain

10 dynamically-reconfϊgurable scan chain

12 scan cell 14 input of scan cell 12

16 output of scan cell 12

18 scan clock(s)

20 scan configuration controller

22 configuration input 24 2-input OR gate

26 control input of 2-input OR gate

28 inverter-based D-latch

30 scan configuration control access network

32 parallel scan chains 34 configuration control lines

36 reconfigurable scan unit

38 programmable scan-mode switches

Reconfigurable Scan Array Structure

40 multiple shorter scan chains 42 multi-row single scan chain

44 reconfigurable long single multi-row scan chain

46 programmable scan configuration switches

48 both ends of scan rows 50

50 scan rows 52 terminals

54 very long multi-row scan chain

56 small segments of very long multi-row scan chain

58 programmed connections

60 reconfigurable scan array structure 62 multiple scan cell segments

64 array of multiple scan cell segments 62

66 programmable scan-mode control switches

68 same scan cells on two neighboring scan segments 70

70 two neighboring scan segments 72 programmable scan configuration switches 74 same row

76 left side of scan array structure 60

78 right side of scan array structure 60

Detailed Description of the Preferred Embodiments

General

A reconfigurable scan array structure provides the flexibility to customize scan configurations with designs to be implemented on pre-manufactured silicon platforms, such as field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). It can also be applied to pre-structured design and implementation platforms, with which manufacturing-critical circuit components and structures are prefixed and are not to be changed by individual designs.

With pre-manufactured platforms, such as FPGAs, built-in reconfigurable scan array structures provide flexible scan configuration solutions to a wide range of different designs that may require post-manufacturing customizable scan configurations. With pre- structured platforms, manufacturing-critical circuit components and structures are defined for a wide range of applications and are not to be altered by application design processes. With these platforms, scan structures are defined not for specific designs, but rather as built-in scan platforms upon which customized scan configurations can be achieved during post-manufacturing processes and applications.

Reconfigurable Scan Chain

FIGURE IA, which is a block diagram of a reconfigurable scan chain architecture, illustrates the structure of a dynamically-reconfigurable scan chain 10. In addition to the normal functional mode, each scan cell 12 has two scan modes: the shift mode for scan operation; and the pass-through (P _T) mode for dynamic scan reconfiguration. In the P T mode, the input 14 of the scan cell 12 is passed through the scan cell 12 and goes directly to the output 16 without requiring scan clock(s) 18. The scan configuration controller 20 sets the scan mode of each scan cell 12 based on the configuration input 22. When m scan cells 12 in a scan chain 10 of length n (m < ή) are set to the P T mode, the resulting scan chain 10 is shorter having a length of n - m.

Existing designs of scan cells can be modified to facilitate the new pass-through mode. One simple modification is to gate the clock 18 of each latch with a 2-input OR gate 24 whose other input is the scan mode — shift or pass-through — control input 26 with an inverter-based D-latch 28 example, as illustrated in FIGURE IB, which is a schematic diagram of an inverter-based D-latch with pass-through. The clock 18 is blocked from passing the 2-input OR gate 24 when the P T input 26 is set to logic 1 forcing the inverter-based D-latch 28 into the pass-through mode. When the P T input 26 is set to logic 0, the inverter-based D-latch 28 is set to the normal shift mode for scan and functional operations. The pass-through mode for other latch designs, such as NAND- based, can be implemented in "similar ways. With master-slave scan flip-flops, the master and slave latches must be set in the pass-through mode at the same time. In cases where logic blocks are placed between master and slave latches for performance improvements, latches to be set to the pass-through mode must be selected carefully. This clock-gating may also be implemented with local scan clock distributions to control a set of scan cells with one scan configuration control signal, so that the use of the gating blocks can be reduced.

The scan configuration controller 20 can be as simple as a shift register, with each bit controlling a single scan configuration unit consisting of either a single scan cell or a set of scan cells. Additional circuits, such as decoders, may be used to best distribute the scan configuration control signals. It is recommended that scan operations with identical scan configurations are to be performed as a group to reduce the number of times to reconfigure the scan structures.⁹

Unlike the dynamic scan approach, which uses a multiplexer to' by-pass a scan cell or a segment of a scan chain, the proposed method doesn't directly add circuit components — transistors and wires — between the data input 14 and the output 16 of scan cells 12. Therefore, the impact to data path is limited — if not zero — and the hardware overhead is relatively less.

The proposed dynamically-reconfigurable scan chain architecture can also be applied to parallel scan chain configurations, such as those used in the STUMPS and some BIST and test compression methodologies. When applied to parallel configurations of scan chains, one or more controllers may be used to spread the scan configuration control accesses. An optimal design of the scan configuration control access would require balancing the need of greater configuration flexibility with minimal hardware overhead and minimal impact to design, implementation, and performance metrics.

FIGURE 2, which is a block diagram of reconfigurable parallel scan chains, illustrates a simple distribution of scan configuration control access network 30 with parallel scan chains 32 where a single scan configuration controller 20 is used. Similar to hierarchical memory systems, a hierarchical scan configuration control system can also be devised. One- disadvantage shared by this proposed approach and the dynamic scan method¹⁰ is the configuration control lines 34 that must reach every reconfigurable scan

⁹ A. R. Pandey and J. H. Pate!, ^' "Reconfiguration Techniques for Reducing Test Time and Test Data Volume in Illinois Scan Structure Based Designs, " in the Proceedings of the IEEE VLSI Test Symposium, pp. 9- 15, 2002; S. Samaranayake, N. Sitchinava, R. Kapur, M. B. Amin, and T.W. Williams, "Dynamic Scan: Driving Down the Cost of Test, " IEEE Computer, pp. 63-68, October 2002.

'⁰ Jd. unit 36 — either individual scan cells or a segment of a scan chain — across a potentially large silicon area. Therefore, the scan configuration control access network 30 must be carefully designed.

An alternative is to employ technologies developed with pre-manufactured silicon platforms, such as SRAM-based FPGAs — for example, by Xilinx Inc., www.xilinx.com. With SRAM-based FPGA technologies, programmable interconnect switches are used to configure interconnects with pre-laid wires to connect circuit blocks.. These switches are controlled by their corresponding memory bits. Based on the stored value, a controlling memory bit can either turn ON or turn OFF its switch. The scan configuration control access network 30 as shown in FIGURE 2 can be eliminated by employing programmable scan-mode switches 38. Depending on the controlling memory bit, a programmable scan-mode switch 38 connects a scan configuration signal either to logic 1 (V _DU) or logic 0 (GND). Each programmable scan- mode switch 38 controls the scan mode of the same reconfigurable scan units 36 on two neighboring scan chains 32, as illustrated in FIGURE 3, which is a block diagram of reconfigurable parallel scan chains.

Reconfigurable Scan Array Structure

A long single scan chain 32 sometimes may be implemented with multiple shorter scan chains 40 placed in parallel and configured as a multi-row single scan chain 42, as shown in FIGURE 4A, which 'is a block diagram of a fixed-length multi-row scan chain. The shorter scan chains 40 may have different lengths.

A reconfigurable long single multi-row scan chain 44 can be constructed by placing programmable scan configuration switches 46 on both ends 48 of the scan rows 50. The resulting scan chain structure is reconfigurable, as shown in FIGURE 4B, which is a block diagram of a reconfigurable scan structure. The programmable scan configuration switches 46 can be programmed to connect any number of terminals 52 for specific configurations and applications, as illustrated in FIGURE 4C, which are block diagrams of programmable scan configuration switches. A very long multi-row scan chain 54 may be broken down to small segments 56 that are separated by 3-and 4- terminal programmable scan configuration switches 46, so that various scan configurations are possible for different designs and applications by programmed connections 58, as shown in FIGURES 5 A and 5B, which are, respectively, a block diagram of a reconfigurable multi-row single scan chain structure wherein S₃ and S₄ are programmable scan configuration switches, and a block diagram of a reconfigured multi- row scan chain. The programmable scan configuration switches 46 are similar to those programmable interconnect switches used in SRAM-based FPGAs. . The architecture of a reconfϊgurable scan array structure 60 is shown in FIGURE 6, which is a block diagram of reconfigurable scan array structures. Multiple scan cell segments 62 are arranged as an array 64. Programmable scan-mode control switches 66 are placed between the same scan cells 68 on two neighboring scan segments 70. Programmable scan configuration switches 72 are placed between two scan segments 62 on the same row 74 as well as at the left and right sides 76, 78 of the scan array structure 60.

The reconfigurable scan array structure 60 provides greater flexibility in customizing scan configurations for post-manufacturing applications. The programmable scan configuration switches 72 are used to provide access points into the array structures 60 by SIs, SOs or MlSRs, and other manufacturing-critical components, as well as enabling many scan configurations. The programmable scan-mode control switches 66 enable fine-tuning custom scan configurations to maximize effectiveness and efficiency for individual applications and designs.

Conclusions

The dynamically-reconfigurable scan structures can be applied in various combinations to pre-manufactured and pre-structured silicon implementation platforms. These structures enable chip designers and manufacturing engineers to tailor individual post-manufacturing processes, such as implementation debugging, manufacturing diagnosis, etc., for specific and individual designs implemented with the common platforms. The capability of sharing the built-in scan structures, while enabling great flexibility in post-manufacturing reconfigurations for specific applications, can reduce design efforts, improve predictability in manufacturing processes, reduce manufacturing and test costs, etc. It will be understood that each of the elements described above or two or more together may also find a useful application in other types of constructions differing from the types described above.

While the invention has been illustrated and described as embodied in a reconfigurable scan array structure, however, it is not limited to the details shown, since it will be understood that various omissions, modifications, substitutions, and changes in the forms and details of the de.vice illustrated and its operation can be made by those skilled in the art without departing in any way from the spirit of the present invention.

Without further analysis the foregoing will so fully reveal the gist of the present invention that others can by applying current knowledge readily adapt it for various applications without omitting features that from the standpoint of prior art fairly constitute characteristics of the generic or specific aspects of the invention.

Claims

The invention claimed is:

1. A reconfigurable scan array structure, wherein said scan array structure has left and right sides, comprising: a) multiple scan cell segments; b) programmable scan-mode control switches; and c) programmable scan configuration switches; wherein said multiple scan cell segments are arranged in an array; wherein said programmable scan-mode control switches are placed between same scan cells on two neighboring scan cell segments; and wherein said programmable scan configuration switches are placed between two scan cell segments on a same row as well as said left and right sides of said scan array structure.

2. A reconfigurable scan array structure for providing greater flexibility in customizing scan configurations for post-manufacturing applications, comprising: a) first means for providing access points into said scan array structure and enabling multiple scan configurations; and b) second means for enabling fine-tuning custom scan configurations to maximize effectiveness and efficiency for individual applications and designs.