WO2007136941A2 - Flip chip mlp with folded heat sink - Google Patents

Flip chip mlp with folded heat sink Download PDF

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Publication number
WO2007136941A2
WO2007136941A2 PCT/US2007/066367 US2007066367W WO2007136941A2 WO 2007136941 A2 WO2007136941 A2 WO 2007136941A2 US 2007066367 W US2007066367 W US 2007066367W WO 2007136941 A2 WO2007136941 A2 WO 2007136941A2
Authority
WO
WIPO (PCT)
Prior art keywords
mlp
heat sink
leads
assembly
folded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2007/066367
Other languages
French (fr)
Other versions
WO2007136941A3 (en
Inventor
Jonathan A. Noquil
Yong Liu
Jocel Gomez
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Priority to DE112007001227T priority Critical patent/DE112007001227T5/en
Priority to JP2009511131A priority patent/JP2009537990A/en
Publication of WO2007136941A2 publication Critical patent/WO2007136941A2/en
Publication of WO2007136941A3 publication Critical patent/WO2007136941A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/10—Arrangements for heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/481—Leadframes for devices being provided for in groups H10D8/00 - H10D48/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07336—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/076—Connecting or disconnecting of strap connectors
    • H10W72/07631—Techniques
    • H10W72/07636—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/761—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors
    • H10W90/766—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • This invention relates in general to semiconductor die packages and methods of making such packages and more particularly to a flip chip molded leadless package (MLP) with a folded heat sink and methods for making and using such a flip chip MLP.
  • MLP flip chip molded leadless package
  • a semiconductor package assembly comprising:
  • MLP molded leadless package
  • a folded heat sink attached to said exposed upper surface of said MLP, said folded heat sink including a planar member generally coextensive in size with said
  • MLP and in contact with said upper surface of said MLP and including one or more leads extending generally perpendicularly to said planar member in a direction towards said lower surface.
  • said MLP includes a power flip chip MOSFET having a drain at said exposed upper surface, wherein said heat sink is attached to said drain, and wherein said one or more leads of said heat sink function as drain leads.
  • FIGS. IA and IB are respective top side and bottom side perspective views of an embodiment of a flip chip MLP with a folded heat sink according to the present invention
  • FIG. 2 is a top perspective view of a lead frame used to form the flip chip
  • FIG. 3A is a top perspective view of the lead frame of FIG. 2 with a semiconductor chip of a first size mounted on the lead frame;
  • FIG. 3B is a top perspective view of the lead frame of FIG. 2 with a semiconductor chip of a second size mounted on the lead frame;
  • FIG. 3C is a top perspective view of the lead frame of FIG. 2 with a semiconductor chip of a third size mounted on the lead frame;
  • FlG. 4 is a top view of a molded array of the lead frames and semiconductor die shown in FIG. 3A;
  • FIG. 5 A is a top view of a flip chip MLP with the semiconductor die shown in FlG. 3A; [003O)]
  • FIG. 5B is a top view of a flip chip MLP with the semiconductor die shown in FIG. 3 B;
  • FIG. 5C is a top view of a flip chip MLP with the semiconductor die shown in FfG. 3C;
  • FlG. 6 is a diagram of the steps used in one embodiment of the present invention to attach the flip chip MLP to folded heat sink;
  • FIG. 7 is a side cross sectional view of the flip chip MLP with a folded heat sink shown in FIGs. IA and IB mounted on solder paste on a conductive track on a printed circuit (PC) board;
  • PC printed circuit
  • FIG. 8 is FIG. 7 after the solder paste has been reflowed
  • FIG. 9 is the same side cross sectiona! view of FlG. 7 except that the folded leads of the folded heat sink have been shortened.
  • FIG. 10 is FIG. 9 after the solder paste has been reflowed.
  • FIGs. IA and IB show an embodiment of a flip chip MLP with a folded heat sink 10 according to the present invention.
  • a flip chip power MLP device 12 is attached to a folded heat sink 14.
  • the device 12 may include a power semiconductor device and a lead frame encapsulated in molding material.
  • the device 12 has a source pad 16, three source lands or leads 18, a gate lead 20, and four leads 22 with no connections on the bottom side of the device 12.
  • a drain region 24 (shown in FIGs. 5 A-C) is exposed on the top side of device 12. Molding material 26 is formed around the source pad 16, the source leads 18, the gate lead 20, the no connection leads 22, and the drain region 24.
  • the folded heat sink 14 includes a planar member 28, generally coextensive in area with the top of the device 12, and folded leads 30 extending generally perpendicular to member 28 and along the side of device 12 with the no connection leads 22,
  • the folded heat sink 14 can be of any electrically and thermally conductive material such as copper, aluminum, conductive polymer, or the like.
  • the folded heat sink 14 is electrically and thermally attached to the drain region 24, and the folded leads 30 provide an emitter connection to the printed circuit (PC) board on which the flip chip is mounted.
  • PC printed circuit
  • the flip chip MLP with a folded heat sink J O may have a foot print of a SO-8 package. This is possible because the lengths of the source and gate lands 38, 20 are equal to the width of the no connection lands 22 plus the width of the folded leads 30 plus the gap between the no connection lands 22 and the folded leads 30.
  • FIG. 2 is a top conceptual perspective view of a half etched lead frame 40 used in forming the flip chip MLP with a folded heat sink 10 without showing the tie bars used to hold the individual elements of the lead frame 40 in place during the subsequent processing through the molding operation.
  • the lead frame 40 is one of an array of lead frames with the tie bars joining the lead frames 40 within the array.
  • the source pad 16 is attached to the source leads 18, and a gate pad 46 is attached to the gate lead 20.
  • FIGs. 3 A, 3B, and 3C are top conceptual perspective views of the lead frame of FIG. 2 with three different sized semiconductor die, 50, 52, and 54, respectively, which may be power MOSFETs, attached to the source pad 16 and the gate pad 46.
  • the semiconductor die 50, 52, and 54 may have solder bail contacts and may be attached to the tead frame 40 using solder paste and a solder reflow operation.
  • FIG. 4 is a top view of an array 58 of the lead frames 40 after the molding operation with their attached semiconductor dies 50 shown in FIG. 3 ⁇ .
  • the back sides 60 of the semiconductor dies 50 are visible in FIG. 4.
  • the lines 62 are indicative of the horizontal and vertical sawing used in the singulation of the individual flip chip MLP devices 12.
  • FIGs. 5A, 5B and 5C are top perspective views of the lead frames 40 after the molding operation with the semiconductor dies 50, 52, and 54, respectively, shown in FlGs. 3 A, 3B, and 3 C, respectively.
  • the bottom 60 of the semiconductor die 50 fills an appreciable amount of the area of the top of the flip chip MLP device 12, and thereby provides a large area for attachment of the device 12 to the folded heat sink 14.
  • FIG. 6 is a diagram of the steps used in one embodiment of the present invention to attach the flip chip MLP device 12 to the folded heat sink 14.
  • flip chip MLP devices 12 move on a conveyer belt 80.
  • a pick rod 82 displaces the flip chip MLP devices 12 as indicated by the arrow 84 which have passed electrical test into a handling device (not shown).
  • a soft solder dispenser 86 pushes soft solder onto the bottom of the planar member 28 of the folded heat sink 14 after it has been heated enough to melt the soft solder wire from the dispenser 88.
  • the flip chip MLP device 12 is aligned with the folded heat sink 14 as indicated by the arrow 86 and the two pieces are pressed together to solder the flip chip MLP device 12 and the folded heat sink 14 to form the flip chip MLP with a folded heat sink 10 as indicated by the arrow 92.
  • the use of soft solder provides an easy soldering process where the wire is melted and attached on the same machine. Good alignment is achieved since alignment is controlled during pick-up with 2 mil placement accuracy possible, and there is minimal voiding of the solder.
  • FlG. 7 is a side cross sectional view of the flip chip MLP device with a folded heat sink 10 shown in FlGs. ] A and I B mounted on first and second solder paste regions 104 and 106, which in turn have been laid down on first and second conductive tracks 108 and 1 10, respectively, on a PC board 1 12. As can be seen in FIG. 7, the no connection lands 22 and the bottoms of the folded leads 30 are planar and rest on the solder paste region 106.
  • FIG. 7 is FIG. 7 after the solder paste regions 104 and 106 have been reflowed.
  • the solder 1 10 from the solder paste region 106 forms an electrical and thermal connection between the no connection leads 22, the folded leads 30 and the conductive track 1 10.
  • the no connect leads 22, which are adjacent the folding leads 30 of the folded heat sink 14, prevent excess solder around the folded leads 30 during soldering of the flip chip MLP with a folded heat sink 10 to the PC board 112.
  • FIG. 9 is the same side cross sectional view of FIG. 7 except that the folded leads 30 of the folded heat sink of FlGs. 7 and 8 have been shortened as indicated by the gap 122, which in one embodiment is about 30 microns, to provide a more reliable solder connection between the folded leads 120 of the folded heat sink 118 and the conductive track ] 10.
  • the soider paste 1 16 is about 150 microns high prior to being reflowed.
  • FIG. 10 is FIG. 9 after the solder pastes 104 and 1 16 have been reflowed. Because of the gap between the ends of the folded leads 120 and the conductive track 1 10, the reflowed solder 1 16 can adhere fully to the bottoms of the folded leads 120. [0049)]
  • the invention has been described in detail with particular reference to certain preferred embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention.

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A semiconductor package assembly including a molded leadless package (MLP) having an exposed top emitter pad and an exposed bottom source pad. A folded heat sink is attached to the exposed top emitter pad of the MLP by a soft solder attach process. The folded heat sink has a planar member generally coextensive in size with the MLP and in electrical and thermal contact with the top emitter pad of the MLP, and also has one or more leads extending generally perpendicularly to the planar member in a direction towards the lower surface of the MLP. These heat sink leads may provide the emitter connection to a printed circuit (PC) board.

Description

FLIP CHIP MLP WITH FOLDED HEAT SINK
CROSS-REFERENCE TO RELATED APPLICATIONS [000I)J This application claims the benefit of U.S. Provisional Patent Application Serial No. 60/802,182, filed on May 19, 2006, which application is hereby incorporated by reference. Reference is also made to a related application entitled "Dual Side Cooling Integrated Transistor Module and Methods of Manufacture," Attorney Docket No. 3021710 (17732.62870.00).
FIELD OF THE INVENTION
[0002)] This invention relates in general to semiconductor die packages and methods of making such packages and more particularly to a flip chip molded leadless package (MLP) with a folded heat sink and methods for making and using such a flip chip MLP.
BACKGROUND OF THE INVENTION
[0003)] Power module packages typically use wire bonding which is a source of high resistance and noise. As the number of connections using wire bonding has increased significantly, problems of increased resistance, signal delays and signal interference has limited the further efficiency and density of future power modules. MLP and flip chip technologies have resulted in improved packaging designs. US Patent 6,507, 120 B2, issued Jan. 34, 2003, inventors Lo et al., and US Patent 6,867,072 B l, issued Mar. 15, 2005, inventors Shiu et al., disclose flip chip and molding techniques which are improvements over traditional wire bonding techniques. US Patent 6,891,256 B2, issued may 10, 2005. inventors Joshi et al., discloses a thin, thermally enhanced flip chip in a leaded molded package which has been suitable for the applications for which it was intended. The package disclosed, however, has certain drawbacks, viz., the leaded molded package occupies more space than a molded leadless package, the heat sink is designed only for a leaded package and not a leadless package, and the method of heat sink attachment is not defined clearly (only that a clip is coupled to the exposed drain, and that paste dispense or printing may be used for such clip attachment). [0004)] With a current MLP package design utilizing a wire bond technique, performance, when a power device is housed, will be noncompetitive in terms of electrical and thermal characteristics. The generation of an MLP with clip bonding on the source and wirebond on the gate is costly and tedious and requires a longer processing flow (die attach, clip attach, and wirebond).
There is thus a need for a flip chip power device MLP type of package that is competitive in terms of electrical and thermal characteristics, that uses a simpler, less costly and tedious process to produce the package, and that efficiently addresses cooling problems.
SUMMARY OF THE INVENTION
[ΘΘ05)] According to the present invention there is provided a solution to these problems and fulfillment of these needs.
[0006)] According to an aspect of the present invention there is provided
[0007)] a semiconductor package assembly comprising:
[0008)] a molded leadless package (MLP) having an exposed upper surface and a lower surface; and
[0009)] a folded heat sink attached to said exposed upper surface of said MLP, said folded heat sink including a planar member generally coextensive in size with said
MLP and in contact with said upper surface of said MLP and including one or more leads extending generally perpendicularly to said planar member in a direction towards said lower surface.
[001O)] According to another feature of the present invention there is provided
[OOIl)] a semiconductor package assembly comprising:
[0012)] a molded leadless package (MLP) having an exposed upper surface and a lower surface; and
[0013)] a folded heat sink attached to said exposed upper surface of said MLP. said folded heat sink including a planar member generally coextensive in size with said
MLP and in contact with said upper surface of said MLP and including one or more leads extending generally perpendicularly to said planar member in a direction towards said lower surface; wherein said MLP includes a power flip chip MOSFET having a drain at said exposed upper surface, wherein said heat sink is attached to said drain, and wherein said one or more leads of said heat sink function as drain leads.
[0014)] According to a further feature of the present invention there is provided [0015)] a method of making a semiconductor package assembly comprising:
[0016)] providing on a tape a half etched lead frame having a die attach pad, a gate lead, one or more source ϊeads, and one or more no connection leads;
10017)] flip chip attaching a power MOSFET to said die attach pad of said lead frame;
[0018)] molding said lead frame and attached power MOSFET flip chip on said tape, such that the drain of said power MOSFET is exposed;
[0019)] producing a molded leadless package (MLP) by sawing said molded lead frame and power MOSFET on said tape;
[002O)] providing a heat sink having a planar member and one or more leads extending generally perpendicularly from said planar member; and
[002I)] picking up a sawn MLP from said tape and soft solder attaching said MLP to said folded heat sink such the heat sink is in contact with said exposed drain and said heat sink leads end in the vicinity of said no connection leads,
BRIEF DESCRIPTION OF THE DRAWINGS
[0022)] The aforementioned and other features, characteristics, advantages, and the invention in general wiil be better understood from the following more detailed description taken in conjunction with the accompanying drawings, in which:
(0023)] FlGs. IA and IB are respective top side and bottom side perspective views of an embodiment of a flip chip MLP with a folded heat sink according to the present invention;
[0024)] FIG. 2 is a top perspective view of a lead frame used to form the flip chip
MLP with a folded heat sink shown in FlGs. IA and IB;
[002S)] FIG. 3A is a top perspective view of the lead frame of FIG. 2 with a semiconductor chip of a first size mounted on the lead frame;
[0026)] FIG. 3B is a top perspective view of the lead frame of FIG. 2 with a semiconductor chip of a second size mounted on the lead frame;
[0027)] FIG. 3C is a top perspective view of the lead frame of FIG. 2 with a semiconductor chip of a third size mounted on the lead frame;
(0028)] FlG. 4 is a top view of a molded array of the lead frames and semiconductor die shown in FIG. 3A;
[0029)[ FIG. 5 A is a top view of a flip chip MLP with the semiconductor die shown in FlG. 3A; [003O)] FIG. 5B is a top view of a flip chip MLP with the semiconductor die shown in FIG. 3 B;
10031)] FIG. 5C is a top view of a flip chip MLP with the semiconductor die shown in FfG. 3C;
[0032)] FlG. 6 is a diagram of the steps used in one embodiment of the present invention to attach the flip chip MLP to folded heat sink;
[0033)] FIG. 7 is a side cross sectional view of the flip chip MLP with a folded heat sink shown in FIGs. IA and IB mounted on solder paste on a conductive track on a printed circuit (PC) board;
[0034)] FIG. 8 is FIG. 7 after the solder paste has been reflowed;
[0035)] FIG. 9 is the same side cross sectiona! view of FlG. 7 except that the folded leads of the folded heat sink have been shortened; and
[0036)] FIG. 10 is FIG. 9 after the solder paste has been reflowed.
[0037)] It will be appreciated that for purposes of clarity and where deemed appropriate, reference numeral have been repeated in the figures to indicate corresponding features. Also, the relative size of various objects in the drawings has in some cases been distorted to more clearly show the invention.
DESCRIPTION OF THE INVENTION
[0038)] FIGs. IA and IB show an embodiment of a flip chip MLP with a folded heat sink 10 according to the present invention. As shown, a flip chip power MLP device 12 is attached to a folded heat sink 14. The device 12 may include a power semiconductor device and a lead frame encapsulated in molding material. The device 12 has a source pad 16, three source lands or leads 18, a gate lead 20, and four leads 22 with no connections on the bottom side of the device 12. A drain region 24 (shown in FIGs. 5 A-C) is exposed on the top side of device 12. Molding material 26 is formed around the source pad 16, the source leads 18, the gate lead 20, the no connection leads 22, and the drain region 24. The folded heat sink 14 includes a planar member 28, generally coextensive in area with the top of the device 12, and folded leads 30 extending generally perpendicular to member 28 and along the side of device 12 with the no connection leads 22, The folded heat sink 14 can be of any electrically and thermally conductive material such as copper, aluminum, conductive polymer, or the like. The folded heat sink 14 is electrically and thermally attached to the drain region 24, and the folded leads 30 provide an emitter connection to the printed circuit (PC) board on which the flip chip is mounted.
[0039)] As can be appreciated by viewing FlG. IB, the flip chip MLP with a folded heat sink J O may have a foot print of a SO-8 package. This is possible because the lengths of the source and gate lands 38, 20 are equal to the width of the no connection lands 22 plus the width of the folded leads 30 plus the gap between the no connection lands 22 and the folded leads 30.
[004O)] FIG. 2 is a top conceptual perspective view of a half etched lead frame 40 used in forming the flip chip MLP with a folded heat sink 10 without showing the tie bars used to hold the individual elements of the lead frame 40 in place during the subsequent processing through the molding operation. The lead frame 40 is one of an array of lead frames with the tie bars joining the lead frames 40 within the array. The source pad 16 is attached to the source leads 18, and a gate pad 46 is attached to the gate lead 20.
[004I)] FIGs. 3 A, 3B, and 3C are top conceptual perspective views of the lead frame of FIG. 2 with three different sized semiconductor die, 50, 52, and 54, respectively, which may be power MOSFETs, attached to the source pad 16 and the gate pad 46. The semiconductor die 50, 52, and 54 may have solder bail contacts and may be attached to the tead frame 40 using solder paste and a solder reflow operation. [0042)] FIG. 4 is a top view of an array 58 of the lead frames 40 after the molding operation with their attached semiconductor dies 50 shown in FIG. 3Λ. The back sides 60 of the semiconductor dies 50 are visible in FIG. 4. The lines 62 are indicative of the horizontal and vertical sawing used in the singulation of the individual flip chip MLP devices 12.
[0043)] FIGs. 5A, 5B and 5C are top perspective views of the lead frames 40 after the molding operation with the semiconductor dies 50, 52, and 54, respectively, shown in FlGs. 3 A, 3B, and 3 C, respectively. In FIG. 5A the bottom 60 of the semiconductor die 50 fills an appreciable amount of the area of the top of the flip chip MLP device 12, and thereby provides a large area for attachment of the device 12 to the folded heat sink 14. However, the semiconductor die 52 and 54, shown in FIGs. 3B and 3C, respectively, provide a significantly decreased area for attachment to the folded heat sink 14. Areas of a printable solderable material 70 and 72 have been applied to the top of the mold material in FIGs. 5 A and 5B, respectively, to enhance the bond between the MLP devices 12 to the folded heat sink 14, [0044)] FIG. 6 is a diagram of the steps used in one embodiment of the present invention to attach the flip chip MLP device 12 to the folded heat sink 14. As shown in FlG. 6, flip chip MLP devices 12 move on a conveyer belt 80. A pick rod 82 displaces the flip chip MLP devices 12 as indicated by the arrow 84 which have passed electrical test into a handling device (not shown). At the same time a soft solder dispenser 86 pushes soft solder onto the bottom of the planar member 28 of the folded heat sink 14 after it has been heated enough to melt the soft solder wire from the dispenser 88. After the appropriate amount of soft solder 90 has been melted onto the folded heat sink 14, the flip chip MLP device 12 is aligned with the folded heat sink 14 as indicated by the arrow 86 and the two pieces are pressed together to solder the flip chip MLP device 12 and the folded heat sink 14 to form the flip chip MLP with a folded heat sink 10 as indicated by the arrow 92. Compared to solder cream, the use of soft solder provides an easy soldering process where the wire is melted and attached on the same machine. Good alignment is achieved since alignment is controlled during pick-up with 2 mil placement accuracy possible, and there is minimal voiding of the solder. In the solder cream process, however, the paste needs to be printed with a printer and stencil, a reflow machine is needed, alignment is affected during the reflow process with a tendency to rotate the die, and voiding is difficult to control during reflow, since flux content is trapped during reflow. The soft solder attach process avoids these problems of the solder cream attach process. 10045)] FlG. 7 is a side cross sectional view of the flip chip MLP device with a folded heat sink 10 shown in FlGs. ] A and I B mounted on first and second solder paste regions 104 and 106, which in turn have been laid down on first and second conductive tracks 108 and 1 10, respectively, on a PC board 1 12. As can be seen in FIG. 7, the no connection lands 22 and the bottoms of the folded leads 30 are planar and rest on the solder paste region 106.
[0046)3 FlG- 8 is FIG. 7 after the solder paste regions 104 and 106 have been reflowed. As can be seen in FIG. 8 the solder 1 10 from the solder paste region 106 forms an electrical and thermal connection between the no connection leads 22, the folded leads 30 and the conductive track 1 10. Although the width of the no connection lands 22 plus the width of the folded leads 30 is less than the width of the source and gate lands 18, 22 the whetting of the solder 1 16 up the sides of the no connection lands 22 and the folded leads 30 provides a solder connection with the conductive track 106 comparable to the solder connection of the source and gate lands 18, 20 to the conductive track 104. Moreover, the no connect leads 22, which are adjacent the folding leads 30 of the folded heat sink 14, prevent excess solder around the folded leads 30 during soldering of the flip chip MLP with a folded heat sink 10 to the PC board 112.
(0047)] FIG. 9 is the same side cross sectional view of FIG. 7 except that the folded leads 30 of the folded heat sink of FlGs. 7 and 8 have been shortened as indicated by the gap 122, which in one embodiment is about 30 microns, to provide a more reliable solder connection between the folded leads 120 of the folded heat sink 118 and the conductive track ] 10. Preferably, for use with this particular embodiment, the soider paste 1 16 is about 150 microns high prior to being reflowed. [0048)] FIG. 10 is FIG. 9 after the solder pastes 104 and 1 16 have been reflowed. Because of the gap between the ends of the folded leads 120 and the conductive track 1 10, the reflowed solder 1 16 can adhere fully to the bottoms of the folded leads 120. [0049)] The invention has been described in detail with particular reference to certain preferred embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention.

Claims

1. A semiconductor package assembly comprising: a molded leadless package (MLP) Slaving an exposed upper surface and a lower surface; and a folded heal sink attached to said upper exposed surface of said MLP, said folded heat sink including a planar member generally coextensive in size with said MLP and in contact with said upper surface of said MLP and one or more leads extending generally perpendicularly to said planar member in a direction towards said lower surface.
2. The assembly of claim 1 wherein said heat sink is attached to said MLP by soft solder.
3. A semiconductor package assembly comprising: a molded leadless package (MLP) having an exposed upper surface and a lower surface; and a folded heat sink attached to said exposed upper surface of said MLP, said folded heat sink including a planar member generally coextensive in size with said MLP and in contact with said upper surface of said MLP and including one or more leads extending generally perpendicularly to said planar member in a direction towards said lower surface; wherein said MLP includes a power flip chip MOSFET having a drain at said exposed upper surface, wherein said heat sink is attached to said drain, and wherein said one or more leads of said heat sink function as drain leads.
4. The assembly of claim 3 wherein said heat sink is attached to said MLP by soft solder.
5. The assembly of claim 3 wherein the exposed upper surface of said MLP has a non-solderable area which is provided with solderable polymer printing,
6. The assembly of claim 3 wherein said MLP has one or more no connection leads which arc adjacent said drain leads of said heat sink and which are soldered together with the folded heat sink when said assembly is soldered to a printed circuit board.
7. The assembly of claim 3 wherein said ends of said heat sink leads are coplanar with said lower surface of said MLP.
8. The assembly of claim 3 wherein said ends of said heat sink leads stop short of said lower surface of said MLP to enhance the solder connection of said leads when said assembly is soldered to a printed circuit board.
9. A method of making a semiconductor package assembly comprising: providing on a tape a half etched lead frame having a die attach pad, a gate lead, one or more source leads, and one or more no connection leads; flip chip attaching a power MOSFET to said die attach pad of said lead frame; molding said lead frame and attached power MOSFET flip chip on said tape, such that the drain of said power MOSFET is exposed; producing a molded leadless package (MLP) by sawing said molded lead frame and power MOSFET on said tape; providing a heat sink having a planar member and one or more leads extending generally perpendicularly from said planar member; and picking up a sawn MLP from said tape and soft solder attaching said MLP to said folded heat sink such that the heat sink is in contact with said exposed drain and said heat sink leads end in the vicinity of said no connection leads.
PCT/US2007/066367 2006-05-19 2007-04-11 Flip chip mlp with folded heat sink Ceased WO2007136941A2 (en)

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US11/625,100 2007-01-19
US11/625,100 US7812437B2 (en) 2006-05-19 2007-01-19 Flip chip MLP with folded heat sink

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US7812437B2 (en) 2010-10-12
DE112007001227T5 (en) 2009-09-10
KR20090009838A (en) 2009-01-23
TW200802760A (en) 2008-01-01
JP2009537990A (en) 2009-10-29
US20110003432A1 (en) 2011-01-06
US20070267728A1 (en) 2007-11-22
US8119457B2 (en) 2012-02-21
WO2007136941A3 (en) 2008-04-10

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