WO2007133915A1 - Integrated optical waveguide assemblies - Google Patents

Abstract

An optical waveguide assembly is described including a substrate and an optical waveguide positioned on the substrate. The waveguide includes a core layer having a refractive index less than that of the substrate. The waveguide also includes two or more lower cladding layers. A refractive index for a first lower cladding layer, closer to the substrate, is less than for a second lower cladding layer, closer to the core. In one embodiment, the substrate is provided with an optical device alignment feature for aligning the waveguide with an optical fiber. In one embodiment, the first and second lower cladding layers are undoped.

Description

INTEGRATED OPTICAL WAVEGUIDE ASSEMBLIES

Field of the Invention

The present invention is directed generally to optical waveguide devices fabricated on a substrate having a refractive index which is higher than the refractive index of the waveguide cladding.

Background of the Invention

Optical waveguide chips are utilized in a wide variety of optical systems, such as sensors and telecommunications networks. The optical waveguide chips are substantially planar optical circuits consisting of one or more optical waveguides fabricated on a silicon or silicon dioxide substrate. In one common construction, the waveguide cores are sandwiched between lower and upper cladding layers.

For use, the waveguides of the waveguide chip are connected to external circuits or other devices by coupling the ends of the waveguides to optical fibers. The accuracy and precision of the alignment between the fiber and waveguide cores greatly affects the optical coupling loss experienced at the interface of the fiber and waveguide.

Because of the unique micromechanical properties of silicon and the advanced capabilities of silicon microelectronics technology, silicon substrates are particularly well-suited for systems that integrate waveguides with precision mechanical structures. For example, anisotropic etching of silicon can be used to produce very precise structures. As a result, precise alignment features and other precise micromechanical structures can be integrated on silicon substrates together with waveguides. However, care must be taken when fabricating optical waveguides on silicon substrates, otherwise optical coupling between the waveguide and substrate can occur; this results in degradation of the optical performance of the waveguide. Silicon has a very high refractive index compared to silica (about 3.5 for silicon, as compared to 1.44 for silica at telecommunications wavelengths). As a consequence of this mismatch in optical properties, if the evanescent electric field of the waveguide comes in contact with the silicon substrate, the waveguide mode becomes a "leaky mode", that is, the loss of the waveguide increases. Furthermore, because of the different boundary conditions associated with the two different optical polarizations in the waveguide, the losses are different for the two different optical polarizations (see W. Stutius and W. Streifer, Silicon Nitride Films on Silicon for Optical Waveguies, Applied Optics Vol. 16, p 3218 (1977) and W. Borland et al, Properties of Four-Layer Planar Optical Waveguides Near Cutoff, IEEE Journal of Quantum Electronics, Vol. QE-23, p 1172 (1987)). Polarization dependent loss (or "PDL") is a very undesirable property in waveguide devices meant for applications in fiber optic communications systems. This is because the optical polarization is not controlled in the optical fiber, and fluctuates randomly with time. Thus waveguide devices that have PDL induce a time-varying signal throughput that degrades system performance. The usual approach to reducing the PDL resulting from substrate coupling is to use a very thick lower cladding layer (between the waveguide core and silicon substrate) to reduce the coupling of the waveguide field to the substrate. However, this approach conflicts with another consequence of the mismatch in the properties of silica and silicon. Because silica has a larger thermal expansion coefficient than silicon, and because silica waveguides are produced via high-temperature processes, silica waveguide layers on a silicon substrate are in a state of compressive stress. This stress, via the stress-optic effect, creates birefringence in the waveguide material. Birefringence, in turn, contributes to undesirable device characteristics, such as polarization mode dispersion ("PMD", which is a polarization dependence in the time it takes a signal to pass through the device), and PDL.

In addition to degrading the optical properties of the device, stress in the silicon degrades the quality and reproducibility of the selective etching process that is used to fabricate alignment v-grooves in the silicon. This degradation makes low-loss passive alignment of fibers to waveguides impractical. It is important to note that substrate-coupling-generated PDL occurs even in the complete absence of birefringence. This is true whether the birefringence arises due to stress-induced birefringence in the waveguide materials, or from the shape of the waveguide core. Thus earlier approaches which seek to reduce waveguide stress by modifying the waveguide structure, thus reducing stress-related birefringence, do not address this important mechanism. For example, neither the use of graded or multiple layers of cladding with thermal expansion coefficients configured to control stress (as taught in US 6,339,667), nor the use of grooves etched near the core to control stress birefringence (as taught in US 6,542,687), nor the use of a thin birefringence- compensating layer near the core (as taught in US 5,341,444), is effective in suppressing PDL resulting from substrate coupling.

The invention disclosed herein provides an approach to reducing PDL resulting from substrate coupling. This in turn means that for a given level of maximum tolerable PDL, the silica lower cladding layer can be made thinner, thus reducing thermal- expansion-induced stress, and thereby both reducing stress birefringence and improving the quality of v-grooves etched in the silicon substrate.

Summary of the Invention An optical waveguide assembly is described including a substrate and an optical waveguide positioned on the substrate. The waveguide includes a core layer having a refractive index less than that of the substrate and two or more lower cladding layers. The two or more lower cladding layers include a first lower cladding layer positioned between the core layer and the substrate and a second lower cladding layer positioned between the first lower cladding layer and the core. The waveguide further includes an upper cladding layer adjacent to and partially surrounding the core layer. A refractive index for the first lower cladding layer is less than for the second lower cladding layer. The substrate is provided with an optical device alignment feature for aligning the waveguide with an optical fiber. In another embodiment of the invention, a method of constructing an optical waveguide assembly is described, including the step of providing a substrate having an alignment feature pattern that defines optical alignment features. The method further includes constructing an optical waveguide on the substrate, including the steps of forming a first lower cladding layer on the substrate, forming a second lower cladding layer on the first lower cladding layer, forming a core layer, and forming an upper cladding layer adjacent to and partially surrounding the core layer. A refractive index for the first lower cladding layer is less than for the second lower cladding layer. The substrate has a refractive index larger than that of the core layer. The method also includes fabricating optical alignment features from the alignment feature pattern on the substrate. In yet another embodiment of the invention, an optical waveguide assembly is described including a substrate and an optical waveguide positioned on the substrate. In this embodiment, the waveguide includes a first undoped silica lower cladding layer adjacent to the substrate, a second undoped silica lower cladding layer adjacent to the first lower cladding layer, a core layer, and an upper cladding layer adjacent to and partially surrounding the core layer. A refractive index for the first lower cladding layer is less than for the second lower cladding layer.

The invention may be more completely understood by considering the detailed description of various embodiments of the invention that follows in connection with the accompanying drawings.

Brief Description of the Drawings FIG. 1 is a cross-sectional view of a waveguide structure having two lower cladding layers.

FIG. 2 illustrates an embodiment of an optical waveguide assembly having integral alignment features according to the invention.

FIG. 3 illustrates a substrate having an etch stop layer with an alignment feature pattern.

FIGS. 4 and 5 are cross-sectional illustrations of the formation of discrete waveguides on the substrate and etch stop layer of FIG. 3.

FIG. 6 illustrates the optical waveguide assembly of FIG. 2, prior to the formation of the integral alignment features. FIG. 7 illustrates another embodiment of an optical waveguide assembly having integral alignment features according to the invention.

FIG. 8 is a cross-sectional illustration of discrete waveguides in the optical waveguide assembly of FIG. 7.

FIG. 9 illustrates the optical waveguide assembly of FIG. 7, prior to the formation of the integral alignment features.

FIG. 10 is a cross-sectional view of a conventional waveguide structure having a single lower cladding layer.

FIG. 11 is an example of a typical 1 X 8 passive splitter layout. FIG. 12 shows the modeled mode profiles of relative electric field amplitude for two fabricated structures and for two comparison dual lower clad structures. FIG. 13 shows the tail of the modeled mode profiles of FIG. 12 near the substrate using a finer vertical scale.

FIG. 14 shows the PDL plotted against lower cladding thickness for various assumptions based upon a perturbation approach for a single lower clad structure. While the invention may be modified in many ways, specifics have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives following within the scope and spirit of the invention as defined by the claims.

Detailed Description of the Preferred Embodiments

The present invention is applicable to optical waveguide assemblies. The invention is particularly applicable to waveguide assemblies formed on a substrate where the refractive index of the substrate is higher than the refractive index of the deposited waveguide cladding layers. An important example of a waveguide assembly where the refractive index of the substrate is higher than that of the waveguide cladding is embodied by silica-based waveguide structures formed on a silicon substrate. This case is particularly important because it is possible to make waveguides of very high optical quality by using silica and doped silica, and the use of a silicon substrate enables the fabrication of integrated micromechanical structures such as fiber alignment grooves. These types of optical waveguide devices are particularly useful in the context of telecommunications devices, sensors, microlasers, and integrated optical amplifiers. Since silica-on-silicon is widely used and understood, the invention will be described as applied to that system. However, it is important to note that silica-based waveguides on silicon substrates are not the only materials combination that can benefit from the approach described here.

A waveguide structure is described that uses two lower cladding layers with different refractive indices instead of one layer of lower cladding. FIG. 1 is a cross- sectional view of one example of such a waveguide structure 2, (based on the silica-on- silicon system) including a silicon substrate 3, a first lower cladding layer 4, and a second lower cladding layer 5. The two lower cladding layers 4, 5 are positioned below the waveguide core 6 and the upper cladding 7. Conventional waveguide structures using silicon substrates have a single lower cladding layer. An example of a waveguide structure 8 having a single lower cladding layer 9 is shown in FIG. 10. The other layers of waveguide 8 of FIG. 10 are similar to the layers of waveguide 2 of FIG. 1 that bear the identical reference numbers: substrate 3, core 6, and upper cladding layer 7. In these structures with a single lower cladding layer, the relatively high index of the silicon substrate tends to capture light that comes in contact with the substrate. At the interface 10 with the substrate, there may be different mode field intensities for TE and TM light, leading to polarization dependent loss (PDL). Furthermore, the different boundary conditions for TE and TM light at the substrate interface causes the TE and TM modal losses to be different, even for the case where the TE and TM have the same modal amplitude at the substrate. To make a device with both low insertion loss and low PDL, one must make both TE and TM modal intensities at the substrate sufficiently small.

In the structure of FIG. 1, the second lower cladding layer 5 that is adjacent to the core 6 has an index that is slightly higher than the index of the first lower cladding layer 4 that is adjacent to the substrate 3, so that the optical mode stays close to the core. Both the first and second lower cladding layers 4, 5 have indices lower than the core 6. As a result of appropriate choices of the indices of refraction, the optical mode does not interact with the high index substrate, and this cause of PDL is addressed and PDL is reduced. The combined lower cladding layers can also be thinner in the structure of FIG. 1 than a single lower cladding layer in conventional devices. As a result, there is less mechanical stress. For various embodiments of a waveguide assembly of the invention using the silica-on-silicon materials system, the first lower cladding layer 4 has an index of refraction of at least 1.440, at least 1.457, not more than 1.48, not more than 1.46 and combinations of these upper and lower limits. One possible index value for the first lower cladding layer 4 is 1.457 for one embodiment. The second lower cladding layer 5 has an index of refraction that is higher than the first lower cladding layer 4 and lower than the core 6. For various embodiments of the waveguide assembly, the second lower cladding layer 5 has an index of refraction of at least 1.442, at least 1.459, not more than 1.482, not more than 1.462, and combinations of these upper and lower limits. The second lower cladding layer 5 preferably has an index of 1.4592 for one embodiment. In various embodiments, the first and second lower cladding layers have indices that differ from each other by at least 0.001, at least 0.0022, not more than 0.042, not more than 0.05, and combinations of these upper and lower limits. In one embodiment, the first and second lower cladding layers have indices that differ from each other by 0.0022. In one embodiment of the invention, the index contrast between the core 6 and second lower cladding layer 5 is at least 0.003. In another embodiment of the invention, the index contrast is at least 0.004. In one embodiment, the index contrast is not more than 0.01. One possible value for the index contrast is 0.0047.

In the embodiment of FIG. 1, the index of the upper cladding layer 7 is closely matched to the index of the second lower cladding layer 5. Preferably, the index of the upper cladding layer 7 is within 0.0005 of the second lower cladding layer 5. More preferably, the index of the upper cladding layer 7 is higher than the index of the second lower cladding, to prevent the mode from being squeezed toward the substrate.

During the process of making the waveguide assembly, the indices of refraction of the various layers are controlled by conventional methods. For a plasma-enhanced chemical vapor deposition (or "PECVD") process, parameters such as process pressure, gas flow, RF (radio frequency) power, doping, etc may be adjusted to control the refractive index. In one embodiment of the invention, methods are used to control the index of the two lower cladding layers that do not require doping. In an alternative embodiment, the indices are controlled by doping.

Because a waveguide assembly having two lower cladding layers with the indices of refraction described herein reduces the PDL, it is possible to construct the waveguide assembly on a silicon substrate with an acceptably low amount of PDL. As a result, the features of silicon can be utilized to create alignment features on the substrate. Examples of waveguide assemblies with alignment features will be described further herein.

The waveguide assembly 2 of FIG. 1 may be included as a part of many different types of optical devices. For example, the waveguide 2 may be a part of an optical splitter device. A 1x8 splitter device is just one example of the many different optical splitter configurations that are possible. FIG. 11 shows a typical configuration of the waveguide core of a 1x8 splitter device from a top view. Preferably, an optical splitter device of the present invention having two lower cladding layers will have fiber-to-fiber polarization dependent loss of less than 0.2 dB. The waveguide assembly 2 can also be a part of an optical device selected from the group consisting of an arrayed-waveguide wavelength multiplexer, an arrayed- waveguide chromatic dispersion compensator, a waveguide Bragg grating, a Mach-Zehnder interferometer, and an integrated optical microcavity resonator. The manufacturing process for a waveguide assembly that may be a part of any one of these types of devices will now be described. The manufacturing process will be described in the context of a 1x8 splitter device, but those of skill in the art will be able to ascertain how to apply these principles to other optical devices.

EXEMPLARY EMBODIMENT OF A WAVEGUIDE ASSEMBLY HAVING TWO

LOWER CLADDING LAYERS FOR LOW POLARIZATION-DEPENDENT LOSS

The manufacturing process for one exemplary embodiment having the wave guide structure shown in FIG. 1 formed in a 1x8 splitter device as laid out in FIG. 11 will now be described. The substrate 3 is silicon in this example. The first lower cladding layer 4 has a thickness of 3-20 μm, a refractive index as discussed above, and is deposited on the silicon substrate 3 using plasma enhanced chemical vapor deposition (PECVD) according to the following conditions:

Temperature: 300-400° C.

SiH₄ flow: 150-400 seem N₂O flow: 500-2000 seem

N₂ flow: 100-1000 seem

RF power: 50-200W

Pressure: 500-2000mTorr

The second lower cladding layer 5 has a thickness of 2-10 μm and a refractive index as described above. This layer is deposited with the following conditions:

Temperature: 300-400° C.

SiH₄ flow: 150-400 seem

N₂O flow: 500-2000 seem

N₂ flow: 100-2000 seem RF power: 50-200W

Pressure: 500-2000mTorr A high refractive index waveguide core layer 6, preferably of Ge-doped SiCh, has a thickness of 4-10 μm and is deposited on top of the second lower cladding layer 5. The refractive index for the core layer is 1.445 to 1.492. In one example, the index of the core layer is 1.4639. The waveguide core layer is fabricated using a PECVD technique according to the following conditions:

SiH₄: 150-400 seem,

GeH₄: 0.5-10 seem,

N₂O: 500-2000 seem,

N₂: 100-1000 seem, RF power: 50-200 W,

Pressure: 500-2000 mTorr,

Temperature: 300-400 ⁰C.

After deposition, the waveguide layers (two lower cladding layers and the core) are annealed at 1000-1400° C for 2-8 hours. After annealing, the waveguide core layer is coated with aluminum with a thickness in the range of 0.2- 1.0 μm by electron beam evaporation. It is also be possible to use other conventional techniques for coating the aluminum layer, such as sputtering or evaporation. A positive photoresist (e.g., Shipley

PRl 813) is coated on the aluminum layer, and the aluminum layer is patterned using a core pattern mask for 1x8 splitter devices by standard photolithography. A reactive ion etching process is then performed to etch the waveguide layer and form ridge waveguide cores in the shape of a 1x8 splitter device. The following conditions are used:

C₄Fs: 10-50 seem

Ch: 0.5-5 seem

RF power: 50-100 W ICP power: 1000-2000 W

Pressure: 3-10 mTorr

After the waveguide cores are formed, an upper cladding layer is provided over the waveguide ridges using borophosphosilicate glass (BPSG) with a refractive index of

1.4425-1.4895 and a thickness in the range of 4 to 30 μm (after reflow) using PECVD according to the following conditions:

SiH₄: 10-50sccm

B2H6: 0.1-10sccm PH3: 0.1-10sccm

N2: 100-lOOOsccm RF power: 50-200W Pressure: 1000-2000 mTorr Temperature: 300-400⁰C

After the BPSG layer was formed, the sample is heated and allowed to reflow at 900-1000⁰C for 2-10 hours.

EXEMPLARY EMBODIMENT OF A LOW PDL WAVEGUIDE ASSEMBLY WITH INTEGRAL ALIGNMENT FEATURES

Because a waveguide assembly having two lower cladding layers with the indices of refraction described herein reduces substrate coupling, it is possible to construct the waveguide assembly on a silicon substrate with an acceptably low amount of PDL. As a result, the features of silicon can be utilized to create alignment features on the substrate. Examples of waveguide assemblies with two lower cladding layers and alignment features will now be described.

One embodiment of a planar waveguide assembly 20 having integral alignment features 22 for positioning an optical fiber 24 according to the invention is illustrated in FIGS. 2-6. In the exemplary embodiment of FIGS. 2-6, the planar waveguide assembly 20 with integral alignment features 22 is made by coating a substrate 26 with an etch stop layer 28. An alignment feature pattern 30 is formed in the etch stop layer 28 for each waveguide assembly 20 on the substrate 26. The alignment feature pattern 30 is fabricated using photolithography and an etch process. After the alignment feature pattern 30 is fabricated in the etch stop layer 28, the layers of the waveguide structures 32 are grown on top of the substrate 26 and etch stop layer 28 with alignment feature pattern 30. The waveguide structures 32 include the two lower cladding layers 42 and 43, as well as the core structures 40 and upper cladding layer 50 described herein. The waveguide layers 32 are next removed by etching in areas where the alignment feature pattern 30 was previously fabricated to expose the pattern 30. Another etch is performed to create the precision alignment features 22 using the previously fabricated alignment feature pattern 30. The alignment features 22 are illustrated as V-grooves, but may have other cross- sectional profiles as well, including U-shaped, trapezoidal or rectangular grooves. Details of the method used to form the first exemplary embodiment are described in greater detail below.

Alignment Feature Patterning

Substrate 26, for example a silicon wafer (doped or undoped), is cleaned using conventional cleaning processes, and coated on one or both sides with an etch stop layer 28 using known deposition techniques. Etch stop layer 28 is formed from a material selected based upon its ability to endure required process temperatures and to withstand the final etching process used to form the alignment features as described below. For example, where the final etching process is a KOH etch, suitable materials for etch stop layer 28 include silicon nitride, gold, chrome-gold, nichrome, hafnium, hafnium oxide, holmium, holmium oxide, magnesium fluoride, magnesium oxide, tantalum oxide, vanadium, tungsten, zirconium, and zirconium oxide. The etch stop layer 28 is deposited on substrate 26 by known processes. For example, suitable techniques include, but are not limited to, thermal evaporation, low pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition (PECVD).

In the exemplary embodiment, the material used to form etch stop layer 28 is silicon nitride (SIsN₄), applied with a thickness in the range of 300-6000 A using a low pressure chemical vapor deposition (LPCVD) process according to the following conditions: NH₃: 100-500 seem, dichlorosilane (DCS): 50-500 seem, pressure: 200-400 mTorr, N₂: 500-300 seem, temperature: 700-1130° C.

A coating adhesion promoter such as hexamethyldisilazane (HMDS) is deposited on top of the etch stop layer 28, and a positive photoresist (e.g., Shipley PR1813) is next coated over the adhesion promoter. The adhesion promoter and photoresist may be applied, for example, by spin coating or other suitable known techniques. The construction is then baked at approximately 96° C. for approximately 30 minutes. The photoresist is next exposed using an alignment feature pattern mask aligned to the wafer, and then developed using conventional techniques. The etch stop layer 28 is etched to form the alignment feature pattern 30. Any suitable known etching technique may be used. In the exemplary embodiment, a dry etch technique is used. For example, a reactive ion etch (RIE) process, and specifically an inductive coupled plasma (ICP) RIE process, may be conducted according to the following conditions: C₄F₈: 10-50 seem, O₂: 0.5-5 seem, RF power: 50-100 W, ICP power: 1000-1800 W, Pressure: 4-10 mTorr.

After etching, the photoresist is stripped, leaving the etch stop layer 28 with the alignment feature pattern 30 on substrate 26, as shown in FIG. 3. For purposes of clarity, FIG. 2 shows only a single chip having an alignment feature pattern 30. In practice, a plurality of waveguide chips are formed from a single wafer, and during the alignment feature patterning process a plurality of alignment feature patterns 30 are formed on the wafer. The wafers are next prepared for fabrication of the optical waveguide structure 32.

Waveguide Fabrication

Prior to fabrication of the waveguides, the wafers and alignment feature pattern are preferably cleaned, such as with a pre-plasma clean. The waveguides are then fabricated using conventional techniques. In the first exemplary embodiment illustrated in FIGS. 2-6, the waveguide structure 32 comprises a high refractive index core 40 sandwiched between two lower cladding layers 42, 43 and an upper cladding layer 44. The construction of waveguides 32 used herein is exemplary only; the invention described and claimed herein is equally useful with any waveguide construction. In alternate embodiments, waveguide structure 32 has other known constructions and is fabricated using other known processes. In the first exemplary embodiment, as illustrated in FIG. 4, a low refractive index first cladding layer 42 (undoped SiC^ in the exemplary embodiment) having a thickness in the range of 3-20 μm and a refractive index in the range of 1.44-1.48, preferably 1.4570, is deposited over the patterned etch stop layer 28 using a plasma-enhanced chemical vapor deposition (PECVD) technique according to the following conditions: Temperature: 300-400⁰C. SiH₄ flow: 150-400 seem

N₂O flow: 500-2000sccm

N₂ flow: 100-1000 seem

RF power: 50-200W Pressure: 500-2000mTorr

Next, a second cladding layer 43 (undoped SiO₂ in the exemplary embodiment) having a thickness in the range of 2-10 μm and a refractive index in the range of 1.442-

1.482, preferably 1.4592, is deposited over the first lower cladding layer 42 using a plasma-enhanced chemical vapor deposition (PECVD) technique according to the following conditions:

Temperature: 300-400° C.

SiH₄ flow: 150-400 seem

N₂O flow: 500-2000sccm

N₂ flow: 100-1000 seem RF power: 50-200W

Pressure: 500-2000mTorr

In alternate embodiments, other low index materials such as magnesium fluoride may be used, as long as the materials are compatible with the subsequent process used to form the alignment grooves. For example, as described below, in one exemplary embodiment the alignment features 22 may be etched into a silicon wafer using an anisotropic etch, such as an anisotropic KOH etch. Some low index materials, such as diamond-like glass (DLG) and many polymers, are not compatible for use with a KOH etch. However, if an alternate to the exemplary KOH etch is used, such materials may be suitable for use.

A high refractive index waveguide core layer 40' (Ge-doped SiO₂ in the exemplary embodiment) having a thickness in the range of 4μm to 10 μm is next deposited over second lower cladding layer 43. The thickness of the waveguide core layer 40' will vary depending upon the particular application. Typically, for a single-mode waveguide, core layer 40' will have a thickness of approximately 8 μm. In the exemplary embodiment, the waveguide core layer 40' can be fabricated using a PECVD technique according to the following conditions: SiH₄: 150-400 seem, GeH₄: 0.5-10 seem, N₂O: 500-2000 seem, N₂: 100-1000 seem, RF power: 50-200 W, Pressure: 500-2000 mTorr, Temperature: 300-400 ⁰C.

After deposition, the waveguide core layer 40', first lower cladding layer 42, second lower cladding layer 43, and the core layer are annealed at 1000-1400° C. for 2-8 hours.

In alternate embodiments, other dopants such as phosphorous, titanium, zirconium, tantalum, or hafnium can be used in silica to create a high refractive index core. Alternatively, the core layer 40' can be fabricated from high index materials such as silicon, titania, zirconia, silicon oxynitride (SiON), or silicon nitride (Si₃N₄).

In other embodiments, the lower cladding layers 42 and 43, and waveguide core layer 40' can be deposited by processes other than the preferred PECVD process described above. For example, other suitable techniques include flame hydrolysis deposition (FHD), chemical vapor deposition (CVD) processes including atmosphere pressure chemical vapor deposition (APCVD) and low-pressure chemical vapor deposition (LPCVD), ion- exchange process, physical vapor deposition (PVD) processes such as sputtering, evaporation, electron beam evaporation, molecular beam epitaxy, and pulsed laser deposition, or sol-gel processes.

After annealing, the waveguide core layer 40' is coated with aluminum with a thickness in the range of 0.2 to 1 μm by conventional techniques, including sputtering, evaporation, and electron beam evaporation. A positive photoresist is coated on the aluminum layer, and the aluminum layer is patterned using a core pattern mask and standard photolithography techniques. The core pattern mask is aligned to the alignment feature pattern using standard mask alignment techniques. An etch process is then performed to etch the waveguide core layer 40' and form waveguide cores 40 (FIG. 5). In the exemplary embodiment, a dry etch is preferred. For example, an RIE etch may be conducted according to the following conditions: C₄F₈: 10-50 seem

O₂: 0.5-5 seem,

RF power: 50-100 W

ICP power: 1000-2000 W Pressure: 3-10 mTorr

After the waveguide cores 40 are formed, upper cladding layer 44 is provided over the waveguide ridges. The upper cladding layer 44 is provided using known suitable low refractive index materials and deposition processes as mentioned with respect to formation of the lower cladding layers 42 and 43, and waveguide core layer 40'. In the exemplary embodiment, a borophosphosilicate glass (BPSG) upper cladding layer 44 is grown to a thickness in the range of 4 to 30 μm (after reflow) over the waveguide cores 40, using

PECVD according to the following conditions.

SiH₄: 10-50 seem

B₂H₆: 0.1-10 seem PH₃: 0.1-10 seem

N₂O: 500-2000 seem

N₂: 100-1000 seem

RF power: 50-200 W

Pressure: 1000-2000 mTorr Temperature: 300-400° C.

The upper cladding layer has a refractive index that closely matches the second lower cladding layer, such as 1.4425 to 1.4895, and 1.4592 in one example. In an exemplary embodiment, the upper cladding layer has an index of refraction that is slightly higher than the index of refraction of the second lower cladding layer, for example 0.0005 higher. After the BPSG layer is formed, the assembly is heated and allowed to reflow at 800-

1200° C. for 2-10 hours. In an exemplary embodiment, the upper cladding layer has a thickness of 9.6 μm extending above the core, after being reflown.

Reveal Alignment Feature Pattern After the waveguides 32 are formed on top of the substrate 26 and previously fabricated alignment feature pattern 30, the upper cladding layer 44 is coated with 1 to 3 μm aluminum using conventional techniques, including sputtering, evaporation, and electron beam evaporation. To reveal the previously fabricated alignment feature pattern 30, a positive photoresist is coated on the aluminum layer and patterned with a mask using standard photolithography techniques. The mask is configured to allow the previously fabricated alignment feature pattern 30 to be revealed by etching the waveguide structure 32, as illustrated in FIG. 6. In the exemplary embodiment, a dry etch is used to remove the portion of the waveguides 32 over the alignment feature pattern 30. For example, an RIE etch may be performed according to the following conditions: C₄F₈: 10-50 seem, O2: 0.5-5 seem, RF power: 50-100 W

ICP power: 1000-2000 W Pressure: 3-10 mTorr

In a preferred embodiment, the RIE etching removes most of the waveguide layers 32, with any remaining waveguide layer material removed by a wet chemical etchant such as hydrofluoric acid (HF).

The remaining aluminum is stripped by etching. In the exemplary embodiment, a wet etch using FLiPOs/HNCVglacial acetic acid is conducted to remove the aluminum. The assembly is now ready for formation of the alignment features 22 by etching of the substrate 26.

Fabrication of Alignment Features

Referring again to FIG. 2, alignment features 22 are next formed in the substrate 26 by etching, using the previously fabricated alignment feature pattern 30 to define the position and size of the alignment features 22. The alignment features 22 are etched using conventional techniques, and the particular etch technique will depend upon the material used as the substrate 26 and upon the material used to form the etch stop layer 28. In the exemplary embodiment, where the substrate 26 is a silicon wafer and silicon nitride is used to form the etch stop layer 28, the alignment features 22 may be etched into the silicon wafer using an anisotropic etch, such as an anisotropic KOH etch. A suitable anisotropic etchant is a mixture of KOH and water (10-50 wt % KOH in water, preferably 35%) at temperatures between 25-100° C, preferably at 85° C. The etchant is preferably agitated to improve the uniformity of etching rates over relatively large areas of the substrate 26. The etch time depends on the width of the alignment features 22 defined by the alignment feature pattern 30.

A silicon wafer has different chemical properties on surfaces oriented differently with respect to the crystal structure of the wafer. Namely, in the (100), (HO), and (111) directions the wafer has an increasing atomic density. For an orientation-dependent etchant (e.g., 10-50 wt % KOH in water) the etch rate in the (111) direction is much smaller than the etch rate in the (100) and (110) directions, such that etching the silicon wafer in the (100) direction with the orientation-dependent etchant will result in V-shaped alignment features 22. Where the etching is not done to completion, the alignment features 22 will have a trapezoidal shape. The geometrical construction of the alignment features 22 formed by anisotropic etching is directly related to the etching window provided by the alignment feature pattern 30 in the etch stop layer 28.

The remaining exposed portions of etch stop layer 28 may optionally be removed by a suitable etching process. It may be desirable to remove exposed areas of etch stop layer 28 to ensure no "overhang" exists along alignment features 22. If not removed, overhanging portions of etch stop layer 28 may break off and fall into alignment features 22, where the debris may cause misalignment of the optical device placed in the alignment feature. The unexposed portions of etch stop layer 28 will remain under waveguides 32.

Assembly

After etching of the alignment features 22, and an optional etching step to remove the remaining etch-stop layer, the substrate is ready for additional processing to form individual waveguide chips having integral alignment features, as illustrated in FIG. 2. Prior to dicing the substrate (a wafer in the exemplary embodiments), a saw cut 50 is made at the junction of the waveguide cores 40 and alignment features 22 to remove any residual radius at the junction and provide a flat surface at the end of the waveguide cores 40 suitable for mating to an optical fiber or other optical device. This flat surface may be perpendicular to the wafer surface, or angled for reduction of optical reflections. Strips of waveguide chips (not shown) are then diced from the substrate 26, and the ends of the waveguide cores 40 may be given an additional optical polishing treatment. For example, a 10-120 second dip into a 1 :6 buffered HF solutions could be used, preferably 40s. The strips of waveguide chips are then further diced to separate individual planar wave-guide assemblies 20. The singulated assemblies are then ready for cleaning and assembly with optical fibers 24.

In a preferred embodiment, the waveguide assembly comprises a silicon substrate 26 having a plurality of V-shaped alignment features 22 formed therein. A silicon nitride etch stop layer 28 covers the substrate 26 between substrate 26 and waveguide structure 32. Waveguide structure 32 includes a plurality of waveguide cores 40 (each corresponding to an alignment feature 22) sandwiched between a lower cladding layer 43 and an upper cladding layer 44.

SECOND EXEMPLARY EMBODIMENT OF A LOW PDL WAVEGUIDE ASSEMBLY WITH INTEGRAL ALIGNMENT FEATURES

Another embodiment of a planar waveguide assembly 20a, having integral alignment features according to the invention is illustrated in FIGS. 7-9. In the second exemplary embodiment, the integral alignment features 22 are made using the waveguide material structures 32 themselves as the pattern for the alignment features 22. As compared to the first exemplary embodiment of FIGS. 2-6, the second exemplary embodiment eliminates the fabrication of alignment feature pattern 30 described above, thereby, reducing process steps. Waveguides 32 are directly deposited on the substrate 26 (a silicon wafer in the exemplary embodiment) and then etched to form a pattern 30a for the alignment features 22 formed in a latter etch step. The alignment features 22 are illustrated as V-grooves, but may have other cross-sectional profiles as well, including U- shaped or rectangular grooves. Details of the method used to form the second exemplary embodiment are described in greater detail below.

Waveguide Fabrication

Prior to fabrication of the waveguides, the substrate 26 is preferably cleaned using conventional techniques, such as a pre-plasma clean. The waveguides 32 are then fabricated using conventional techniques. In the second exemplary embodiment, as shown in FIG. 7, the waveguides 32 comprise a first lower cladding layer 42, a second lower cladding layer 43, a high refractive index core 40, and an upper cladding layer 44. The waveguides 32 may be fabricated using the same processes and conditions as described above with respect to the first exemplary embodiment. Alignment Feature Patterning

After the waveguides 32 are formed on the substrate 26, the upper cladding layer

44 is coated with 1 to 3 μm of aluminum using conventional techniques, including sputtering, evaporation, and electron beam evaporation. The aluminum is then patterned with an alignment feature pattern mask using standard photolithography techniques. As illustrated in FIG. 9, the waveguide layers 40, 42, 43, 44 are next etched down to the substrate 26, such that the remaining waveguide material forms a pattern 30a for the alignment features 22. In the exemplary embodiment, an RIE etch of the waveguide layers may be performed according to the following conditions: C₄F₈: 10-50 seem,

O₂: 0.5-5 seem,

RF power: 50-100 W

ICP power: 1000-2000 W

Pressure: 3-10 mTorr The remaining aluminum is stripped by etching. In the exemplary embodiment, a wet etch using FLiPOs/HNOs/glacial acetic acid is conducted to remove the aluminum. The assembly is now ready for formation of the alignment features 22 by etching of the substrate 26.

Fabrication of Alignment Features

Alignment features 22 are formed in the substrate 26 by etching, using the previously etched waveguide layers 40, 42, 43, 44 as an alignment feature pattern 30a to define the position and size of the alignment features 22. The alignment features 22 are etched using conventional techniques. In the exemplary embodiment, the alignment features 22 are etched into the silicon wafer substrate 26 using an anisotropic etch, such as an anisotropic KOH etch. A suitable anisotropic etchant is described above with respect to the first exemplary embodiment.

Assembly After etching of the alignment features 22, the substrate 26 is ready for additional processing to create the flat end facets of the waveguides 32, and to form individual waveguide chips having integral alignment features, as described above with respect to the first exemplary embodiment.

EXPERIMENTAL RESULTS AND SIMULATIONS FOR A LOW-PDL 1 X 8 PASSIVE SPLITTER DEVICE

A series of analytical and modeling experiments were performed to assess the optical properties of waveguides with a single lower cladding layer and waveguides with two lower cladding layers. Commercially available Beam Propagation Method (BPM) software was used to solve for the fundamental modes of each polarization for various waveguide structures for comparison of modal properties. Specifically, BeamPROP™ software was used as the BPM software, which is available from RSoft Design Group, Inc. of Ossining, New York.

Also, waveguide structures were fabricated having a straight waveguide configuration and a 1x8 splitter configuration, with both a single lower cladding layer and dual lower cladding layers, and their optical properties were tested. The fabrication process and the optical properties of these structures are described below.

Finally, a perturbation analytical approach was used to predict PDL for a waveguide with a single lower cladding layer in order to verify the experimental results and to demonstrate that much of the PDL was due to substrate coupling. The perturbation analytical approach was developed based upon W. Stutius and W. Streifer, Silicon Nitride Films on Silicon for Optical Waveguides, Applied Optics Vol. 16, p 3218 (1977) to characterize the effect that the substrate has on waveguide PDL in general and for a single lower clad waveguide structure.

First, the optical modeling assumptions and results will be described. Then, the results of the perturbation analytical approach will be described. Finally, two fabricated splitter example structures will be discussed, along with their tested optical properties.

Details of Waveguide Modeling Using BPM Software

Modeling was performed using the BPM software for three different straight waveguide configurations which will now be described. Cases A, C, and D have a dual layer lower cladding, as illustrated in FIG. 1. Case B has a single layer lower cladding as illustrated in FIG 10. For all cases the various waveguide design parameters are shown in Table 1 and an operation wavelength of 1550 nm was used. The RSoft BeamPROP™ software package was used to solve for the fundamental mode of each polarization in the waveguide. Cases A and B nominally correspond to the dual lower clad and single lower clad structures, respectively, that were fabricated. Cases C and D correspond to exemplary dual lower clad structures that are modeled for easier comparison to Case B, since other parameters than just lower clad design were varied from A to B. Since birefringence has a small effect on the portion of the optical mode near the substrate in these waveguide structures (as will be shown later in the discussion of the perturbation approach used to calculate PDL), these comparisons were done assuming zero birefringence.

Table 1. Description of Four Cases used for Optical Modeling

FIGS. 12 and 13 are graphs of the relative field amplitude in the waveguide plotted against the vertical position in the waveguide, where the substrate is at a vertical position of 0 μm. The relative field amplitude is the ratio of the field amplitude as a function of distance from the substrate in the lateral center of the waveguide, to the highest field amplitude in the waveguide. FIG. 13 graphs the same data as FIG. 12, but with a finer vertical scale, so that the differences in relative field amplitude near the interface 10 with the substrate 3 are more apparent. It is helpful to note that a relative field amplitude on the order of 0.001 or more at the substrate begins to cause significant polarization dependent loss (PDL) based on comparison of modeling and measurement results. These graphs illustrate the benefits of this invention by demonstrating that the dual lower cladding structures A, C and D have lower field amplitude at the substrate than the single lower cladding structure B.

First compare the fabricated single lower clad structure, Case B plotted with bold black line B in FIG. 13, with a comparison dual lower clad structure of the same index contrast between the core and the cladding immediately adjacent to the core, Case C plotted with dashed black line C in FIG. 13. The only difference between these two waveguide structure cases is the first 10 μm of the lower cladding from Case C has a lower index of refraction (by 0.0022) than Case B. The effect of this is a very large reduction in the field amplitude at the substrate for Case C. The field amplitude at the substrate for Case C is significantly lower than for Case B. Note that these plots show the TE results. Field amplitudes and effective indices for the TM mode (with zero birefringence) are typically identical to within <1% for these structures. The large PDL is primarily a result of the TE and TM modes interacting with the substrate differentially, through the lower clad-substrate interface boundary conditions, rather than from differential modal shapes. Different modal shapes, due to birefringence, will also affect the PDL, but we have shown this to be a lower order effect.

Next compare Case B with a second comparison dual lower clad structure, Case D plotted with dotted black line D in FIG. 13. The two differences are that Case D has the index of refraction in the lower 10 μm of the lower clad layer reduced by 0.0022 and the index of refraction of the core layer reduced by 0.001. Case D allows a significant amount of isolation from the substrate while at the same time reducing the index contrast of the waveguide from 0.0057 to 0.0047.

Case A, plotted with thin black line in FIG. 13 is very close in performance to Case D. This also demonstrates that for the dual lower clad design, the amplitude of the field near the substrate is likely much less dependent on actual waveguide parameters (core width, height, and upper clad thickness) which may be likely to vary from run to run.

Note that the benefit seen with a dual lower clad structure would be enhanced if the difference between the two lower cladding layer indices of refraction could be increased from the 0.0022 level used in the simulation.

Comparing Case A to Case B reveals that Case A achieves better isolation than Case B. Cases A and B are nominally the same as the two fabricated samples discussed below, Examples 1 and 2. The dual lower cladding Case A has greater isolation from the substrate (by approximately 2 μm), even though the index contrast for Case B has been increased by approximately 20% compared to Case A.

Details of Waveguide Modeling Using a Perturbation Analytical Approach

W. Stutius and W. Streifer, Silicon Nitride Films on Silicon for Optical Waveguides, Applied Optics Vol. 16, p 3218 (1977) describes an approach by which one can assess the effect that a high index substrate has on a guided mode by perturbing the solution for the case where the structure has an infinite lower cladding, so that the PDL for a waveguide with a certain thickness of the lower cladding layer can be determined This approach will be referred to as the Stutius model. This approach is useful because it gives an intuitive and correct picture of PDL and because it is very easy to determine the PDL based on the specific structure. This type of modeling was performed to verify that the experimental results were correct, and to demonstrate that much of the PDL was due to substrate coupling.

However, this model describes a 4-layer planar waveguide. Therefore, to use the model to quantitatively determine the PDL for a single lower clad channel waveguide with a finite upper clad thickness, the BPM Software was used to model the effects of limiting the upper clad thickness and channel width such that the model could be applied to our single lower clad structure. Furthermore, measurements of wafer bow were used to determine stress, from which channel waveguide birefringence was calculated. The effect of this birefringence was added, although the resulting change in PDL was small.

The perturbation model predicts that, due to the boundary conditions at the substrate, the TM mode loss will be higher than the TE mode loss for a structure with an insufficient amount of lower cladding. Furthermore, the model predicts that such a structure inherently has PDL, even in the absence of any other effect (birefringence, waveguide bending, etc). We have verified that the TM loss is higher in our single lower clad samples by using polarized input light and assessing the output beam profile after passing through a bulk polarizer.

FIG. 14 shows the PDL (TM mode insertion loss minus TE mode insertion loss) plotted vs lower clad thickness for four different scenarios using the Stutius model. The first scenario (calculated plot 60 which is a bold black line) nominally corresponds to Case B in Table 1, except with an infinite width channel and infinite thickness upper clad (n=3.5 was used for Si at 1550 nm for all modeling). Using BeamPROP and comparing the tails of the optical modes for the case of infinite width core and infinite thickness upper cladding to the actual Case B, it was determined that, near the substrate, the effective cladding thickness was reduced by 2.5 μm. (Note that approximately 2 μm of this effect is due to reducing the channel width from infinity to 6.9 μm) The second scenario (adjusted plot 62 which is a dotted black line) corresponded to our nominally designed structure (Case B) with no birefringence, after accounting for the 2.5 μm shift. Wafer bow measurements were used to calculate a stress in the fabricated waveguides of 150 MPa. This corresponded closely with 140 MPa, the stress calculated based on M.Huang, Thermal Stresses in Optical Waveguides, Optics Letters, Vol. 28, No. 23, p. 2327 (2003). Using the parameters from the fabricated structure described above as Case B. Then, various equations were used to calculate that the waveguides experience a birefringence of 0.0005. The equations used to calculate birefringence were found in Barlow and Payne, The Stress-Optic Effect in Optical Fibers, IEEE Journal of Quantum Electronics, Vol. QE-19, No. 5, p. 834 (May 1983) and T. Schreiber et al, Stress-Induced Birefringence in Large-Mode-Area Micro- Structured Optical Fibers, Optics Express, Vo. 13, No. 10, 3637 (May 1, 2005). The third scenario (birefringence adjusted plot 64 which is a thin black line) corresponds to the second scenario after adding in the effect of birefringence. As can be seen from Figure 12, birefringence has a relatively small effect on the PDL performance of this structure. The fourth scenario corresponded to a worst-case error assumption and is shown at worst case plot 66 on FIG. 12. To arrive at this set of data, the third scenario data was the starting point, and it was further assumed that the measurements of layer indices were off by the measurement accuracy (0.0005). In all cases (for lower cladding, core, and upper cladding), the error was made in the direction that would enhance substrate coupling. Finally, for comparison, also shown on FIG 14. is data measured from an array of fabricated straight waveguides having the same features as the optical modeling Case B, shown using plot 68 in Fig. 14). The dashes at the end of the line correspond to the range of PDL values measured for the array of straight waveguides.

The perturbation analysis demonstrates that the amount of PDL that was measured in the fabricated sample is reasonable. The actual data of plot 68 is close to the perturbation analysis data, for example, of plot 64 and plot 66. Furthermore, the perturbation analysis demonstrates that PDL is inherent in this type of waveguide structure on a high index substrate, regardless of waveguide design and birefringence, if a thin lower cladding is used (<20 μm for low index contrast). For this particular design, the PDL is on the order of the insertion loss, such that most of the loss is coming from the TM mode interacting with the substrate. As the lower cladding thickness is reduced further, the waveguide will experience both higher PDL and higher insertion loss as both TE and TM polarization will be more highly attenuated.

Details of Splitter Waveguide Fabrication and Testing

The observations of the modeling experiments that two lower cladding layers decreases PDL were verified by fabricating and testing two waveguides. Example 1 has two lower cladding layers, similar to the layer structure illustrated in FIG. 1, while Example 2 has one lower cladding layer, similar to the layer structure illustrated in FIG. 2.

The thicknesses and indices of refraction of Examples 1 and 2 are summarized in Table 2.

Table 2. Description of Examples 1 and 2

In Example 1, the first lower cladding layer had a thickness of 10 μm, a refractive index of 1.4570, and was deposited on a silicon wafer using plasma enhanced chemical vapor deposition (PECVD) according to the following conditions: Temperature: 350° C.

SiH₄ flow: 250 seem

N₂O flow: 1500 seem

N₂ flow: 600 seem

RF power: 140W Pressure: 1600mTorr

The second lower cladding layer had a refractive index of 1.4592, a thickness of

6.8 μm, and was deposited with the following conditions:

Temperature: 350° C.

SiH₄ flow: 310 seem N₂O flow: 1500 seem

N₂ flow: 600 seem

RF power: 11OW

Pressure: 1600mTorr A high refractive index (1.4639) waveguide core layer (Ge-doped SiCh) having a thickness of 7 μm was deposited on top of the second lower cladding layer. The resulting index contrast for this sample between the core and the second lower cladding layer was

0.0047. The waveguide core layer was fabricated using a PECVD technique according to the following conditions SiH₄: 250 seem

GeH₄: 1.4 seem

N₂O: 1500 seem

N₂: 600 seem

RF power: 110 W Pressure: 1600 mTorr

Temperature: 350 °C.

After deposition, the waveguide layers (two lower cladding layers and the core) were annealed at 1120° C for 4 hours. After annealing, the waveguide core layer was coated with aluminum with a thickness of 0.6 μm by electron beam evaporation. A positive photoresist (e.g., Shipley PRl 813) was coated on the aluminum layer, and the aluminum layer was patterned using a core pattern mask with 1x8 splitter devices on it by standard photolithography. A reactive ion etching process was then performed to etch the waveguide layer and form ridge waveguide cores in the shape of a 1x8 splitter device.

The following conditions were used: C₄Fs: 45 seem

RF power: 70 W

ICP power: 1600 W

Pressure: 6mTorr After the waveguide cores were formed, an upper cladding layer was provided over the waveguide ridges using borophosphosilicate glass (BPSG) with a refractive index of 1.4593 and a thickness of 9.6 μm (after reflow) using PECVD according to the following conditions:

SiH₄: 17sccm

B2H6: 3.5sccm PHs: l.δsccm

N2: όOOsccm

RF power: 130W

Pressure: 2000 mTorr Temperature: 350⁰C

After the BPSG layer was formed, the sample was heated and allowed to reflow at

1080⁰C for 4 hours.

Example 2, the comparison sample, was fabricated by the same techniques as

Example 1, but used a single lower cladding 17 μm thick with an index of refraction of 1.4592, a core layer index of refraction of 1.4649, and an upper cladding index of refraction of 1.4594. Thus, for Example 2, the index contrast between the core and the lower cladding layer was 0.0057.

Optical measurements were performed on the two 1x8 splitter device examples to measure the polarization dependence loss (PDL) and the optical loss. Table 3 shows the details of optical performance results for Example 1, tested using light of 1310 nm wavelength and 1550 nm wavelength. The insertion loss and PDL were measured at each of the eight ports of the 1x8 splitter devices.

Table 3. Optical Performance Data for Example 1

Table 4 shows the details of optical performance results for Example 2, tested using light of 1310 nm wavelength and 1550 nm wavelength. Table 4. Optical Performance Data for Example 2

The optical performance results for Example 2 are significantly worse than for Example 1. It is believed that the poor performance is due to substrate coupling loss, resulting in a large average PDL (3.0 dB) and insertion loss (11.6 dB) at 1550nm as shown in Table 4 above. That is, in Example 2 the waveguide mode fields are stronger at the surface of the silicon substrate, and experience polarization-dependent coupling into the high- index silicon, resulting in PDL. Essentially, a waveguide of this design and index contrast (core index minus clad index = 0.0057) is not adequately decoupled from the substrate for a single lower clad structure like Example 2. However, by reducing the index of refraction of the portion of the lower cladding nearest the substrate, as was done for Example 1, substrate coupling is reduced, even for a lower index contrast.

This is advantageous for allowing three different approaches to modifying conventional waveguides. First, one can reduce substrate coupling for a given lower clad thickness by replacing a single lower cladding with a two layer lower cladding of the same thickness. Second, one can reduce the total amount of lower clad thickness required for a given substrate coupling by replacing a single lower cladding with a two layer lower cladding of a reduced thickness. Third, one can potentially both reduce the thickness of the lower cladding layer and reduce substrate coupling. This results in a device with lower stress in the silicon, which in turn improves the selective etching characteristics of the Si and thereby improves the quality of alignment structures that can be made.

These achievements have implications for silicon integrated optical circuits since PDL is a significant issue for many of these devices. For example, one has more flexibility to simultaneously: match waveguide and fiber mode field diameters (typically requires lower waveguide index contrast); match the height of the fiber above the silicon surface (determined by V-groove design) with the height of the waveguide above the silicon surface (determined by layer thicknesses) for a passively aligned device; reduce substrate coupling and PDL; and reduce stress and improve V-groove quality by using thinner layers.

There are multiple advantages to a waveguide design with a lower overall thickness. One can reduce the time and materials costs of producing the waveguide structure. Second, the reduced thickness of the waveguide structures results in lower stress and stress-induced birefringence. The lower birefringence results in reduced polarization-dependent bend and y-branch splitting loss, further contributing to low device PDL. Finally, the reduced stress in the silicon substrate improves the quality of selective etching, yielding better quality v-grooves. In short, the approach permits lower manufacturing cost, improved optical performance, improved integration with silicon microstructures, and more design flexibility compared to other methods of addressing undesirable stress-related polarization effects.

Throughout the Detailed Description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as "top," "bottom," "front," "back," "leading," "trailing," etc., is used with reference to the orientation of the FIG(S). being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is not limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. For purposes of clarity and ease of understanding, the dimensions of some elements in the FIGS, are greatly exaggerated. Also, the FIGS, of the present application illustrate a single chip having an optical waveguide assembly according to the present invention. However, the processes described herein are typically carried out at the wafer level, with the processed wafer encompassing a plurality of similar optical waveguide assemblies which are subsequently diced into individual chips, as illustrated in the FIGS, and described below.

Although specific embodiments have been illustrated and described herein for purposes of description of the preferred embodiment, it will be appreciated by those of ordinary skill in the art that a wide variety of alternate and/or equivalent implementations calculated to achieve the same purposes may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. Those with skill in the mechanical, electrical, chemical, and optical arts will readily appreciate that the present invention may be implemented in a very wide variety of embodiments. This application is intended to cover any adaptations or variations of the preferred embodiments discussed herein. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.

The present invention should not be considered limited to the particular examples described above, but rather should be understood to cover all aspects of the invention as fairly set out in the attached claims. Various modifications, equivalent processes, as well as numerous structures to which the present invention may be applicable will be readily apparent to those of skill in the art to which the present invention is directed upon review of the present specification. The claims are intended to cover such modifications and devices.

The above specification provides a complete description of the structure and use of the invention. Since many of the embodiments of the invention can be made without parting from the spirit and scope of the invention, the invention resides in the claims.

Claims

WE CLAIM:

1. An optical waveguide assembly, comprising:

(a) a substrate,

(b) an optical waveguide positioned on the substrate, the waveguide comprising: (i) a core layer, wherein the substrate has a refractive index larger than that of the core layer; (ii) two or more lower cladding layers comprising:

(1) a first lower cladding layer positioned between the core layer and the substrate; (2) a second lower cladding layer positioned between the first lower cladding layer and the core; (iii) an upper cladding layer adjacent to and partially surrounding the core layer; and

(iv) wherein a refractive index for the first lower cladding layer is less than for the second lower cladding layer; and

(c) wherein the substrate is provided with an optical device alignment feature for aligning the waveguide with an optical fiber.

2. The optical waveguide assembly of claim 1, wherein the substrate is silicon.

3. The optical waveguide assembly of claim 1, wherein the optical waveguide is part of a passively-aligned optical splitter device, having polarization dependent loss of less than 0.2 dB.

4. The optical waveguide assembly of claim 1 wherein the second lower cladding layer is free of doping.

5. The optical waveguide assembly of claim 1 wherein the first and second lower cladding layers are free of doping.

6. The optical waveguide assembly of claim 1 wherein the refractive index for the second lower cladding layer is within 0.0005 of a refractive index for the upper cladding layer.

7. The optical waveguide assembly of claim 1 wherein the difference between the refractive index of the second lower cladding layer and the core layer is at least 0.003.

8. The optical waveguide assembly of claim 1, where the refractive index of the upper cladding layer is higher than the refractive index of the second lower cladding layer.

9. The optical waveguide assembly of claim 1 wherein the refractive index of the second lower cladding is more than 0.001 higher than the refractive index of the first lower cladding.

10. The optical waveguide assembly of claim 1 wherein the two or more lower cladding layers have refractive values increasing from the substrate to the core in steps of 0.001 or higher.

11. The optical waveguide assembly of claim 1, wherein the waveguide includes exactly two lower cladding layers, wherein the first lower cladding layer is adjacent to the substrate and the second lower cladding layer, wherein the second lower cladding layer is adjacent to the first lower cladding layer and the core layer.

12. A method of constructing an optical waveguide assembly comprising: (a) providing a substrate, wherein the substrate is provided with an alignment feature pattern that defines optical alignment features; and

(b) constructing an optical waveguide on the substrate, including the steps of: (i) forming a first lower cladding layer on the substrate; (ii) forming a second lower cladding layer on the first lower cladding layer; (iii) forming a core layer; and

(iv) forming an upper cladding layer adjacent to and partially surrounding the core layer; and (v) wherein a refractive index for the first lower cladding layer is less than for the second lower cladding layer; (vi) wherein the substrate has a refractive index larger than that of the core layer; and (c) fabricating optical alignment features from the alignment feature pattern on the substrate.

13. The method of claim 12, wherein the substrate is silicon.

14. The method of claim 12, further comprising coupling an optical fiber to the waveguide, wherein the optical fiber is aligned with the waveguide using the optical alignment features fabricated from the alignment feature pattern.

15. An optical waveguide assembly, comprising: (a) a substrate;

(b) an optical waveguide positioned on the substrate, the waveguide comprising: (i) a first undoped silica lower cladding layer adjacent to the substrate; (ii) a second undoped silica lower cladding layer adjacent to the first lower cladding layer; (v) a core layer;

(vi) an upper cladding layer adjacent to and partially surrounding the core layer; and (vii) wherein a refractive index for the first lower cladding layer is less than for the second lower cladding layer

16. The optical waveguide assembly of claim 15, wherein the substrate is silicon.

17. The optical waveguide assembly of claim 15, wherein the optical waveguide is part of an optical splitter device, having polarization dependent loss of less than 0.2 dB.

18. The optical waveguide assembly of claim 15 wherein the refractive index for the second lower cladding layer is within 0.0005 of a refractive index for the upper cladding layer.

19. The optical waveguide assembly of claim 15 wherein the core layer is adjacent to the second lower cladding layer.