WO2007130017A1

WO2007130017A1 - Bus loop power interface and method

Info

Publication number: WO2007130017A1
Application number: PCT/US2006/016439
Authority: WO
Inventors: Stig Lindemann
Original assignee: Micro Motion, Inc.
Priority date: 2006-04-28
Filing date: 2006-04-28
Publication date: 2007-11-15
Also published as: CA2650475C; KR101128960B1; JP5155302B2; RU2404527C2; BRPI0621757B1; JP2009535892A; AU2006343388A1; MX2008013260A; AR060681A1; CN101433037A; EP2027688A1; US8063694B2; BRPI0621757A2; RU2008146963A; KR20090009920A; US20090278519A1; HK1132393A1; AU2006343388B2; EP2027688B1; CN101433037B

Abstract

A bus loop power interface (100) is provided according to the invention. The bus loop power interface (100) comprises a voltage control module (110) receiving a loop voltage VLOOP and generating a predetermined supply voltage VSUPPLY, an impedance control module (120) coupled to the voltage control module (110), with the impedance control module (120) receiving a loop current ILOOP and generating a predetermined supply current ISUPPLY, and a feedback (115) coupled between the voltage control module (110) and the impedance control module (120). The feedback (115) provides a feedback signal to the voltage control module (110) that enables the voltage control module (110) to substantially maintain the predetermined supply voltage VSUPPLY.

Description

BUS LOOP POWER INTERFACE AND METHOD

Background of the Invention

1. Field of the Invention

The present invention relates to a bus loop power interface, and more particularly, to a bus loop power interface and method for an instrumentation bus.

2. Statement of the Problem Flowmeters are used to measure the mass flow rate, density, and other characteristics of flowing materials. The flowing materials can comprise liquids, gases, combined liquids and gases, solids suspended in liquids, and liquids including gases and suspended solids. For example, flowmeters are widely used in the well production and refining of petroleum and petroleum products. A flowmeter can be used to determine well production by measuring a flow rate {i.e., by measuring a mass flow through the flowmeter), and can even be used to determine the relative proportions of the gas and liquid components of a flow.

In many process control or industrial automation settings, a bus loop (or instrumentation bus) is used to connect to various devices, such as sensor devices and other instrument devices. The bus loop is commonly used to deliver electrical power to the various attached instrument or sensor devices. In addition, the bus loop is also commonly used to communicate data both to and from the sensor or instrument device. Therefore, the bus loop is connected to a master device that can provide regulated electrical power over the bus and that can perform communications over the bus. The master device can send commands and/or programming, data, calibrations and other settings, etc., to the sensor and instrument devices. The master device can also receive data from the sensor and instrument devices, including identification data, calibration data, measurement data, operational data, etc. FIG. 1 shows a two-wire bus loop 1 according to the prior art. The bus loop

1 can include a master device 2 that operates the bus loop 1 , multiple sensor or instrument devices 3-5, and terminators 6. The master device 2 can pass digital communication signals to external devices, such as to monitoring and control stations, for example. The master device 2 is connected to an electrical power source and provides electrical power over the two-wire bus loop 1. The master device 2 typically provides electrical power that is current limited, voltage limited, and power limited.

The bus loop 1 can comprise a FIELDBUS bus loop, for example. The term FIELDBUS refers to a two-wire instrumentation bus standard that is typically used to connect together multiple instruments and is further capable of being used to provide digital communications between instruments. Alternatively, the bus loop 1 can comprise other buses, such as PROFIBUS, HART, a 4-20 mA bus loop, etc.

FIG. 2 shows a prior art power regulation scheme for a prior art bus device 3 connected to the bus loop 1. The prior art bus device 3 includes voltage regulator 8 and a load 9 in series with the voltage regulator 8. The voltage regulator 8 maintains a constant voltage level to the load 9.

However, this prior art power regulation has drawbacks. The maximum electrical power (P) provided in this prior art arrangement comprises the output voltage of the series regulator (V) multiplied by the loop current (I). A loop interface that uses this kind of linear regulation has poor power transfer because the voltage parameter V in the available power equation (P = V X I) is essentially fixed. In addition, the bus voltage dips when the loop current increases, due to the relatively high loop impedance. One possible solution could be the use of a switch mode power supply

(SMPS). A SMPS is also referred to as a switched mode power supply or a switching power supply. A SMPS generates a time varying signal from the DC bus voltage, performs a voltage step-up conversion, and converts the resulting time- varying signal back to a DC voltage that can have a higher voltage level than the original DC bus voltage. As a result, the V term in the power equation can be increased.

However, the drawback of a SMPS device is that a SMPS device typically has a low input impedance characteristic. This is not compatible with a device powered from the bus loop 1 , where the loop impedance is kept high in order to enable communication signals to pass over the bus loop 1.

Summary of the Solution

A bus loop power interface is provided according to an embodiment of the invention. The bus loop power interface comprises a voltage control module receiving a loop voltage V_LOOP and generating a predetermined supply voltage V_SUPPLY, an impedance control module coupled to the voltage control module, with the impedance control module receiving a loop current IL_OOP and generating a predetermined supply current ISUPPLY, and a feedback coupled between the voltage control module and the impedance control module. The feedback provides a feedback signal to the voltage control module that enables the voltage control module to substantially maintain the predetermined supply voltage V_SUPPLY-

A bus loop power interface is provided according to an embodiment of the invention. The bus loop power interface comprises a switch mode power supply (SMPS) U₂ receiving a loop voltage V_LOOP and generating a predetermined supply voltage V_SUPPLY- The bus loop power interface further comprises a current measuring resistor R-i receiving a loop current IL_OOP, an op-amp U-i including input terminals across the current measuring resistor R₁, and a transistor Qi biased by the op-amp U-i. The transistor Q-) receives the loop current ILO_OP and generates a predetermined supply current ISUPPLY- The output of the op-amp Ui controls an impedance characteristic of the transistor Qi and controls the predetermined supply current ISUPPLY- The bus loop power interface further comprises a transistor Q₂ coupled to the SMPS U₂. The transistor Q₂ is biased by the loop voltage VLO_OP- The bus loop power interface further comprises a feedback resistor R₂ connected between the transistor Q₂ and ground. The feedback resistor R₂ receives a feedback current I_F from the transistor Q₂. A feedback voltage VFB across the feedback resistor R₂ is received by a feedback input FB of the SMPS U₂. The transistor Q₂ and the feedback resistor R₂ enable the SMPS U₂ to substantially maintain the predetermined supply voltage VSUPPLY-

A method of controlling electrical power in a bus loop power interface is provided according to an embodiment of the invention. The method comprises receiving electrical power from an instrumentation bus at a loop voltage VL_OOP and at a loop current I_LOOP, generating a predetermined supply voltage VSUPPLY from the loop voltage VLOOP, and generating a predetermined supply current I_SUPPLY, with the predetermined supply current ISUPPLY being related to a predetermined impedance characteristic of the bus loop power interface.

ASPECTS

In one aspect of the bus loop power interface, the predetermined supply current ISUPPLY is substantially fixed. In another aspect of the bus loop power interface, the predetermined supply current I_SUPPLY is varying.

In yet another aspect of the bus loop power interface, the impedance control module regulates electrical impedance in the bus loop power interface. In yet another aspect of the bus loop power interface, the impedance control module further comprises an impedance control line, with the impedance control line being configured to control the predetermined supply current I_SUPPLY and control an electrical impedance of the impedance control module.

In yet another aspect of the bus loop power interface, the bus loop power interface further comprises a pair of input terminals and a pair of output terminals, wherein the impedance control module receives the loop current ILOOP from the input terminals and wherein the voltage control module is connected to the pair of output terminals.

In yet another aspect of the bus loop power interface, the voltage control module further comprises a switch mode power supply (SMPS) U₂.

In yet another aspect of the bus loop power interface, the impedance control module further comprises a current measuring resistor Ri receiving the loop current ILO_OP, an op-amp Ui including input terminals across the current measuring resistor R-_I, and a transistor Q₁ biased by the op-amp Ui and receiving the loop current ILO_OP, with the output of the op-amp Ui controlling an impedance characteristic of the transistor Qi and controlling the predetermined supply current ISUPPLY- In yet another aspect of the bus loop power interface, the feedback - comprises a transistor Q₂ that is biased by the loop voltage VL_OOP and a feedback resistor R₂ connected between the transistor Q₂ and ground, with the feedback resistor R₂ receiving a feedback current I_F from the transistor Q₂, wherein a feedback voltage V_FB across the feedback resistor R₂ is received by a feedback input FB of the SMPS U₂.

In yet another aspect of the bus loop power interface, the SMPS U₂ comprises a voltage control module. In yet another aspect of the bus loop power interface, the current measuring resistor R₁, the op-amp U₁, and the transistor Q-i comprise an impedance control module.

In yet another aspect of the bus loop power interface, the transistor Q₂ and the feedback resistor R₂ comprise a feedback. In yet another aspect of the bus loop power interface, the current measuring resistor R-i, the op-amp Ui, and the transistor Q-i regulate electrical impedance in the bus loop power interface.

In yet another aspect of the bus loop power interface, the bus loop power interface further comprises an impedance control line configured to control the predetermined supply current ISUPPLY and control an electrical impedance of the impedance control module.

In yet another aspect of the bus loop power interface, the bus loop power interface further comprises an impedance control line coupled to the op-amp U₁, with the impedance control line being configured to control a bias voltage of the transistor Q₁.

In one aspect of the method, the method maximizes the electrical power available to the bus loop power interface.

In another aspect of the method, the method maximizes the electrical power available to the bus loop power interface while maintaining a substantially high impedance.

In yet another aspect of the method, the method maximizes the electrical power available to the bus loop power interface by maximizing the predetermined supply voltage V_SUPPLY and the predetermined supply current ISUPPLY- In yet another aspect of the method, the method further comprises regulating the predetermined supply current I_SUPPLY to generate a communication signal.

In yet another aspect of the method, the method further comprises receiving an impedance control input and generating the predetermined supply current 'SUPPLY based on the impedance control input. In yet another aspect of the method, the bus loop power interface comprises a voltage control module receiving a loop voltage VLOOP and generating a predetermined supply voltage VSUPPLY, an impedance control module coupled to the voltage control module, with the impedance control module receiving a loop current •LOOP and generating a predetermined supply current ISUPPLY, and a feedback coupled between the voltage control module and the impedance control module, with the feedback providing a feedback signal to the voltage control module that enables the voltage control module to substantially maintain the predetermined supply voltage VSUPPLY- In yet another aspect of the method, the predetermined supply current 'SUPPLY is substantially fixed.

In yet another aspect of the method, the predetermined supply current ISUPPLY is varying. In yet another aspect of the method, the impedance control module further comprises an impedance control line, with the impedance control line being configured to control the predetermined supply current ISUPPLY and control an electrical impedance of the impedance control module.

In yet another aspect of the method, the voltage control module further comprises a switch mode power supply (SMPS) U₂.

In yet another aspect of the method, the impedance control module further comprises a current measuring resistor Ri receiving the loop current IL_OOP_, an op- amp Ui including input terminals across the current measuring resistor Ri, and a transistor Qi biased by the op-amp U-i and receiving the loop current IL_OOP, with the output of the op-amp Ui controlling an impedance characteristic of the transistor Q₁ and controlling the predetermined supply current I_SUPPLY-

In yet another aspect of the method, the feedback further comprises a transistor Q₂ that is biased by the loop voltage VLOOP and a feedback resistor R₂ connected between the transistor Q₂ and ground, with the feedback resistor R₂ receiving a feedback current I_F from the transistor Q₂, wherein a feedback voltage VFB across the feedback resistor R₂ is received by a feedback input FB of the SMPS U₂.

Description of the Drawings

FIG. 1 shows a two-wire bus loop according to the prior art. FIG. 2 shows a prior art power regulation scheme for a prior art bus device connected to the bus loop.

FIG. 3 shows a bus loop power interface according to an embodiment of the invention.

FIG. 4 shows the bus loop power interface according to an embodiment of the invention.

Detailed Description of the Invention

FIGS. 3-4 and the following description depict specific examples to teach those skilled in the art how to make and use the best mode of the invention. For the purpose of teaching inventive principles, some conventional aspects have been simplified or omitted. Those skilled in the art will appreciate variations from these examples that fall within the scope of the invention. Those skilled in the art will appreciate that the features described below can be combined in various ways to form multiple variations of the invention. As a result, the invention is not limited to the specific examples described below, but only by the claims and their equivalents. FIG. 3 shows a bus loop power interface 100 according to an embodiment of the invention. The bus loop power interface 100 provides electrical power to a bus device attached to an instrument bus loop 1 (not shown). The bus loop power interface 100 can be the only device attached to the bus loop 1 or can be one bus instrument of many.

The bus device in one embodiment comprises a flow meter, such as a Coriolis flow meter or a vibrating densitometer, for example. However, other bus devices are contemplated and are within the scope of the description and claims. The bus loop power interface 100 includes a voltage control module 110, an impedance control module 120, and a feedback 115 coupled between the voltage control module 110 and the impedance control module 120. The bus loop power interface 100 includes a pair of input terminals 101 configured to be coupled to an bus loop 1 and a pair of output terminals 102 configured to be coupled to a sensor or instrument device (also not shown). The impedance control module 120 receives the loop current ILO_OP from the input terminals 101 and the voltage control module 110 is connected to the pair of output terminals 102. The bus loop power interface 100 receives a loop voltage VL_OOP from the bus and provides a predetermined supply voltage V_SUPPLY at the output terminals 102. In addition, the bus loop power interface 100 receives a loop current ILOOP from the bus and provides a predetermined supply current ISUPPLY at the output terminals 102.

The voltage control module 110 provides the predetermined supply voltage VSUPPLY from the loop voltage VL_OOP- The voltage control module 110 includes a switch mode power supply (SMPS) in some embodiments. The supply voltage VSUPPLY of the voltage control module 110 (and of the bus loop power interface 100) can comprise a direct current (DC) voltage in some embodiments. Alternatively, the supply voltage VSUPPLY can comprise a DC voltage including a superimposed digital communication signal. The supply voltage VSUPPLY can be less than the loop voltage VLO_OP- The supply voltage VSUPPLY can be greater than or equal to the loop voltage VLOOP- The supply voltage VSUPPLY can be at a fixed or varying level.

The impedance control module 120 regulates electrical impedance in the bus loop power interface 100. The impedance control module 120 provides the predetermined supply current ISUPPLY from the loop current Loop. The supply current I_SUPPLY is generated by varying the impedance provided by the impedance control module 120. As a result, the impedance of the bus loop power interface 100 can be maintained at a relatively high impedance level. In some embodiments, the predetermined supply current ISUPPLY produced by the impedance control module 120 is substantially fixed. Alternatively, in other embodiments the predetermined supply current ISUPPLY is varying, such as in embodiments where a varying current is used to generate a communication signal. In some embodiments, the impedance control module 120 includes an impedance control line 106. The impedance control line 106 is configured to control the predetermined supply current ISUPPLY and control the electrical impedance of the impedance control module 120.

The impedance control line 106 can be used in some embodiments to vary the supply current ISUPPLY, such as in embodiments that employ electrical current to generate a communication signal. Alternatively, in other embodiments the impedance control line 106 can comprise a fixed value that generates a substantially fixed impedance value (and therefore a substantially fixed supply current ISUPPLY)-

The feedback 115 generates feedback from the impedance control module 120 to the voltage control module 110. The feedback 115 provides a feedback signal to the voltage control module 110 that enables the voltage control module 110 to substantially maintain the predetermined supply voltage YSUPPLY- The feedback 115 can include a voltage level feedback, for example, wherein the voltage control module 110 uses the voltage level feedback in order to maintain the supply voltage VSUPPLY- In addition or alternatively, the feedback 115 can transfer an error current to the voltage control module 110, wherein the error current generates a feedback voltage that is used by the voltage control module 110 to maintain the supply voltage VSUPPLY (see FIG. 4 and the accompanying text). The feedback 115 is used to generate and maintain the regulated supply voltage VSUPPLY- In addition, the feedback 115 is also used to maximize electrical power output by the bus loop power interface 100 and therefore to achieve a maximum power transfer. The feedback 115 can ensure that the bus loop power interface 100 tracks a specific electrical power operating point. Even when the supply voltage VSUPPLY changes, the bus loop power interface 100 maximizes available power. A bus device coupled to the pair of input terminals 101 may have to operate at a specific supply current ISUPPLY that is determined by a process value. In such a case, the bus loop power interface 100 can still maximize the available power.

The bus loop power interface 100 can be used with any instrument bus, such as a FIELDBUS, a PROFIBUS, or a HART bus, for example. In these applications, a digital communication signal can be superimposed on the supplied electrical power. Alternatively, the bus loop power interface 100 can be used for a 4-20 milliamp (imA) bus loop, for example, wherein the electrical current output is modulated in order to generate a superimposed communication signal.

In some embodiments, the bus loop power interface 100 can be used in intrinsically safe (IS) environments. An IS environment can include vapors, gases, liquids, dust, etc., that presents a fire or explosion hazard. Therefore, an IS compliant bus is limited in available current and/or voltage that it can supply.

Advantageously, the bus loop power interface 100 can maximize delivered electrical power by maximizing both the available voltage and the available current. This is achieved while maintaining a high input impedance. The bus loop power interface 100 will substantially maintain the supply voltage V_SUPPLY over various current levels. The bus loop power interface 100 therefore facilitates communication while delivering maximum electrical power.

The bus loop power interface 100 implements a method of controlling electrical power according to an embodiment of the invention. The bus loop power interface 100 receives electrical power from an instrumentation bus at a loop voltage V_LOOP and at a loop current I L_OOP, generates a predetermined supply voltage VSUPPLY from the loop voltage V_LOOP, and generates a predetermined supply current ISUPPLY- The predetermined supply current ISUPPLY is related to a predetermined impedance characteristic of the bus loop power interface. The method maximizes the electrical power available to the bus loop power interface 100. The method maximizes the electrical power available to the bus loop power interface 100 while maintaining a substantially high impedance. The method maximizes the electrical power available to the bus loop power interface 100 by maximizing the predetermined supply voltage VSUPPLY and the predetermined supply current ISUPPLY. This is achieved even where the supply voltage VSUPPLY or the supply current I_SUPPLY may be constrained by a process value of the corresponding bus device.

The method can regulate the predetermined supply current ISUPPLY in order to generate a communication signal. The method can receive an impedance control input and can generate the predetermined supply current I_SUPPLY based on the impedance control input.

FIG. 4 shows the bus loop power interface 100 according to an embodiment of the invention. The bus loop power interface 100 in this embodiment includes the voltage control module 110, the impedance control module 120, and the feedback 115, as previously discussed.

The voltage control module 110 in this embodiment includes a switch mode power supply (SMPS) U₂, an inductor Li, capacitors Ci and C₂, a diode Di, and a Zener diode Z₁. As previously discussed, the predetermined supply voltage V_SUPPLY can comprise a DC voltage that is greater than, equal to, or less than the loop DC voltage V_LOOP- The capacitor, inductor, and diode components can be chosen to achieve the predetermined supply voltage VSUPPLY-

The impedance control module 120 in this embodiment includes an op-amp U₁, a resistor R-i, a voltage input VJ_seι, and a transistor Q₁. The op-amp Ui includes input terminals across the resistor R₁. The transistor Q-i is biased by the op-amp U₁. The resistor R₁ receives the loop current I_LOOP and the transistor Q₁ receives the loop current I_LOOP and generates a predetermined supply current 'SUPPLY- The op-amp U₁ is configured to measure the voltage across the resistor R₁, wherein the voltage is generated by an electrical current (i.e., IL_OOP) flowing through the resistor R₁. The measured current is used to control the gate (G) voltage of the transistor Q₁. Changing the voltage bias of the gate of the transistor Q₁ changes the source-to-drain impedance of the transistor Q₁. The voltage input V_l_Set in some embodiments comprises the impedance control input 106 of FIG. 3. The impedance control line 106 is coupled to the op- amp Ui and can therefore control a bias voltage of the transistor Q₁.

The transistor Qi can comprise a power transistor. In the embodiment shown, the transistor Q-i comprises a field effect transistor (FET) or a metal oxide semiconductor field effect transistor (MOSFET), such as a BSP 149 transistor, available from Infineon Technologies AG. However, any suitable transistor device can be used, and is within the scope of the description and claims.

The feedback 115 in this embodiment includes a transistor Q₂ and a feedback resistor R₂. The transistor Q₂ is biased by the loop voltage V_LOOP- The feedback resistor R₂ is connected between the transistor Q₂ and ground. The feedback resistor R₂ receives a feedback current I_F from the transistor Q₂. A feedback voltage V_FB across the feedback resistor R₂ is received by a feedback input FB of the SMPS U₂. When the actual supply voltage VSUPPLY increases to above a target supply voltage, the bias voltage at the base of the transistor Q₂ will increase. If the voltage across the base-collector junction of the transistor Q₂ (i.e., VB_C of Q2) becomes greater than 0.7 volts, then a positive feedback current IFB will flow through the feedback resistor R₂ to ground. This in turn causes the voltage across the feedback resistor R₂ to increase and consequently places a higher feedback voltage on the feedback (FB) pin of the SMPS U₂. As a result, the supply voltage V_SUPPLY will be reduced by the SMPS U₂. Conversely, if the actual supply voltage V_SUPPLY drops below the predetermined supply voltage, the feedback voltage at the FB pin will decrease and the SMPS U₂ will bring the actual supply voltage V_SUPPLY up to substantially the same level as the predetermined target supply voltage VSUPPLY- The transistor Q₂ and the feedback resistor R₂ enable the SMPS U₂ to substantially maintain the predetermined supply voltage VSUPPLY-

The invention can advantageously maximize available power at the pair of output terminals 102. The power can be represented as:

P = [VLOOP - (VBE of Q₂)] * LOOP ^* (E of U₂) (1 ) where (V_BE of Q₂) is the voltage across the base-emitter junction of transistor Q₂ and where (E of U₂) is the switching efficiency of the SMPS U₂. The term [VLOOP - (VBE of Q₂)] comprises the voltage V_Ci across the capacitor C₁, and is equivalent to the supply voltage VSUPPLY- In one embodiment, the transistor Q2 comprises a bipolar junction transistor (BJT), such as a BC 859 transistor, available from Fairchild Semiconductor Corporation. However, it should be understood that other transistors are contemplated and are within the scope of the description and claims. The bus loop power interface and method according to the invention can be employed according to any of the embodiments in order to provide several advantages, if desired. The invention provides a regulated electrical voltage. The invention provides a regulated electrical current. The invention provides a high input impedance. The invention provides an ability to control current. The invention provides an ability to control impedance. The invention provides a maximized electrical power.

Claims

CLAIMSWhat is claimed is:

1. A bus loop power interface (100), comprising: a voltage control module (110) receiving a loop voltage VL_OOP and generating a predetermined supply voltage V_SUPPLY; an impedance control module (120) coupled to the voltage control module (110), with the impedance control module (120) receiving a loop current IL_OOP and generating a predetermined supply current I_SUPPLY; and a feedback (115) coupled between the voltage control module (110) and the impedance control module (120), with the feedback (115) providing a feedback signal to the voltage control module (110) that enables the voltage control module (110) to substantially maintain the predetermined supply voltage V_SUPPLY-

2. The bus loop power interface (100) of claim 1 , wherein the predetermined supply current I_SUPPLY is substantially fixed.

3. The bus loop power interface (100) of claim 1 , wherein the predetermined supply current I_SUPPLY is varying.

4. The bus loop power interface (100) of claim 1 , with the impedance control module (120) regulating electrical impedance in the bus loop power interface (100).

5. The bus loop power interface (100) of claim 1 , with the impedance control module (120) further comprising an impedance control line (106), with the impedance control line (106) being configured to control the predetermined supply current ISUPPLY and control an electrical impedance of the impedance control module (120).

6. The bus loop power interface (100) of claim 1 , with the bus loop power interface (100) further comprising: a pair of input terminals (101); and a pair of output terminals (102); wherein the impedance control module (120) receives the loop current I_LOOP from the input terminals (101) and wherein the voltage control module (110) is connected to the pair of output terminals (102).

7. The bus loop power interface (100) of dai^'m 1 , with the voitage contro⁾ module (110) further comprising a switch mode power supply (SMPS) U2.

8. The bus loop power interface (100) of claim 1 , with the impedance control module (120) further comprising: a current measuring resistor Ri receiving the loop current L_OOP.^" an op-amp Ui including input terminals across the current measuring resistor

a transistor Qi biased by the op-amp Ui and receiving the loop current I_LO_OP, with the output of the op-amp Ui controlling an impedance characteristic of the transistor Qi and controlling the predetermined supply current ISUPPLY-

9. The bus loop power interface (100) of claim 7, with the feedback (115) comprising: a transistor Q₂ that is biased by the loop voltage V_LOOP! and a feedback resistor R₂ connected between the transistor Q2 and ground, with the feedback resistor R₂ receiving a feedback current IF from the transistor Q₂, wherein a feedback voltage V_FB across the feedback resistor R₂ is received by a feedback input FB of the SMPS U₂.

10. A bus loop power interface (100), comprising: a switch mode power supply (SMPS) U₂ receiving a loop voltage VL_OOP and generating a predetermined supply voltage V_SUPPLY; a current measuring resistor Ri receiving a loop current ILO_OP; an op-amp Ui including input terminals across the current measuring resistor

Ri; a transistor Q-i biased by the op-amp U₁, with the transistor Q₁ receiving the loop current ILOOP and generating a predetermined supply current

ISUPPLY, with the output of the op-amp Ui controlling an impedance characteristic of the transistor Q₁ and controlling the predetermined supply current ISUPPLY; a transistor Q₂ coupled to the SMPS U₂, with the transistor Q₂ being biased by the loop voltage VL_OOP! and a feedback resistor R₂ connected between the transistor Q₂ and ground, with the feedback resistor R₂ receiving a feedback current I_F from the transistor Q₂, wherein a feedback voltage VFB across the feedback resistor R₂ is received by a feedback input FB of the SMPS U₂ and wherein the transistor Q₂ and the feedback resistor R₂ enable the SMPS U₂ to substantially maintain the predetermined supply voltage

VSUPPLY-

11. The bus loop power interface (100) of claim 10, wherein the predetermined supply current I_SUPPLY is substantially fixed.

12. The bus loop power interface (100) of claim 10, wherein the predetermined supply current I_SUPPLY is varying.

13. The bus loop power interface (100) of claim 10, with the SMPS U₂ comprising a voltage control module (110).

14. The bus loop power interface (100) of claim 10, with the current measuring resistor R₁, the op-amp U₁, and the transistor Q₁ comprising an impedance control module (120).

15. The bus loop power interface (100) of claim 10, with the transistor Q₂ and the feedback resistor R₂ comprising a feedback (115).

16. The bus loop power interface (100) of claim 10, with the current measuring resistor R₁, the op-amp U₁, and the transistor Q₁ regulating electrical impedance in the bus loop power interface (100).

17. The bus loop power interface (100) of claim 10, further comprising an impedance control line (106) being configured to control the predetermined supply current I_SUPPLY and control an electrical impedance of the impedance control module (120).

18. The bus loop power interface (100) of claim 10, further comprising an impedance control line (106) coupled to the op-amp U₁, with the impedance control line (106) being configured to control a bias voltage of the transistor Q₁.

19. A method of controlling electrical power in a bus loop power interface, the method comprising: receiving electrical power from an instrumentation bus at a loop voltage

VLOOP and at a loop current Loop; generating a predetermined supply voltage V_SUPPLY from the loop voltage VLOOP; and generating a predetermined supply current ISUPPLY. with the predetermined supply current ISUPPLY being related to a predetermined impedance characteristic of the bus loop power interface.

20. The method of claim 19, with the method maximizing the electrical power available to the bus loop power interface.

21. The method of claim 19, with the method maximizing the electrical power available to the bus loop power interface while maintaining a substantially high impedance.

S

22. The method of claim 19, with the method maximizing the electrical power available to the bus loop power interface by maximizing the predetermined supply voltage V_SUPPLY and the predetermined supply current ISUPPLY-

23. The method of claim 19, further comprising regulating the predetermined supply current ISUPPLY to generate a communication signal.

24. The method of claim 19, further comprising: receiving an impedance control input; and generating the predetermined supply current I_SUPPLY based on the impedance control input.

25. The method of claim 19, with the bus loop power interface comprising: a voltage control module receiving a loop voltage V_LOOP and generating a predetermined supply voltage VSUPPLY; an impedance control module coupled to the voltage control module, with the impedance control module receiving a loop current IL_OOP and generating a predetermined supply current ISUPPLY; and a feedback coupled between the voltage control module and the impedance control module, with the feedback providing a feedback signal to the voltage control module that enables the voltage control module to substantially maintain the predetermined supply voltage V_SUPPLY-

26. The method of claim 25, wherein the predetermined supply current ISUPPLY is substantially fixed.

27. The method of claim 25, wherein the predetermined supply current ISUPPLY is varying.

28. The method of claim 25, with the impedance control module further comprising an impedance control line, with the impedance control line being configured to control the predetermined supply current ISUPPLY and control an electrical impedance of the impedance control module.

29. The method of claim 25, with the voltage control module further comprising a switch mode power supply (SMPS) U₂.

30. The method of claim 25, with the impedance control module further comprising: a current measuring resistor Ri receiving the loop current IL_OOP; an op-amp Ui including input terminals across the current measuring resistor R-_I ; and a transistor Q₁ biased by the op-amp U₁ and receiving the loop current ILO_OP, with the output of the op-amp Ui controlling an impedance characteristic of the transistor Q₁ and controlling the predetermined supply current ISUPPLY-

31. The method of claim 25, with the feedback further comprising: a transistor Q2 that is biased by the loop voltage VL_OOP; and a feedback resistor R₂ connected between the transistor Q₂ and ground, with the feedback resistor R₂ receiving a feedback current IF from the transistor Q₂, wherein a feedback voltage VFB across the feedback resistor R₂ is received by a feedback input FB of the SMPS U₂.