WO2007126820A1 - Récupération de phase à partir d'une horloge directe - Google Patents

Récupération de phase à partir d'une horloge directe Download PDF

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Publication number
WO2007126820A1
WO2007126820A1 PCT/US2007/007574 US2007007574W WO2007126820A1 WO 2007126820 A1 WO2007126820 A1 WO 2007126820A1 US 2007007574 W US2007007574 W US 2007007574W WO 2007126820 A1 WO2007126820 A1 WO 2007126820A1
Authority
WO
WIPO (PCT)
Prior art keywords
phase
clock signal
signal
received
clock
Prior art date
Application number
PCT/US2007/007574
Other languages
English (en)
Inventor
Emerson Fang
Gerald R. Talbot
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/627,578 external-priority patent/US20070230646A1/en
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Publication of WO2007126820A1 publication Critical patent/WO2007126820A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0025—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of clock signal

Definitions

  • This application is related to integrated circuits and more particularly to data communications links between integrated circuits.
  • a transmitting node compliant with an exemplary communications link may transmit, on a separate signal line, a reference clock for use in sampling commands, addresses or data (hereinafter, "data") by the receiving node.
  • data data
  • introduction of skew between received data and a received sample clock may compromise data recovery.
  • skew between the reference clock and the received data causes data transitions to approach the sampling point
  • the data transitions may fall within the clock setup time of a sampling device (e.g., flip flop or other state element) causing errors in data recovery.
  • a sampling device e.g., flip flop or other state element
  • the phase relationship between the received clock signal and the received data signal may not be stationary, which adds complexity to clock and data recovery operations. Accordingly, techniques for maintaining the integrity of data recovered by a receiving node on a data communications link are desired.
  • a clock phase recovery circuit in a communications receiver generates a sample clock signal for recovering data from a received data signal.
  • the sample clock signal is based at least in part on phase difference information associated with the received clock signal and the received data signal.
  • the received clock signal and received data signal are separately received by a receive interface circuit from a transmit interface circuit over a data communications link. Transmit clock jitter is effectively a common mode phase variation that is substantially rejected by the clock phase recovery circuit. Accordingly, the transmit clock jitter can be greater than otherwise allowable.
  • an apparatus in at least one embodiment of the invention, includes a circuit on a first integrated circuit coupled to receive, from a second integrated circuit, at least one received data signal and a received clock signal on separate communications paths.
  • the circuit is coupled to generate a sample clock signal and a sampled data signal.
  • the sampled data signal is the received data signal sampled by the sample clock signal.
  • the sample clock signal is determined at least in part according to a phase difference between the received clock signal and the received data signal.
  • the sample clock signal is determined at least in part according to a target sampling point of the received data signal.
  • a printed circuit board includes the first integrated circuit and the second integrated circuit.
  • a communications link couples the first integrated circuit to the second integrated circuit.
  • the communications link includes a plurality of unidirectional sets of signals.
  • at least one of the plurality of unidirectional sets of signals provides the received data signal and the received clock signal from the second integrated circuit to the first integrated circuit.
  • a method includes generating a sample clock signal on a first integrated circuit based at least in part on a phase difference between a received clock signal received from a second integrated circuit and a received data signal.
  • the received data signal is received from the second integrated circuit separately from the received clock signal.
  • the sample clock signal is based at least in part on a target sampling point of the received data signal.
  • the first and second integrated circuits are included on a printed circuit board and the first integrated circuit is coupled to the second integrated circuit by a communications link including a plurality of unidirectional sets of signals.
  • at least one of the plurality of unidirectional sets of signals provides the received data signal and the received clock signal from the second integrated circuit to the first integrated circuit.
  • FIG. 1 illustrates a block diagram of two integrated circuit devices coupled by a communications link consistent with one or more embodiments of the present invention.
  • FIG. 2 illustrates a block diagram of a portion of a communications link receive path on an integrated circuit device consistent with one or more embodiments of the present invention.
  • FIG.3 illustrates a block diagram of an exemplary clock phase recovery circuit consistent with one or more embodiments of the present invention.
  • FIG.4 illustrates a block diagram of an exemplary portion of the clock phase recovery circuit of FIG. 3 consistent with one or more embodiments of the present invention.
  • FIG. S illustrates a block diagram of an exemplary phase shifting circuit of a clock phase recovery circuit of FIG. 3 consistent with one or more embodiments of the present invention.
  • integrated circuit 102 communicates with integrated circuit 104 by an exemplary communications link including transmit interfaces 110, receive interfaces 114, and communications paths 106 and 108, which include respective, individual communications paths for clock signals (e.g., CLK[m:0]), control signals (e.g., CTL[m:0]), and data signals (e.g., n-bits of commands, addresses, or data, i.e.,
  • CAD[n:0] CAD[n:0]
  • Those individual communications paths may be single-ended or differential communications paths.
  • a bit-time is half a clock period in duration, i.e., two data bits (e.g., two CAD[n:0] bits or two CTL[m:0] bits) are transmitted on a corresponding communications path per clock cycle (e.g., a period of a respective one of CLK[m:0]).
  • the teachings herein may be adapted for bit-times having one clock period in duration (i.e., one data bit is transmitted on a corresponding communications path per clock cycle) or for other suitable bit-time durations.
  • Communications paths 106 and 108 are unidirectional, i.e., communications path 106 provides a path from integrated circuit 102 to integrated circuit 104 and communications path 108 provides a path to integrated circuit 102 from integrated circuit 104.
  • the exemplary, individual communications paths, CLK, CTL, and CAD[7:0] in integrated circuit 104 are received by individual receivers 202 and individual clock phase recovery circuits 204 in receive interface 114.
  • Receivers 202 may perform signal equalization, signal level shifting, noise reduction, or other appropriate signal processing functions.
  • Exemplary clock phase recovery circuits 204 individually receive a received clock signal (i.e., a forward clock signal, e.g., CLK) in addition to a respective, received data signal (e.g., CTL, CADO, CADl, ..., CAD7).
  • Clock phase recovery circuits 204 generate corresponding sample clocks (e.g., CTL-SCLK, CADO-SCLK, CAD1_SCLK,..., CAD7_SCLK) and provide the recovered data (e.g., CTL_R, CAD 1_R, CAD2_R,...CAD7_R) to other circuitry of receive interface 114.
  • An individual sample clock signal e.g., CAD4_SCLK
  • CLK dynamically delayed version of the received clock signal
  • corresponding received data signal e.g., CAD4
  • individual ones of clock phase recovery circuits 204 generate a sample clock signal for sampling the received data signal at the center of a data eye of the received data signal.
  • the phase difference between the received clock signal and the received data signal may be nonstationary, i.e., this phase difference varies during a period of communications link operation.
  • the delay applied to the received clock signal to generate the sample clock signal is adjusted during the period of communications link operation, accordingly.
  • the phase difference between the received clock signal and the received data signal at the receiver is less than a particular transport phase difference threshold value (e.g., 3 unit intervals or bit-times).
  • the phase difference between the sample clock signal and the received data signal may be greater than that particular transport phase difference threshold value.
  • Clock phase recovery circuit 204 recovers phase information from the received data signal (e.g., CAD4) and the received clock signal (e.g., CLK) to generate a sample clock signal (e.g., CAD4 SCLK) and a sampled data signal (CAD4 OUT).
  • Phase detector 305 includes two flip-flops (e.g., flip-flop 306 and flip-flop 308) that sample the received data signal based on the sample clock signal (e.g., CAD4_SCLK) 180° out of phase with each other.
  • Phase detector 305 provides two signals, a sampled received data signal and a signal providing phase information, e.g., CAD4_OUT and CAD4_PHI, respectively. Those signals are indicative of the phase difference between the received data signal and the received clock signal and are provided to state machine 314.
  • State machine circuit 314 generates digital control signals (e.g., PSEL, W;, and W 1+1 ) for adjusting the sample clock signal based on a comparison of CAD4_OUT to CAD4_PHI.
  • State machine circuit 314 controls a phase selection and phase interpolation circuit, (e.g., phase select and phase interpolator circuit 312) to generate the sample clock signal based at least in part on the received clock signal to generate the sample clock signal having a target phase relationship to the received data signal.
  • state machine 314 may generate control signals PSEL, Wj, and Wj +1 to apply an appropriate delay to the received clock signal to generate the sample clock signal to sample the received data signal in substantially the center of the data eye.
  • State machine 314 determines whether the phase of the sample clock signal is early or late with respect to the received data signal and issues a phase change request (e.g., appropriate values of PSEL, W ; , and W i+
  • digital circuitry included in state machine 314 is responsive to a clock derived from the sample clock signal. However, other clock signals of suitable frequency may be used by state machine 314.
  • phase select and phase interpolation circuit 312 receives n phase signals from delay-locked loop (DLL) 310 (e.g., ⁇ o, ⁇ ,..., ⁇ n - ⁇ ), which generates these signals based on the received clock signal.
  • DLL delay-locked loop
  • OLL 310 includes a delay line (e.g., delay line 323) that is configured to have a total delay equal to the period of the received clock signal.
  • Phase signals ⁇ o, ⁇ ⁇ o -i are spaced evenly to cover the 360° phase space of the received clock signal.
  • Phase signals ⁇ 0 , ⁇ ,- -, ⁇ n - ⁇ may include n/2 true phase signals (e.g., ⁇ 0 , ⁇ ,..., ⁇ n/2-1) and corresponding n/2 complementary phase signals (e.g., ⁇ 0B , ⁇ IB> - - > ⁇ (I ⁇ - ⁇ )B ) in implementations of clock phase recovery circuit 204 that include complementary delay lines in DLL 310, as discussed below.
  • Delay-locked loop 310 includes a feedback loop including phase detector 320, which may be any suitable phase detector that compares the received clock signal to a delayed version of the received clock signal to generate a phase difference signal. That phase difference is applied to delay line 323.
  • delay line 323 may be a voltage-controlled delay line.
  • the phase difference may be converted by phase-to-voltage circuit 322 into a voltage (e.g., P2V_OUT) that is applied to delay line 323 to adjust the delay of individual delay elements of the delay line to be equivalent and to have a duration that provides a cumulative delay of the delay line equal to the period of the received clock.
  • the delay line is a current-controlled delay line and the phase difference is converted by an appropriate circuit, accordingly.
  • Phase signals ⁇ 0 , ⁇ ,..., ⁇ n . ⁇ are versions of the received clock delayed by equivalent increments from next adjacent phase signals. Those phase signals may be generated by tapping off nodes of the delay line.
  • DLL 310 locks at the 180° point of the received clock signal, which is a half-rate clock signal (e.g., 2.6GHz at a 5.2Gbps data rate) to provide a total delay that is equal to one unit interval or bit-time (e.g., 192ps for a 2.6GHz received clock signal).
  • DLL 310 is a delay line that includes two complementary delay lines driven by complementary versions of the received clock signal.
  • the two complementary delay lines are tapped after each inverter of the delay lines to provide phase-adjacent signals separated by only one inverter delay, thereby improving phase resolution by a factor of two of the individual delay lines.
  • DLL 310 locks at the 180° point of the received clock signal, which is a half-rate clock signal (e.g., 2.6GHz at a 5.2Gbps data rate) to provide a delay of the individual ones of the complementary delay lines that is equal to one unit interval or bit-time (e.g., 192.3ps for a 2.6GHz received clock signal).
  • Delay-locked loop 310 outputs true taps from delay line 323 (e.g., ⁇ o, ⁇ ,.-., ⁇ s), which provide the first 180° of phase signals.
  • DLL 310 outputs complement taps (e.g., ⁇ OB> ⁇ I B .- - -, ⁇ SB ), which provide the second 180° of phase signals.
  • phase select and phase interpolator circuit 312 selects (e.g., according to PSEL) two adjacent phase signals that have phases with respect to the received clock signal that are nearest to the phase difference to be applied to the received clock signal for use in generating the sample clock signal.
  • Those two adjacent phase signals e.g., ⁇ ; and ⁇ i +l
  • phase interpolator circuit 326 receives two adjacent phase signals (e.g., ⁇ ; and ⁇ i +l ) and a phase interpolation of the two adjacent phase signals may be performed to generate an interpolated clock signal (e.g., PI_OUT) that is used to generate the sample clock signal.
  • Phase interpolator circuit 326 may be any suitable phase interpolation circuit. Phase interpolator designs are well known in the art and are typically dependent upon the particular DLL implementation and electrical parameters of the interface in which they operate.
  • phase interpolator 326 may not apply an equal weight to each of the adjacent phase signals. Rather, phase interpolator 326 may receive control signals (e.g., weighting signals W; and Wi +1 ) generated by state machine 314 that indicate an appropriate weighting function for application to phase signals ⁇ i and ⁇ i+ i to generate the signal having an intermediate phase, e.g., PI-OUT. Accordingly, PI-OUT is an interpolated version of ⁇ i and ⁇ i+ ⁇ having a particular phase relationship with the received data signal and is used to generate the sample clock signal, which may be phase aligned with the center of the data eye of the received data signal.
  • control signals e.g., weighting signals W; and Wi +1
  • weighting signals W 1 and W 1+ are four bits wide, i.e., each of the phase signals ⁇ i and ⁇ .
  • DLL 310 provides only the exemplary discrete values 0°, 30°, 60°, 90°, 120°, .... 330° phase shift signals.
  • the sample clock may be generated by an exclusive-or (e.g., as applied by XOR 318) of the intermediate phase signal (e.g., PI_OUT) with a phase-shifted version of the intermediate phase signal.
  • the intermediate phase signal is a phase-shifted version of the received clock signal and, thus, is a half-rate clock signal (e.g., 2.6GHz at a 5.2Gbps data rate).
  • a full-rate clock signal (e.g., 5.2GHz at a 5.2Gbps data rate) is generated by exclusive-oring the intermediate phase signal with a version of the intermediate phase signal that is phase shifted by 90°.
  • an appropriate phase shift (e.g., a 90° phase shift) is generated by including within exemplary phase shift circuit 316, an appropriate fraction of the number of delay elements in the delay line 323 of DLL 310.
  • the delay elements in phase shift circuit 316 are adjusted by the voltage generated by phase-to-voltage circuit 322 (e.g., P2V_OUT) that is applied to delay line 323 to adjust the delay of individual delay elements of delay line 323 to be equivalent and to have a duration that provides a total delay of the delay line equal to an appropriate period of the received clock signal.
  • P2V OUT is applied to phase shift circuit 316 to provide a 90° phase shift.
  • the signal generated by XOR 318 is the sample clock signal that is used to sample the received data signal.
  • One edge of the sample clock signal (i.e., rising or falling edge) is aligned with transitions in the received data signal.
  • the other edge of the sample clock signal is half a unit interval away from the data edge, which is generally in the center of the data eye and is used to sample the received data signal.
  • transmit clock jitter since transmit clock jitter is present in both the received data signal and the received clock signal, the transmit clock jitter is effectively a common mode phase variation that is rejected by clock phase recovery circuit 204. Accordingly, the transmit clock jitter can be greater than otherwise allowable (e.g., as compared to clock recovery techniques that do not use a forward clock).
  • clock phase recovery circuit 204 may recover from the low-power mode by maintaining or restoring the digital state from a previously known digital state. Upon resumption of data transmission, the clock phase recovery will be faster than if DLL 310 achieves lock from an initialization state.
  • transmit interface 110 may send a clock signal on CLK, but not send data on an individual one of CTL or CAD [n:0].
  • Delay-locked loop 310 may continue to operate and adjust the delay of the delay line 323. Upon resumption of data transmission, the clock phase recovery will be faster than if DLL 310 achieves lock from a previous state or from an initialization state.
  • circuits and physical structures are generally presumed, it is well recognized that in modem semiconductor design and fabrication, physical structures and circuits may be embodied in computer-readable descriptive form suitable for use in subsequent design, test or fabrication stages. Structures and functionality presented as discrete components in the exemplary configurations may be implemented as a combined structure or component.
  • the invention is contemplated to include circuits, systems of circuits, related methods, and computer-readable medium encodings of such circuits, systems, and methods, all as described herein, and as defined in the appended claims.
  • a computer-readable medium includes at least disk, tape, or other magnetic, optical, semiconductor (e.g., flash memory cards, ROM), or electronic medium.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

L'invention concerne un circuit de récupération de phase d'horloge (204) dans un récepteur de communications qui génère un signal d'horloge d'échantillonnage permettant de récupérer des données à partir d'un signal de données reçu. Le signal d'horloge d'échantillonnage est fondé au moins en partie sur des informations de différence de phase associées au signal d'horloge reçu et au signal de données reçu. Le signal d'horloge reçu et le signal de données reçu sont reçus séparément par un circuit interface de réception (114) depuis un circuit interface d'émission (110) sur une liaison de communications de données. La gigue de l'horloge d'émission représente effectivement une variation de phase de mode commun qui est sensiblement rejetée par le circuit de récupération de phase d'horloge. En conséquence, la gigue d'horloge d'émission peut être supérieure que ce qui est permis généralement.
PCT/US2007/007574 2006-04-24 2007-03-29 Récupération de phase à partir d'une horloge directe WO2007126820A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US74547906P 2006-04-24 2006-04-24
US60/745,479 2006-04-24
US11/627,578 US20070230646A1 (en) 2006-03-28 2007-01-26 Phase recovery from forward clock
US11/627,578 2007-01-26

Publications (1)

Publication Number Publication Date
WO2007126820A1 true WO2007126820A1 (fr) 2007-11-08

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ID=38462439

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/007574 WO2007126820A1 (fr) 2006-04-24 2007-03-29 Récupération de phase à partir d'une horloge directe

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TW (1) TW200818829A (fr)
WO (1) WO2007126820A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030002607A1 (en) * 2001-06-28 2003-01-02 Intel Corporation Clock recovery using clock phase interpolator
US20040046589A1 (en) * 2002-09-11 2004-03-11 Gauthier Claude R. Source synchronous interface using variable digital data delay lines
US20040202266A1 (en) * 2003-03-26 2004-10-14 Peter Gregorius Clock and data recovery unit
EP1601130A2 (fr) * 1997-02-06 2005-11-30 Rambus, Inc. Circuit à boucles à retard de phase servant à régler un retard d'horloge

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1601130A2 (fr) * 1997-02-06 2005-11-30 Rambus, Inc. Circuit à boucles à retard de phase servant à régler un retard d'horloge
US20030002607A1 (en) * 2001-06-28 2003-01-02 Intel Corporation Clock recovery using clock phase interpolator
US20040046589A1 (en) * 2002-09-11 2004-03-11 Gauthier Claude R. Source synchronous interface using variable digital data delay lines
US20040202266A1 (en) * 2003-03-26 2004-10-14 Peter Gregorius Clock and data recovery unit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
DALLY W J ET AL: "A second-order semidigital clock recovery circuit based on injection locking", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 38, no. 12, December 2003 (2003-12-01), pages 2101 - 2110, XP011104260, ISSN: 0018-9200 *
STEFANOS SIDIROPOULOS ET AL: "A Semidigital Dual Delay-Locked Loop", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 32, no. 11, November 1997 (1997-11-01), pages 1683 - 1692, XP011060611, ISSN: 0018-9200 *

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