WO2007123694A1 - Circuit de mémoire - Google Patents

Circuit de mémoire Download PDF

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Publication number
WO2007123694A1
WO2007123694A1 PCT/US2007/007930 US2007007930W WO2007123694A1 WO 2007123694 A1 WO2007123694 A1 WO 2007123694A1 US 2007007930 W US2007007930 W US 2007007930W WO 2007123694 A1 WO2007123694 A1 WO 2007123694A1
Authority
WO
WIPO (PCT)
Prior art keywords
state
feedback loop
inverter
data input
memory circuit
Prior art date
Application number
PCT/US2007/007930
Other languages
English (en)
Inventor
Robert P. Masleid
Original Assignee
Transmeta Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/395,017 external-priority patent/US8067970B2/en
Priority claimed from US11/396,114 external-priority patent/US7592836B1/en
Application filed by Transmeta Corporation filed Critical Transmeta Corporation
Publication of WO2007123694A1 publication Critical patent/WO2007123694A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization

Definitions

  • Embodiments here described relate to electronic circuits, in particular memory circuits.
  • This writing discloses at least multi-write memory circuit with a data input and a clock input.
  • a memory circuit is a type of circuit whose output depends on both the input to the circuit and the circuit's previous state (the state prior to the input).
  • a state-storage feedback loop included in a memory circuit allows a previous input, along with a current input, to affect the current output.
  • a memory circuit has a state-storage feedback loop coupled to a clock input and to a data input.
  • the data input is introduced into the feedback loop at multiple points, and propagated in parallel from those points to other points in the feedback loop.
  • a memory circuit may include a state-storage feedback loop coupled to a clock input and to a data input.
  • the data input is introduced into the feedback loop at multiple points, and propagated in parallel from those points to other points in the feedback loop.
  • Figures 1 and 2 illustrate embodiments of a memory circuit having a data input and a clock input and reduced minimum retention voltage in accordance with the present invention.
  • FIGS. 3 and 4 illustrate embodiments of a three-state inverter in accordance with the present invention.
  • Figures 5, 6, 7 and 8 illustrate embodiments of a multi-write memory circuit having a data input and a clock input and reduced minimum retention voltage in accordance with the present invention.
  • Figures 9 and 10 illustrate embodiments of a memory circuit having first and second data inputs and reduced minimum retention voltage in accordance with the present invention.
  • Figures 11, 12, 13, 14, 15 and 16 illustrate embodiments of a multi-write memory circuit having first and second data inputs and reduced minimum retention voltage in accordance with the present invention.
  • Figure 17 is a flowchart of a rhethod'for writing state to a memory circuit having a data input and a clock input and reduced minimum retention voltage in accordance with one embodiment of the present invention.
  • Figure 18 is a flowchart of a method for writing state to a memory circuit having first and second data inputs and reduced minimum retention voltage in accordance with one embodiment of the present invention.
  • Memory circuits in accordance with the present invention may be implemented as latches or flip-flops.
  • the memory circuits described herein are devices that store one bit.
  • FIG. 1 is a schematic of a memory circuit 10 having a data input D, a control input (e.g., clock input elk), and an output Q-bar in accordance with one embodiment of the present invention.
  • the state-storage feedback loop 14 of circuit 10 includes additional elements; the additional elements may be referred to collectively as a redundant element.
  • the feedback loop 14 includes inverters 16 and 17.
  • the inverters 16 and 17 affect the statistical and electrical behavior of (he circfuit, and in particular statistically lower the minimum retention voltage (Vmin) of the circuit 10, where Vmin is the minimum voltage at which state can be successfully retained by a memory circuit such as circuit 10.
  • Reducing Vmin may also reduce standby voltage, and consequently may reduce standby leakage and standby power. Furthermore, reducing Vmin may reduce the sensitivity of circuit 10 to transistor mismatch that can occur during fabrication. Also, in comparison to a conventional memory circuit, circuit 10 advantageously has a greater static noise margin (SNM).
  • SNM static noise margin
  • Figure 2 is a schematic of a memory circuit 20 having a data input D, a clock input elk, and an output Q-bar in accordance with another embodiment of the present invention.
  • the state-storage feedback loop 27 of circuit 20 includes additional elements. Specifically, in addition to inverter 21 and three-state inverter 26, the feedback loop 27 includes inverters 21 , 22, 23 and 24. The extended length of feedback loop 27 relative to feedback loop 14 can enhance the advantages mentioned above.
  • FIG. 3 is a schematic of an embodiment of a three-state inverter 30 in accordance with the present invention.
  • Three-state inverter 30 includes multiple p- type devices and multiple n-type devices (transistors). The p-type devices are configured to pull the output high (when appropriate) and the n-type devices are configured to pull the output low. Consequently, the drive capability of three-state inverter 30 is less than the drive capability of a conventional inverter.
  • three-state inverter 30 includes two p-type devices 32 and 33, and two n-type devices 34 and 35.
  • the gates of devices 32 and 35 are coupled to the input.
  • the gate of device 33 is coupled to the output of an inverter 31 , which receives an enable signal, and the gate of device 34 is also coupled to the enable input.
  • the enable signal when the enable signal is high, then the output is driven.
  • FIG. 4 is a schematic of another embodiment of a three-state inverter 40 in accordance with the present invention.
  • three-state inverter 40 includes two p-type devices 42 and 43, and two n-type devices 44 and 45.
  • the gates of devices 42 and 45 are coupled to the input.
  • the gate of device 44 is coupled to the output of an inverter 41 , which receives a disable signal, and the gate of device 43 is also coupled to the disable input.
  • the disable signal when the disable signal is low, then the output is driven.
  • Figure 5 is a schematic of a multi-write memory circuit 50 having a data input D, a clock input elk, and an output Q-bar.
  • the state-storage feedback loop 51 of circuit 50 includes an inverter 52, a three-state inverter 53, an inverter 54 and a three-state inverter 55, coupled in series.
  • the inverter 54 and the three-state inverter 55 constitute a redundant element that reduces the minimum retention voltage of circuit 50.
  • Circuit 50 may be referred to as a multi-write quad Vmin latch.
  • the three-state inverters 53 and 55 each have a clock input that, in the embodiment of Figure 5, provides a disable signal to the three-state inverters 53 and 55.
  • a data input of the three-state inverter 53 is coupled to an output of the inverter 52, and a data input of the three-state inverter 55 is coupled to an output of the inverter 54.
  • the three-state inverters 53 and 55 buffer the state received from the inverters 52 and 54, respectively, subject to the state of a clock signal.
  • a three-state inverter 56 is coupled between the data input D and inverter 54, and a three-state inverter 57 is coupled between the data input D and inverter 52.
  • the three-state inverters 56 and 57 each have a clock input that, in the embodiment of Figure 5, provides an enable signal to the three- state inverters 56 and 57.
  • the data input signal D is sensed in parallel by both the inverter 52 and the inverter 54. That is, according to the present embodiment of the present invention, the data input D is written (or driven or loaded) in parallel into feedback loop 51 at multiple locations, labeled A and B, instead of in just one location. An update of the remainder of feedback loop 51 proceeds in parallel from each of the write locations A and B.
  • the feedback loop 14 of circuit 10 ( Figure 1 ) is similar to the feedback loop
  • a state- storage feedback loop of a reduced Vmin memory circuit can be updated in less time.
  • the time e.g., hold time, setup time, or some other mea'sure
  • the time e.g., hold time, setup time, or some other mea'sure
  • Figures 6, 7 and 8 are schematics of other embodiments of a multi-write memory circuit having a data input and a clock input and reduced minimum retention voltage in accordance with the present invention.
  • the state- storage feedback loop 61 of memory circuit 60 includes an inverter 62, a three-state inverter 63, an inverter 64, a three-state inverter 65, an inverter 66 and a three-state inverter 67, coupled in series.
  • the inverter 64, three-state inverter 65, inverter 66 and three-state inverter 67 constitute a redundant element that reduces the minimum retention voltage of circuit 60.
  • Circuit 60 may be referred to as a multi- write hex Vmin latch.
  • the three-state inverters 63, 65 and 67 each have a clock input that, in the embodiment of Figure 6, provides a disable signal to the three-state inverters 63, 65 and 67.
  • a data input of the three-state inverter 63 is coupled to an output of the inverter 62
  • a data input of the three-state inverter 65 is coupled to an output of the inverter 64
  • a data input of the three-state inverter 67 is coupled to an output of the inverter 66.
  • the three-state inverters 63, 65 and 67 buffer the state received from the inverters 62, 64 and 66, respectively, subject to the state of a clock signal.
  • a three-state inverter 68 is coupled between the data input D and inverter 64, a three-state inverter 69 is coupled between the data input D and inverter 62, and a three-state inverter 601 is coupled between the data input D and inverter 66.
  • the three-state inverters 68, 69 and 601 each have a clock input that, in the embodiment of Figure 6, provides an enable signal to the three- state inverters 68, 69 and 601.
  • the data input D is written in parallel into feedback loop 61 at multiple locations, labeled A, B and C, instead of in just one location.
  • An update of the remainder of feedback loop 61 proceeds in parallel from each of the write locations A, B and C.
  • feedback loop 61 is updated in two inversions, despite the extended length of feedback loop 61 relative to feedback loop 51.
  • the state-storage feedback loop 81 of memory circuit 80 includes an inverter 82, a three-state inverter 83, an inverter 84, a three-state inverter 85, an inverter 86 and a three-state inverter 87, coupled in series.
  • the inverter 84, three- state inverter 85, inverter 86 and three-state inverter 87 constitute a redundant element that reduces the minimum retention voltage of circuit 80.
  • Circuit 80 may be referred to as a multi-write series hex Vmin latch.
  • the three-state inverters 83, 85 and 87 each have a clock input that, in the embodiment of Figure 7, provides a disable signal to the three-state inverters 83, 85 and 87.
  • a data input of the three-state inverter 83 is coupled to an output of the inverter 82
  • a data input of the three-state inverter 85 is coupled to an output of the inverter 84
  • a data input of the three-state inverter 87 is coupled to an output of the inverter 86.
  • the three-state inverters 83, 85 and 87 buffer the state received from the inverters 82, 84 and 86, respectively, subject to the state of a clock signal.
  • a three-state inverter 88 is coupled between the data input D and inverter 84, a three-state inverter 89 is coupled between the data input D and inverter 82, and a three-state "inverter 801 is coupled between the data input D and inverter 86.
  • the three-state inverters 88, 89 and 801 each have a clock input that, in the embodiment of Figure 7, provides an enable signal to the three- state inverters 88, 89 and 801.
  • the data input D is written in parallel into feedback loop 81 at multiple locations, labeled A, B and C, instead of in just one location.
  • An update of the remainder of feedback loop 81 proceeds in parallel from each of the write locations A, B and C.
  • feedback loop 81 is updated in two inversions, despite the extended length of feedback loop 81 relative to some of those examples.
  • the state-storage feedback loop 101 of memory circuit 100 includes an inverter 102, a three-state inverter 103, an inverter 104 and a three- state inverter 105, coupled in series.
  • the inverter 104 and three-state inverter 105 constitute a redundant element that reduces the minimum retention voltage of circuit 100.
  • Circuit 100 may be referred to as a multi-write series-inversion Vmin latch.
  • the three-state inverters 103 and 105 each have a clock input that, in the embodiment of Figure 8, provides a disable signal to the three-state inverters 103 and 105.
  • a data input of the three-state inverter 103 is coupled to an output of the inverter 102, and a data input of the three-state inverter 105 is coupled to an output of the inverter 104.
  • the three-state inverters 103 and 105 buffer the state received from the inverters 102 and 104, respectively, subject to the state of a clock signal.
  • a three-state inverter 106 is coupled between the data input D and inverter 102, and a three-state inverter 107 is coupled between the data input D and inverter 104.
  • the three-state inverters 106 and 107 each have a clock input that, in the embodiment of Figure 8, provides an enable signal to the three-state inverters 106 and 107.
  • the data input D is written in parallel into feedback loop 101 at multiple locations, labeled A and B, instead of in just one location.
  • An update of the remainder of feedback loop 61 proceeds in parallel from each of the write locations A and B.
  • feedback loop 101 is updated in two inversions.
  • Embodiments in accordance with the present invention are not limited to the examples described by Figures 5-8 above.
  • embodiments in accordance with the present invention introduce a data input into multiple points on a state- storage feedback loop. Accordingly, a feedback loop of arbitrary length can be updated in as few as two inversions, depending on the number of write locations.
  • the feedback loop includes an even number of circuit elements (e.g., inverters and three-state inverters) coupled in series. In one such embodiment, the feedback loop includes a same number of inverters and three- state inverters coupled alternately in series.
  • feedback loop 51 includes, in order, inverter 52, three-state inverter 53, inverter 54 and three-state inverter 55. The data input is introduced into feedback loop 51 at the inputs of the inverters 52 and 54, which alternate with three-state inverters 53 and 55 in feedback loop 51 , and the three-state inverters 53 and 55 buffer the state output by the inverters 52 and 54, subject to the clock signal elk.
  • the state-storage feedback loop can be viewed as having a number of stages where, in one embodiment, each stage includes a first element (e.g., an inverter) and a second element (e.g., a three-state inverter) coupled in series. In one such embodiment, each stage has a clock input and a data input, where a state on the data input is written in parallel into each of the stages.
  • first element e.g., an inverter
  • second element e.g., a three-state inverter
  • the multi-write reduced Vmin circuits of Figures 5-8 can be used in combination with the reduced Vmin circuits of Figures 1-2. Because a multi-write Vmin circuit may have larger data and clock input capacitances than a reduced Vmin circuit, and thus may slightly increase power dissipation within the feedback loop, it may be appropriate to use multi-write reduced Vmin circuits in critical paths (for speed) and reduced Vmin circuits in non-critical paths (to conserve power).
  • Figure 9 is a schematic of a memory circuit 110 having a first data input set- bar, a second data input reset-bar, a first output Q, and a second output Q-bar in accordance with one embodiment of the present invention.
  • the state-storage feedback loop 111 of circuit 110 includes additional elements (which may be referred to collectively as a redundant element).
  • the feedback loop 111 includes inverters 114 and 115.
  • the inverters 114 and 115 affect the statistical and electrical behavior of the circuit, and in particular statistically lower the Vmin of the circuit 110.
  • reducing Vmin may also reduce standby voltage, and consequently may reduce standby leakage and standby power.
  • reducing Vmin may reduce the sensitivity of circuit 110 to transistor mismatch that can occur during fabrication.
  • circuit 110 advantageously has a greater SNM.
  • Figure 10 is a schematic of a memory circuit 120 having a first data input set- bar, a second data input reset-bar, a first output Q, and a second output Q-bar in accordance with another embodiment of the present invention.
  • the state-storage feedback loop 121 of circuit 120 includes additional elements. Specifically, in addition to NAND gates 122 and 123, the feedback loop 121 includes inverters 124, 125, 126 and 126. The extended length of feedback loop 121 relative to feedback loop 111 can enhance the advantages mentioned above.
  • Figure 11 is a schematic of a multi-write memory circuit 130 having a first data input set-bar, a second data input reset-bar, a first output Q, and a second output Q-bar in accordance with another embodiment of the present invention.
  • Circuit 130 may be referred to as a multi-write reduced Vmin set-reset latch.
  • the state-storage feedback loop 131 of circuit 130 includes NAND gates 132, 133, 134 and.135, coupled in series.
  • the NAND gates 134 and 135 constitute a redundant element that reduces the minimum retention voltage of circuit 130.
  • the data input signal set-bar is sensed in parallel by both NAND gate 133 and NAND gate 135, and the data input signal reset-bar is sensed in parallel by both NAND gate 132 and NAND gate 134. That is, according to the present embodiment of the present invention, the set-bar signal is written in parallel into feedback loop 131 at multiple locations, labeled A and B, instead of in just one location, and the reset-bar signal is written in parallel into feedback loop 131 at multiple locations, labeled C and D, instead of in just one location. Signals proceed in parallel through feedback loop 131 from each of the write locations A, B, C and D.
  • the time needed to update feedback loop 131 is less than the propagation time around a conventional feedback loop (that is, a feedback loop having only a single write location).
  • Feedback loop 131 is updated in two inversions; if there was only a single write location, then it would take four inversions to update the feedback loop.
  • a state- storage feedback loop of a reduced Vmin memory circuit is updated in less time than the propagation time around the feedback loop.
  • the time e.g., hold time, setup time, or some other measure
  • the time needed to secure a new state in the memory circuit is reduced, in this respect improving the performance of reduced Vmin memory circuits.
  • Figures 12, 13, 14, 15 and 16 are schematics of other embodiments of a multi-write memory circuit having first and second data inputs and reduced minimum retention voltage in accordance with the present invention.
  • the state-storage feedback loop 141 of circuit 140 includes an inverter 142, an OR- AND invert (OAI) stage that includes OR gate 143 and NAND gate 144, an inverter 145, and another OAI stage that includes OR gate 146 and NAND gate 147, coupled in series.
  • the inverter 145, the OR gate 146 and the NAND gate 147 constitute a redundant element that'reduces the minimum retention voltage of circuit 140.
  • Circuit 140 may be referred to as a quad inversion OAI multi-write Vmin set-reset latch.
  • the data input signal set-bar is sensed in parallel by both NAND gate 144 and NAND gate 147, and the data input signal reset is sensed in parallel by both OR gate 143 and OR gate 146. That is, according to the present embodiment of the present invention, the set-bar signal is written in parallel into feedback loop 141 at multiple locations, labeled A and B, instead of in just one location, and the reset signal is written in parallel into feedback loop 141 at multiple locations, labeled C and D, instead of in just one location. Signals proceed in parallel through feedback loop 141 from each of the write locations A, B, C and D. Thus, feedback loop 141 is updated in two inversions, despite the presence of the redundant element.
  • the state-storage feedback loop 151 of circuit 150 includes an inverter 152, an AND-OR invert (AOI) stage that includes AND gate 153 and NOR gate 154, an inverter 155, and another AOI stage that includes AND gate 156 and NOR gate 157, coupled in series.
  • the inverter 155, the AND gate 156 and the NOR gate 157 constitute a redundant element that reduces the minimum retention voltage of circuit 150.
  • Circuit 150 may be referred to as a quad inversion AOI multi- write Vmin set-reset latch.
  • the data input signal set-bar is sensed in parallel by both AND gate 153 and AND gate 156, and the data input signal reset is sensed in parallel by both NOR gate 154 and NOR gate 157. That is, according to the present embodiment of the present invention, the set-bar signal is written in parallel into feedback loop 151 at multiple locations, labeled A and B, instead of in just one location, and the reset signal is written in parallel into feedback loop 151 at multiple locations, labeled C and D, instead of in just one location. Signals proceed in parallel through feedback loop 151 from each of the write locations A, B 1 C and D. Thus, feedback loop 151 is updated in two inversions, despite the presence of the redundant element.
  • the state-storage feedback loop 161 of circuit 160 includes NAND gates 162, 163, 164, 165, 166 and 167, coupled in series.
  • the NAND gates 164, 165, 166 and 167 constitute a redundant element that reduces the minimum retention voltage of circuit 160.
  • Circuit 160 may be referred to as a hex NAND multi-write Vmin set-reset latch.
  • the data input signal set-bar is sensed in parallel by NAND gates 163, 165 and 167, and the data input signal reset-bar is sensed in parallel by NAND gates 162, 164 and 166. That is, according to the present embodiment of the present invention, the set-bar signal is written in parallel into feedback loop 161 at multiple locations, labeled A, B and C, instead of in just one location, and the reset-bar signal is written in parallel into feedback loop 161 at multiple locations, labeled D, E and F, instead of in just one location. Signals proceed in parallel through feedback loop 161 from each of the write locations A, B, C, D, E and F. Thus, feedback loop 161 is updated in two inversions, despite the presence of the redundant element.
  • the state-storage feedback loop 171 of circuit 170 includes an inverter 172, an OAI stage that includes OR gate 173 and NAND gate 174, an inverter 175, an OAI stage that includes OR gate 176 and NAND gate 177, an inverter 178, and an OAI stage that Includes OR gate 179 and NAND gate 1701 , coupled in series.
  • the inverters 175 and 178, the OR gates 176 and 179, and the NAND gates 177 and 1701 constitute a redundant element that reduces the minimum retention voltage of circuit 170.
  • Circuit 170 may be referred to as a hex inversion OAI multi-write Vmin set-reset latch.
  • the data input signal set-bar is sensed in parallel by NAND gates 174, 177 and 1701 , and the data input signal reset is sensed in parallel by OR gates 173, 176 and 179. That is, according to the present embodiment of the present invention, the set-bar signal is written in parallel into feedback loop 171 at multiple locations, labeled A, B and C, instead of in just one location, and the reset signal is written in parallel into feedback loop 171 at multiple locations, labeled D, E and F, instead of in just one location. Signals proceed in parallel through feedback loop 171 from each of the write locations A, B, C, D, E and F. Thus, feedback loop 171 is updated in two inversions, despite the presence of the redundant element.
  • the state-storage feedback loop 181 of circuit 180 includes an inverter 182, an AOI stage that includes AND gate 183 and NOR gate 184, an inverter 185, and an AOI stage that includes AND gate 186 and NOR gate 187, an inverter 188, and an AOI stage that includes AND gate 189 and NOR gate 1801 , coupled in series.
  • the inverters 185 and 188, the AND gates 186 and 189, and the NOR gates 187 and 1801 constitute a redundant element that reduces the minimum retention voltage of circuit 180.
  • Circuit 180 may be referred to as a hex inversion AOI multi-write Vmin set-reset latch.
  • the data input signal set-bar is sensed in parallel by AND gates 183, 186 and 189, and the data input signal reset is sensed in parallel by NOR gates 184, 187 and 1801. That is, according to the present embodiment of the present invention, the set-bar signal is written in parallel into feedback loop 181 at multiple locations, labeled A, B and C, instead of in just one location, and the reset signal is written in parallel into feedback loop 181 at multiple locations, labeled D, E and F, instead of in just one location. Signals proceed in parallel through feedback loop 181 from each of the write locations A, B, C, D, E and F. Thus, feedback loop 181 is updated in two inversions, despite the presence of the redundant element.
  • Embodiments in accordance with the present invention are not limited to the examples described by Figures 11-16 above.
  • embodiments in accordance with the present invention introduce first and second data inputs into multiple points on a state-storage feedback loop. Accordingly, a feedback loop of arbitrary length can be updated in as few as two inversions, depending on the number of write locations.
  • the feedback loop includes an even number of circuit elements (e.g., gates) coupled in series.
  • a first data input is introduced into the feedback loop at the inputs of alternate circuit elements (e.g., at the input of every other gate in the feedback loop), and a second data input is introduced into the feedback loop at the circuit elements between the alternate circuit elements.
  • the state-storage feedback loop can be viewed as having a number of stages, where the first data input is written in parallel into each of the stages, and where the second data Input is also written in parallel into each of the stages.
  • the multi-write reduced Vmin circuits of Figures 11-16 can be used in combination with the reduced Vmin circuits of Figures 9-10. Because a multi-write Vmin circuit may have larger data capacitances than a reduced Vmin circuit, and thus may slightly increase power dissipation within the feedback loop, it may be appropriate to use multi-write reduced Vmin circuits in critical paths (for speed) and reduced Vmin circuits in non-critical paths (to conserve power).
  • FIG 17 is a flowchart 1900 of a method for writing state to a memory circuit having a data input and a clock input and reduced minimum retention voltage in accordance with one embodiment of the present invention (e.g., the circuits of Figures 5-8).
  • flowchart 1900 a method for writing state to a memory circuit having a data input and a clock input and reduced minimum retention voltage in accordance with one embodiment of the present invention (e.g., the circuits of Figures 5-8).
  • steps are disclosed in flowchart 1900, such steps are exemplary. That is, embodiments in accordance with the present invention are well-suited to performing various other steps or variations of the steps recited in flowchart 1900. It is appreciated that the steps in flowchart 1900 may be performed in an order different than presented and that the steps in flowchart 1900 are not necessarily performed in the sequence illustrated.
  • step 1910 of Figure 17 a clock input is received at a first set of multiple points in a state-storage feedback loop of a memory circuit.
  • a data input is received at a second set of multiple points on the feedback loop.
  • the data input is received at alternate circuit elements of the feedback loop.
  • the feedback loop may include a same number of inverters and three-state inverters coupled alternately in series.
  • the data input is received at the inputs of the inverters.
  • step 1930 the data input is propagated from the second set of multiple points to other points in the feedback loop.
  • Figure 18 is a flowchart 2000 of a method for writing state to a memory circuit having first and second data inputs and reduced minimum retention voltage in accordance with one embodiment of the present invention (e.g., the circuits of Figures 11-16).
  • flowchart 2000 Although specific steps are disclosed in flowchart 2000, such steps are exemplary. That is, embodiments in accordance with the present invention are well-suited to performing various other steps or variations of the steps recited in flowchart 2000. It is appreciated that the steps in flowchart 2000 may be performed in an order different than presented and that the steps in flowchart 2000 are not necessarily performed in the sequence illustrated.
  • a first data input is received at a first set of multiple points in a state-storage feedback loop of a memory circuit.
  • step 2020 a second data input is received at a second set of multiple points in the feedback loop.
  • step 2030 the first and second data inputs are propagated from the first and second sets of points to other points in the feedback loop.
  • embodiments in " accordance with the present invention can reduce the time needed to secure a new state in a feedback loop of a memory circuit.

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Abstract

Cette invention concerne divers types de circuits de mémoire. Un circuit de mémoire peut comprendre une boucle de rétroaction à mémoire d'état couplée à une entrée d'horloge et à une entrée de données. L'entrée de données est introduite dans la boucle de rétroaction au niveau de multiples points puis propagée en parallèle depuis ces points vers d'autres points dans la boucle de rétroaction.
PCT/US2007/007930 2006-03-31 2007-03-30 Circuit de mémoire WO2007123694A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/395,017 2006-03-31
US11/395,017 US8067970B2 (en) 2006-03-31 2006-03-31 Multi-write memory circuit with a data input and a clock input
US11/396,114 US7592836B1 (en) 2006-03-31 2006-03-31 Multi-write memory circuit with multiple data inputs
US11/396,114 2006-03-31

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WO2007123694A1 true WO2007123694A1 (fr) 2007-11-01

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09244585A (ja) * 1996-03-04 1997-09-19 Toppan Printing Co Ltd ラッチ機能付きレベルシフタ回路
US6211702B1 (en) * 1998-05-06 2001-04-03 Oki Electric Industry Co., Ltd. Input circuit
US20040076041A1 (en) * 1999-07-06 2004-04-22 Hideo Akiyoshi Latch circuit having reduced input/output load memory and semiconductor chip

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09244585A (ja) * 1996-03-04 1997-09-19 Toppan Printing Co Ltd ラッチ機能付きレベルシフタ回路
US6211702B1 (en) * 1998-05-06 2001-04-03 Oki Electric Industry Co., Ltd. Input circuit
US20040076041A1 (en) * 1999-07-06 2004-04-22 Hideo Akiyoshi Latch circuit having reduced input/output load memory and semiconductor chip

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HAMID MAHMOODI-MEIMAND AND KAUSHIK ROY: "Data-Retention Flip-flops for Power-Down Applications", XP002448196, Retrieved from the Internet <URL:http://ieeexplore.ieee.org/iel5/9255/29377/01329362.pdf> *

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