WO2007119373A1 - システム制御装置 - Google Patents
システム制御装置 Download PDFInfo
- Publication number
- WO2007119373A1 WO2007119373A1 PCT/JP2007/055220 JP2007055220W WO2007119373A1 WO 2007119373 A1 WO2007119373 A1 WO 2007119373A1 JP 2007055220 W JP2007055220 W JP 2007055220W WO 2007119373 A1 WO2007119373 A1 WO 2007119373A1
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- WO
- WIPO (PCT)
- Prior art keywords
- unit
- peripheral device
- external microcomputer
- system lsi
- lsi
- Prior art date
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
Definitions
- the present invention relates to an improvement of a system control device in which a system LSI having an additional function is added so that an external microcomputer having a predetermined function has an additional function.
- an analog TV device is equipped with a digital TV function
- a car navigation device is equipped with a digital TV function
- a personal computer is equipped with a digital TV function
- a system LSI with a system control microcomputer and a digital TV function integrated into one chip is added.
- Patent Document 1 JP 2004-164113 A
- the present invention uses a system control microcomputer built in the system LSI for execution of the function of the system LSI while using the system LSI including the system control microcomputer. It is configured that an external system control microcomputer directly performs system bus control indirectly through the system LSI, or an external system control microcomputer directly performs system bus control.
- the system control device of the present invention includes a system LSI unit that incorporates a system control microcomputer that integrates a single or a plurality of functions on one chip and controls the system bus with respect to the execution of the functions.
- An external microcomputer unit, and the external microcomputer unit incorporates another system control microcomputer for controlling the system node with respect to execution of at least a part of the functions of the system LSI unit.
- the present invention provides the system controller, wherein the system LSI unit includes an arbitration unit that arbitrates access to the system bus with the external microcomputer unit, and the system LSI unit and the external microcomputer unit include The system bus is shared, and one of the system control microcomputers controls the system bus by access arbitration by the arbitration unit.
- the present invention provides the system controller, wherein the system LSI unit uses the arbitration unit and a system bus interface to receive an access request from the external microcomputer unit, and at the time of receiving the request, A part of the function of the system LSI unit is controlled in response to an access request.
- the present invention provides the system control device including a peripheral device unit connected to the system bus, wherein the system LSI unit uses the arbitration unit and a system bus interface to Upon receiving an access request to the peripheral device section At the time of acceptance, the peripheral device unit is accessed according to the access request.
- the present invention provides the system control device, wherein the system LSI unit and the peripheral device unit each output an acknowledge signal when access is completed, and the system LSI unit and the peripheral device unit An acknowledge signal control unit is provided for controlling so that the output acknowledge signal is not input to the external microcomputer unit.
- the present invention is characterized in that, in the system control apparatus, the acknowledge signal control unit is provided in the system LSI unit.
- the present invention provides the system control device in which read data read from the peripheral device unit is input to the system LSI unit when a read access request is made from the external microcomputer unit to the peripheral device unit.
- the read data signal control unit controls the system LSI unit so as not to output the read data to the data bus, and the read data signal control unit is provided in the system LSI unit. It is provided inside.
- the present invention provides the system controller, wherein when the read access request is made from the external microcomputer unit to the peripheral device unit, the system LSI unit takes in the read data read from the peripheral device unit, The fetched read data is sent to the system bus, and an acknowledge signal is issued to the external microcomputer unit.
- the external microcomputer unit receives the acknowledge signal from the system LSI unit and completes the read access.
- the present invention provides the system control device, wherein the peripheral device unit outputs an acknowledge signal upon completion of access, and issues a read access request from the external microcomputer unit to the peripheral device unit.
- the external microcomputer unit and the system LSI unit receive the acknowledge signal output from the peripheral device unit and complete the read access.
- the present invention provides the system controller, wherein the system LSI unit indirectly issues a write access request from the external microcomputer unit to the peripheral device unit.
- the system LSI unit issues an acknowledge signal to the external microcomputer unit when the external microcomputer unit receives a write access request to the peripheral device unit, and terminates the write access request of the external microcomputer unit. After acquiring the system bus, a write access request is issued to the peripheral device unit.
- the present invention provides the system control device, wherein the peripheral device unit outputs an acknowledge signal when access is completed, and issues a write access request from the external microcomputer unit to the peripheral device unit.
- the peripheral device unit receives the output acknowledge signal and the write access is completed.
- the present invention includes a peripheral device unit connected to the system bus in the system control device, wherein the system control microcomputer of the external microcomputer unit acquires the system bus with respect to the arbitration unit of the system LSI unit After acquiring the system bus, the access request is made directly to the system LSI unit or the peripheral device unit without operating the system control microcomputer of the system LSI unit.
- the system control apparatus includes an address strobe signal control unit between the system LSI unit and the external microcomputer unit, and the address strobe signal control unit includes:
- the address strobe signal issued by the external microcomputer is effective only when an access request from the external microcomputer unit to the system LSI unit is issued.
- the present invention is characterized in that, in the system control apparatus, the address strobe signal control unit is built in the system LSI unit.
- the system LSI unit is a system LSI incorporating a digital television function
- the external microcomputer unit includes an analog television function, a car navigation function.
- it is a microcomputer having a personal computer function.
- the system control microcomputer of the external microcomputer unit requests the arbitration unit built in the system LSI unit to acquire the system bus, and the arbitration unit grants permission.
- the system bus can be acquired and the external microcomputer unit can directly or system control microcomputer Requests for read or write access via the system bus can be made to the system LSI part and peripheral device part via the network.
- system LSI when a system LSI having a new function is added to a system having an existing function, the system LSI to be added is added to many system designers.
- System control can be performed using the system control microcomputer in the existing system, which is not limited to only the system control microcomputer in the system, so the degree of freedom in selecting the system control microcomputer can be increased and the existing design assets can be used effectively.
- system LSIs with attractive new functions can be easily introduced, and system construction can be made at low cost.
- FIG. 1 is a diagram showing an overall configuration of a system control apparatus according to a first embodiment of the present invention.
- FIG. 2 is a diagram showing a read access chart to an external microcomputer unit system LSI unit in the system control device.
- FIG. 3 is a diagram showing a write access chart to the external microcomputer component system LSI unit in the system control device.
- FIG. 4 is a diagram showing a lead access chart to the peripheral device section of the external microcomputer unit in the system control apparatus.
- FIG. 5 is a diagram showing a light access chart to the peripheral device section of the external microcomputer unit in the system control apparatus.
- FIG. 6 is a diagram showing an overall configuration of a system control apparatus according to a second embodiment of the present invention.
- FIG. 7 is a view showing a read access chart from an external microcomputer unit to a peripheral device unit in a system control apparatus according to a fifth embodiment of the present invention.
- FIG. 8 is a view showing a write access chart from the external microcomputer unit to the peripheral device unit in the system control apparatus according to the sixth embodiment of the present invention.
- FIG. 9 is a diagram showing an overall configuration of a system control apparatus according to an eighth embodiment of the present invention. Explanation of symbols
- FIG. 1 shows the overall configuration of the system control apparatus according to the first embodiment of the present invention.
- an external microcomputer unit 102 is an existing microcomputer, for example, a microcomputer having an analog TV function or a car navigation function, or a microcomputer built in a personal computer.
- the system LSI unit 101 has a system control microcomputer (not shown) built in along with functions such as a digital television function and is integrated on a single chip.
- the peripheral device unit 103 includes a system bus interface such as a USB controller.
- the signal flowing through the system bus 104 is a 32-bit address signal (EA [31: 0]), a 16bit data signal (ED [15: 0]), a read signal (XERE: negative logic), 1 byte 1 write unit (XEWE [1: 0]: negative logic), 6 chip select signals (XECS [5: 0]: negative logic), size signal ESZ indicating access size .
- EA 32-bit address signal
- ED 16bit data signal
- XERE negative logic
- XEWE 1 byte 1 write unit
- 6 chip select signals XECS [5: 0]: negative logic
- size signal ESZ indicating access size .
- the address signal EA, data signal ED, and size signal ESZ are all transmitted from the external microcomputer unit 102 and the system LSI unit 101.
- the read signal XERE, the write signal XE WE, and the chip select signal XECS are for accessing the peripheral device unit 103. Therefore, in the present embodiment, the microcomputer power built in the external microcomputer 102 is not directly related to the execution of at least a part of the function of the system LSI unit 101 (for example, the digital TV function). It is output only from the system LSI unit 101 so that the peripheral device unit 103 can be accessed, and is not output from the external microcomputer unit 102.
- the system LSI unit 101 incorporates an arbitration unit 101a and implements the following specifications. Specifically, when the external microcomputer unit 102 asserts a bus request signal (XEBRQ: negative logic), which is a bus request signal, the arbitration unit 101a receives the bus request signal XEB RQ, and performs the nose access being executed. After the completion, a nodal signal (XEBGT: negative logic), which is a bus release notification signal, is asserted to the external microcomputer unit 102 to perform a bus arbitration function that releases the right to use the system bus 104 to the external microcomputer unit 102.
- XEBRQ negative logic
- XEBGT nodal signal
- the system LSI unit 101 When the system LSI unit 101 asserts the bus grant signal XEBGT to release the right to use the system bus 104 to the external microcomputer unit 102, the address signal EA, the data signal ED, the size signal ESZ, and the address valid
- the system LSI unit 101 can accept an access request from the external microcomputer 102.
- the access request from the external microcomputer 102 is a system comprising the read / write signal ERXW, the address strobe signal XEAS, the acknowledge signal XEDK, and the system bus 104 after the external microcomputer 102 acquires the system bus 104 using the arbitration unit 101a. This is done as follows using the bus interface.
- FIG. 2 shows an access chart when the external microcomputer unit 102 has read access to the system LSI unit 101 after acquiring the right to use the system bus 104.
- the system LSI unit 101 outputs the read data ED and the acknowledge signal XEDK as the external microcomputer. This is output to section 102 to show how the read access is completed.
- FIG. 3 shows the system after the external microcomputer unit 102 has acquired the right to use the system bus 104.
- An access chart for write access to the LSI unit 101 is shown.
- the system LSI unit 101 performs the write operation of the data ED.
- the acknowledge signal XEDK is output to the external microcomputer unit 102, and the write access is terminated.
- FIG. 4 shows that after the external microcomputer unit 102 acquires the right to use the system bus 104, it issues a read access request to the peripheral device unit 103 to the system LSI unit 101, and issues this access request.
- the read cycle chart in which the received system LSI unit 101 performs read access to the peripheral device unit 103 is shown.
- the external microcomputer unit 102 outputs the address signal EA, size signal ESZ, read / write signal ER XW (High level), and address strobe signal XEAS.
- the LSI unit 101 When the LSI unit 101 outputs the chip select signal XECS and the read signal X ERE specifying the peripheral device unit 103, and the peripheral device unit 103 outputs the read data ED to the system bus 104, the system that has received this read data ED The LSI unit 101 outputs the read data ED to the system bus 104 and outputs the acknowledge signal XEDK to the external microcomputer unit 102, and the external microcomputer unit 102 ends the read access.
- FIG. 5 After the external microcomputer unit 102 has acquired the right to use the system bus 104, it issues a write access request to the peripheral device unit 103 to the system LSI unit 101, and receives this access request.
- the system LSI unit 101 outputs acknowledge signal XEDK.
- the external microcomputer 102 that received this signal XEDK immediately ends the write access.
- the system LSI unit 101 outputs a signal such as the write data ED received from the external microcomputer unit 102 and the chip select signal XECS to the system bus 104 and writes the write data ED to the peripheral device unit 103.
- FIG. 6 shows the overall configuration of the system control apparatus according to the present embodiment.
- the system LSI unit 601 having the arbitration unit 601a, the external microcomputer unit 602, and the system bus 604 are the same as those in the first embodiment, but the difference from the first embodiment is that the peripheral device A point 603 is a handshake device having a function of outputting an acknowledge signal, and an acknowledge signal control unit 605 is added.
- acknowledge signal control section 605 The operation of acknowledge signal control section 605 will be described separately for a read access request and a write access request.
- the peripheral device unit 603 When a read access request is made from the external microcomputer unit 602 to the peripheral device unit 603, the peripheral device unit 603 outputs read data and issues an acknowledge signal, and the acknowledge signal control unit 605 sends the acknowledge signal to the external microcomputer. Passed to part 602. As a result, the external microcomputer unit 602 ends the read cycle. After that, the system LSI unit 601 that has received the read data ED from the peripheral device unit 603 issues the read data ED again to the system bus 604 and outputs the acknowledge signal XEDK as in the chart of FIG. The signal control unit 605 masks the output of the acknowledge signal to the external microcomputer unit 602. The external device 602 receives read data from the system LSI unit 601. However, data collision can be avoided by setting a sufficient wait period.
- the acknowledge signal control unit 605 passes the acknowledge signal XE DK issued from the system LSI 601 to the external microcomputer unit 602.
- the external microcomputer unit 602 ends the write cycle.
- the system LSI unit 601 has the ability to issue a write access request to the peripheral device unit 603.
- the acquisition right of the system bus 604 has already been transferred from the external microcomputer unit 602 to the system LSI unit 601. Even if the 603 issues the acknowledge signal XEDK, the system does not malfunction, but it is desirable to prevent the acknowledge signal control unit 605 from issuing the analog signal XEDK from the peripheral device unit 603 to the external microcomputer unit 602. .
- the present embodiment has the following advantages. That is, in the first embodiment, the peripheral device unit 103 does not have a function of outputting the acknowledge signal XEDK, and the set period Since this is a fixed-length access device that is considered to have been accessed after the elapse of time, fixed-length access must be set in the peripheral device selection register existing in the system LSI unit 101.
- a handshake device that outputs an acknowledge signal as 603 can be adopted, and the degree of freedom in device selection of the peripheral device unit 603 can be improved, and the degree of freedom in system design is improved.
- the force in which the acknowledge signal control unit 605 is arranged outside the system LSI unit 601 is adopted in the present embodiment.
- the system LSI unit 601 issues the read data to the system bus 604.
- a read data control unit (not shown) is provided so that the received read data is not issued to the system bus 604, and this read data control unit is incorporated in the system LSI unit 601. .
- the external device 602 does not need to worry about data collision, so that an effect of facilitating system design can be obtained.
- the peripheral device unit 103 is a handshake device, the operation at the time of a read access request from the external microcomputer unit to the peripheral device unit 103 is improved.
- the system LSI unit 101 has a built-in register for setting whether the peripheral device unit 103 is a handshake device or a fixed-length device.
- Self-referencing, peripheral device 103 is handshake device Make sure that
- the system LSI unit 101 receives from the peripheral device unit 103 as can be seen in comparison with the lead cycle chart of FIG.
- the operation of outputting the read data ED to the system bus 104 again can be made unnecessary, and the overhead during the read cycle via the system LSI unit 101 can be improved for that time.
- FIG. 8 shows a write access chart according to the sixth embodiment of the present invention.
- the overall configuration of the system control device is the same as in Figure 1.
- the system LSI unit 101 corresponds to the chip corresponding to the peripheral device unit 103.
- Select signal XECS and read Z write signal XEWE (Low level) are additionally issued to write the write data ED from the external microcomputer unit 102 to the peripheral device unit 103, and then the peripheral device unit that completed the writing
- acknowledge signal XEDK is issued from 103
- external microcomputer unit 102 receives acknowledge signal XEDK and terminates the write access request. Therefore, according to the present embodiment, it is possible to achieve two cycles in terms of the appearance of the system and achieve one write access cycle, and the external microcomputer unit 103 does not need to consider an extra wait setting. Request overhead is effectively improved.
- the write access request in the sixth embodiment is optimized.
- the system LSI unit 101 has a built-in register for setting whether it is a handshake device or a fixed-length device, so that the setting is self-referenced and the peripheral device unit 103 is set as a handshake device.
- a write access request from the external microcomputer unit 102 to the peripheral device unit 103 is issued, a chip select signal XECS and a read Z write signal XEWE (Low level) corresponding to the peripheral device unit 103 are additionally issued to
- the device unit 103 writes the write data ED and issues the acknowledge signal XEDK
- the system LSI unit 101 and the external device unit 102 that have received the acknowledge signal XEDK end each write cycle.
- the system LSI unit 101 has a higher degree of freedom in selecting a device as a handshake device or a fixed-length device in the write cycle, and the write cycle protocol is the same as that of the read cycle. Because it can be realized with this protocol, implementation design becomes very easy. However, since the external microcomputer unit 103 can establish complete handshake access, the overhead during the write cycle can be effectively improved.
- FIG. 9 shows the overall configuration of the system control apparatus according to the eighth embodiment of the present invention.
- system control microcomputer of the system LSI unit 901 is not used, and the microcomputer built in the external microcomputer unit 902 is directly used as the system control microcomputer. 901 and the peripheral device unit 903 are controlled.
- the system LSI unit 901 having the arbitration unit 901a, the external microcomputer unit 902, and the peripheral device unit 903 are arranged, and the address strobe control unit 905 exists.
- the system LSI unit 901 does not output the chip select signal XE CS and the read Z write signal XERE to the system bus 904 because the microcomputer built in the external microcomputer unit 902 becomes the system control microcomputer. Output from the microcomputer unit 902.
- the address strobe control unit 905 validates the address strobe signal XEAS only when an access request is made from the external microcomputer unit 902 to the system LSI unit 901, and when an access request is made from the external microcomputer unit 902 to the peripheral device unit 903, Disable address strobe signal XEAS.
- the system LSI unit 901 performs an operation only to open the system bus 904 unless the address strobe signal XEAS is input from the external microcomputer unit 902. Therefore, the external device unit 902 can directly access the peripheral device unit 903.
- the overhead due to the indirect read or write access to the system LSI unit 901 that is, the write access is performed in two cycles as shown in FIG.
- the overhead of 1 access cycle is minimized, and the system performance is improved.
- the peripheral device 903 can be employed not only as a fixed-length device but also as a node shake device, the degree of freedom in system design is improved.
- the address strobe signal control unit 905 is arranged outside the system LSI unit 901, but it may be arranged inside the system LSI unit 901. In this case, a configuration that is easy in system design can be provided.
- the present invention provides a system control microcomputer in an existing system to many system designers when a system LSI having a new function is added to a system having an existing function. Any of the system control microcomputers in the LSI Therefore, it is useful as a system control device that can construct a system at low cost while effectively utilizing existing design assets.
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Abstract
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US12/096,473 US20090125664A1 (en) | 2006-04-04 | 2007-03-15 | System controller |
JP2008510785A JPWO2007119373A1 (ja) | 2006-04-04 | 2007-03-15 | システム制御装置 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2006103167 | 2006-04-04 | ||
JP2006-103167 | 2006-04-04 |
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WO2007119373A1 true WO2007119373A1 (ja) | 2007-10-25 |
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PCT/JP2007/055220 WO2007119373A1 (ja) | 2006-04-04 | 2007-03-15 | システム制御装置 |
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US (1) | US20090125664A1 (ja) |
JP (1) | JPWO2007119373A1 (ja) |
WO (1) | WO2007119373A1 (ja) |
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US9092387B2 (en) * | 2008-12-10 | 2015-07-28 | Micron Technology, Inc. | Non-volatile memory device capable of initiating transactions |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10134008A (ja) * | 1996-11-05 | 1998-05-22 | Mitsubishi Electric Corp | 半導体装置およびコンピュータシステム |
JP2004199187A (ja) * | 2002-12-16 | 2004-07-15 | Matsushita Electric Ind Co Ltd | Cpu内蔵lsi |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3075184B2 (ja) * | 1996-08-02 | 2000-08-07 | 日本電気株式会社 | 演算処理機能付主記憶システム及びその制御方法 |
JP4554016B2 (ja) * | 2000-01-20 | 2010-09-29 | 富士通株式会社 | バス使用効率を高めた集積回路装置のバス制御方式 |
JP2006172256A (ja) * | 2004-12-17 | 2006-06-29 | Renesas Technology Corp | 情報処理装置 |
-
2007
- 2007-03-15 US US12/096,473 patent/US20090125664A1/en not_active Abandoned
- 2007-03-15 WO PCT/JP2007/055220 patent/WO2007119373A1/ja active Application Filing
- 2007-03-15 JP JP2008510785A patent/JPWO2007119373A1/ja not_active Withdrawn
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10134008A (ja) * | 1996-11-05 | 1998-05-22 | Mitsubishi Electric Corp | 半導体装置およびコンピュータシステム |
JP2004199187A (ja) * | 2002-12-16 | 2004-07-15 | Matsushita Electric Ind Co Ltd | Cpu内蔵lsi |
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JPWO2007119373A1 (ja) | 2009-08-27 |
US20090125664A1 (en) | 2009-05-14 |
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