WO2007108406A1

WO2007108406A1 - Error tolerant method and semiconductor integrated circuit capable of realizing the method

Info

Publication number: WO2007108406A1
Application number: PCT/JP2007/055342
Authority: WO
Inventors: Kazuteru Nanba; Hideo Ito; Yoichi Sasaki
Original assignee: National University Corporation Chiba University
Priority date: 2006-03-23
Filing date: 2007-03-16
Publication date: 2007-09-27
Also published as: JPWO2007108406A1; JP4555971B2

Abstract

A software error tolerant method that is useful for a logic circuit unit and a semiconductor integrated circuit that carries out the method are provided to enhance capability in attenuating a software error while to suppress decrease in a circuit operation speed. In an error tolerance method, a pass transistor attenuates a signal including a software error generated by a logic circuit unit and a Schmidt trigger circuit masks the attenuated signal. A semiconductor integrated circuit is comprised of a logic circuit unit, a pass transistor electrically connected with the logic circuit unit and a Schmidt trigger circuit electrically connected with the pass transistor.

Description

Specification

Error tolerant method and semiconductor integrated circuit capable of realizing the method

The present invention relates to an error tolerant method and a semiconductor integrated circuit capable of executing the method.

Background art

[0002] Errors that occur in a semiconductor integrated circuit can be classified into soft errors and hard errors. A hard error is an error caused by the structure of the semiconductor integrated circuit itself, and once it occurs, the signal value continues to be indefinitely incorrect. On the other hand, a soft error is an error that temporarily occurs during the operation of the semiconductor integrated circuit although the configuration of the semiconductor integrated circuit is normal. To recover. Soft errors occur when, for example, a semiconductor integrated circuit collides with the VLSI radiation power such as a-line or neutron beam that is generated by power such as a package enclosing space space or VLSI. It tends to occur on memory.

[0003] As a technique relating to soft error countermeasures (hereinafter referred to as "soft error tolerant" t), for example, Non-Patent Document 1 below discloses a semiconductor integrated circuit including a logic circuit unit and a latch circuit unit connected to the logic circuit unit. In the circuit, a technology has been disclosed in which the latch circuit portion has a double latch structure.

[0004] Further, in Non-Patent Document 2 below, the logic circuit unit and the output of the logic circuit unit are delayed by a delay time δ (where δ is the maximum value of the time affected by the soft error). A delay circuit having a delay time of 2 δ, a majority circuit that makes a majority decision based on the output of the logic circuit unit, the output of the first delay circuit and the output of the second delay circuit, and A technology relating to a semiconductor integrated circuit having a latch circuit portion for storing the output of the majority circuit is disclosed.

[0005] Further, Non-Patent Document 3 shown below has a logic circuit section, a plurality of nos transistors connected to the logic circuit part, and a latch circuit part connected via these pass transistors. Thus, a technique for attenuating soft errors that occur in the logic circuit section is described.

[0006] Non-Patent Document 1: M. Omana, D. Rossi, C. Metra, "Novel Transient Fault Hardened Static Latch, ..., ITC, pp886-892, 2003

Non-Patent Document 2: Nico idis, Time Redundancy― Based Soft— Error Tolorance to Rescue Nanometer Technologies ”, Proc. IEEE VLSI Test Symp., Pp86—94, 1999

Non-Patent Document 3: J. Kumar, Mehdi B. Tahoori, 'Use of pass transistor logic to minimize the impact of soft errors in combinational circuits, Workshop on System Effects of Logic Soft Errors ^ 2005 Disclosure of Invention

Problems to be solved by the invention

However, the technique described in Non-Patent Document 1 can prevent a soft error occurring in the latch unit, but cannot prevent a soft error occurring in the logic circuit unit. .

[0008] In addition, in the technique described in Non-Patent Document 2, it is necessary to increase the clock cycle by 2 δ, which may reduce the operation speed of the circuit. In addition, this technology uses a majority circuit, but there is a problem that the circuit becomes complicated and has a large area.

[0009] In addition, the technique described in Non-Patent Document 3 has a limit in the ability to be attenuated by the pass transistor, and a problem remains in the ability when a large soft error pulse is generated.

Therefore, the present invention provides a soft error tolerant method useful for a logic circuit unit and a semiconductor integrated circuit that realizes the soft error tolerant method, and further increases the soft error attenuation capability while suppressing a decrease in the operation speed of the circuit. With the goal.

Means for solving the problem

That is, an error tolerant method as a means for solving the above-described problem is characterized in that a signal including a soft error generated by a logic circuit unit is attenuated by a pass transistor and further masked by a Schmitt trigger circuit. One.

[0012] Although not limited, the Schmitt trigger circuit in this means is It is also desirable to use a barter type Schmitt trigger circuit.

[0013] In addition, a semiconductor integrated circuit as another means for solving the above-described problem includes a logic circuit portion, a pass transistor electrically connected to the logic circuit portion, and an electrically connected to the pass transistor. And a Schmitt trigger circuit.

[0014] Although not limited thereto, it is desirable to have a latch circuit unit electrically connected to the Schmitt trigger circuit in this means, and the path arranged in parallel with the Schmitt trigger circuit It is also desirable to have a transistor.

The invention's effect

As described above, the present invention is a soft error tolerant method useful for a logic circuit unit and a semiconductor integrated circuit that realizes the soft error tolerant method, and further increases the soft error attenuation capability while suppressing a decrease in the operation speed of the circuit. be able to.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments and examples shown below.

[0017] (Embodiment 1)

FIG. 1 shows a functional block diagram of the semiconductor integrated circuit according to the present embodiment.

As shown in FIG. 1, the semiconductor integrated circuit 1 according to the present embodiment includes a logic circuit unit 2, a soft error tolerant circuit unit 3 connected to the logic circuit unit, and a latch connected to the soft error tolerant circuit unit 3. And a circuit unit 4.

[0018] The logic circuit unit 2 is a circuit unit for performing calculation based on input data and outputting the result, and is not limited to, for example, an AND gate, an OR gate, a NOT gate, Force logic circuit unit 2 configured by combining NAND gates etc. Of course, it has a latch circuit.

The soft error tolerant circuit unit 3 is a circuit unit 3 for correcting a soft error that occurs in the logic circuit unit 2. Specifically, for example, as shown in FIG. 2, the pass transistor 31 and the pass transistor And a Schmitt trigger circuit 32 connected to 31. The nose transistor 31 is a transistor that connects the logic circuit section 2 and the Schmitt trigger circuit 32 via the source Z drain region of the transistor, and is not limited to the transistor, but as shown in FIG. The pass transistor 31 according to the present embodiment includes an NMOS transistor 311 and a PMOS transistor 312, and the source Z drain region in each transistor is electrically connected to the source Z drain region in the other transistor. . Note that the gate of the NMOS transistor 311 is grounded to the external power supply Vcc, and the gate of the PMOS transistor 312 is grounded, so that the gates of both transistors are on. Note that the pass transistor 31 in the present embodiment is not limited as long as it has the above-described function, and is a combination of the NMOS transistor 311 and the PMOS transistor 312. For example, the NMOS transistor only, the PMOS transistor only The present embodiment is not limited to this embodiment.

[0021] The Schmitt trigger circuit 32 is a circuit mainly used to remove noise at the rise and fall of a signal, and although not limited thereto, the source Z drain region is common as shown in FIG. And a common source / drain region 325 between the NMOS transistor 321 and PM transistor connected in series, and an inverter 327 electrically connected to the 326, and the output of the inverter 327 Are connected to the gates of NMOS transistor 323 and PMOS transistor 324. Note that the common source Z drain of the NMOS transistors 321 and 323 is grounded, and the non-common source Z drain of the PMOS transistors 322 and 324 is connected to Vcc. In the present embodiment, the output of the inverter 327 is also the output of the Schmitt transistor circuit.

The force shown in FIG. 2 as an example of the Schmitt trigger circuit 32 of the present embodiment, for example, a configuration as shown in FIG. 3 can be adopted and is limited to the configuration described in the present embodiment. This is not the case. The Schmitt trigger circuit 32 shown in FIG. 3 includes a plurality of PMOS transistors 3211 and 3212 and a plurality of N MOS transistors 3213 and 3214 that are connected in series in a common manner with a common source Z drain region, and a plurality of PMOS transistors. 3211, 3212 common source Z drain region PMOS transistor 3216 connected to 3215 and multiple NMO And an NMOS transistor 3218 connected to a common source / drain region 3217 of the S transistors 3213 and 3214. In this figure, the Schmitt trigger circuit 32 has an output of the source / drain region 3219 between the PMOS transistor 3212 and the NMOS transistor 3213, and is connected to the gates of the PMOS transistor 3216 and the NMOS transistor 3218 described above. ing.

Here, the principle of noise removal by the Schmitt trigger circuit 32 will be described with reference to FIG. Generally, a digital circuit determines whether an input signal is “1” or “0” (in some expressions, “High”, “Low”, “high potential”, or “low potential”). Specifically, “1” is judged for an input having a predetermined voltage or higher, and “0” is judged for an input signal lower than a predetermined voltage (this predetermined voltage is called “threshold voltage”). o However, noise is usually added to these input signals, and this becomes a significant problem at voltages near the threshold voltage. In other words, depending on the magnitude of the noise, the input signal that should be originally “1” becomes “0” due to noise, or the input signal that should originally be “0” becomes “1”. (See Fig. 4 (A)). On the other hand, the Schmitt trigger circuit has two threshold voltages to give directionality to the input signal. According to this circuit, if the input signal exceeds Vth + and is determined to be “1”, it remains “1” even if the input signal falls below Vth +, and it is not determined to be “0” unless it falls below Vth−. This prevents noise near the threshold voltage (see Fig. 4 (B)).

[0024] The latch circuit unit 4 is a circuit unit for holding the output from the soft error tolerant circuit unit 3 based on the logic circuit unit 2, and is not limited as long as the output can be stored. However, an example of this circuit configuration is shown in FIG. The latch circuit 4 preferably stores the output temporarily for data processing, but may be omitted if the latch circuit 4 has a configuration that does not require a latch such as direct input to another logic circuit unit. The

Next, an error tolerant method using the semiconductor integrated circuit according to the present embodiment will be described. First, it is assumed that a soft error has occurred in the logic circuit unit 2. Then, a signal including this soft error (hereinafter referred to as “soft error signal”) is input to the non-transistor 31 and the voltage is attenuated. The nos transistor 31 normally receives the signal from the logic circuit section 2. When a temporary soft error is input, the magnitude of the input soft error is attenuated so that the Schmitt trigger circuit 32 can mask it. (The attenuation factor of the pass transistor is approximately 10%). Then, the Schmitt trigger circuit 32 can mask the soft error based on the input signal in which the soft error is attenuated. More specifically, in the pass transistor 31, for example, as shown in FIG. 6, there is a case where the initial magnitude of the soft error generated in the logic circuit section 2 exceeds the threshold voltage (Vth +). Even so, the non-transistor 31 can attenuate the soft error voltage until noise masking is possible, and keep it within the range that can be masked by the Schmitt trigger circuit. By doing so, it becomes a soft error tolerant method useful for the logic circuit unit according to the present embodiment, and it is possible to further increase the soft error attenuation capability while suppressing a decrease in the operation speed of the circuit. In particular, according to this circuit, since there is no need to provide a delay circuit as in the prior art, it is possible to reduce the operating speed. In addition, the majority circuit is unnecessary and the semiconductor integrated circuit does not increase in area. Needless to say, if a soft error does not occur in the logic circuit unit 2, the output signal from the logic circuit unit 2 can be output to the latch circuit unit 4 as it is.

(Embodiment 2)

The present embodiment is substantially the same as the first embodiment, except that the soft error tolerant circuit unit 3 has a function as a latch. FIG. 7 shows a functional block diagram of the semiconductor integrated circuit 1 according to the present embodiment, and FIG. 8 shows an example of an equivalent circuit of the soft error tolerant circuit unit 3 according to the present embodiment.

As shown in FIG. 7, the soft error tolerant circuit unit 3 of the semiconductor integrated circuit according to the present embodiment has a latch function, and is configured integrally with the latch circuit unit 4 in the first embodiment. Is different.

Further, as shown in FIG. 8, the soft error tolerant circuit unit 3 according to the present embodiment includes a force pass transistor 31 and a Schmitt trigger circuit 32 that are substantially the same as the example of the first embodiment shown in FIG. And a pass transistor 33 connected in parallel with the Schmitt trigger circuit 32.

[0029] The pass transistor 31 is a force NMOS transistor having substantially the same configuration as that of the first embodiment. The difference is that the gate of 321 is connected to the clock signal elk, and the gate of the PMOS transistor 322 is connected to the inverted clock signal inverted from the clock signal elk. That is, the pass transistor 31 can control the input to the Schmitt trigger circuit 32 or the pass transistor 33 arranged in parallel with the Schmitt trigger circuit 32 in this way.

The pass transistor 33 connected in parallel to the Schmitt trigger circuit 32 in the present embodiment is different in the signal input to the force gate having the same configuration as the pass transistor 31 in the previous stage. Specifically, the inverted clock signal is input to the gate of the NMOS transistor 331, and the clock signal elk is input to the gate of the PMOS transistor 332. As a result, when the gate of the previous pass transistor 31 is in the on state, it is turned off, and when it is in the off state, it is turned on.

It is to be noted that the Schmitt trigger circuit 33 is of course not limited to the example of FIG. 8 as in the above-described embodiment, and may be configured as shown in FIG. 9, for example. The Schmitt trigger circuit 32 shown in Fig. 9 is connected to the output side of the Schmitt trigger circuit shown in Fig. 4 in series with a common source Z drain region. The difference is that the PMOS transistor 3220 and the NMOS transistor 3221 are arranged. Note that the source Z drain region on the non-common side of the PMOS transistor 3220 is provided at Vcc, and the source Z drain region on the non-common side of the NMOS transistor 3221 is provided. The common source Z drain region 3222 is the output of the Schmitt trigger circuit 33.

As described above, according to the semiconductor integrated circuit according to the present embodiment, the pass transistor 33 is provided between the pass transistor 31 and the Schmitt trigger circuit 32 which only have the same effect as in the first embodiment. Are provided in parallel and a loop is formed, so that an error mask function is provided and a latch circuit can be configured to function as a latch. This makes it possible to further reduce the area.

Brief Description of Drawings

[0033] FIG. 1 is a diagram showing functional blocks of a semiconductor integrated circuit according to an embodiment.

FIG. 2 is a diagram showing detailed circuits of a pass transistor and a Schmitt trigger circuit according to the embodiment. FIG. 3 is a diagram for explaining the operation of the Schmitt trigger circuit according to the embodiment.

FIG. 4 is a diagram showing an example of another configuration of the Schmitt trigger circuit according to the embodiment.

FIG. 5 is a diagram showing a detailed circuit of the latch circuit according to the embodiment.

FIG. 6 is a diagram for explaining operations of a pass transistor and a Schmitt trigger circuit.

FIG. 7 is a functional block diagram of a semiconductor integrated circuit according to a second embodiment.

FIG. 8 is a diagram showing a detailed circuit of a pass transistor and a Schmitt trigger circuit.

FIG. 9 is a diagram showing another example of a Schmitt trigger circuit.

Explanation of symbols

1 ... Semiconductor integrated circuit, 2 ... Logic circuit part, 3 ... Error tolerant circuit part, 4 ... Latch circuit 31 ... Non-range run, 32 ... Schmidts-Riga times, 33 ... · Nos Rungis evening, 311, 32 1, 323-NMOS transistor, 312, 322, 324 · "PMOS transistor

Claims

The scope of the claims

[1] An error tolerant method in which a signal containing a soft error generated by a logic circuit section is attenuated by a pass transistor and then masked by a Schmitt trigger circuit.

2. The error tolerant method according to claim 1, wherein an inverter type Schmitt trigger circuit is used as the Schmitt trigger circuit.

[3] Logic circuit part,

A pass transistor electrically connected to the logic circuit unit;

And a Schmitt trigger circuit electrically connected to the nos transistor.

4. The semiconductor integrated circuit according to claim 3, further comprising a latch circuit portion electrically connected to the Schmitt trigger circuit.

5. The semiconductor integrated circuit according to claim 3, further comprising a pass transistor arranged in parallel with the Schmitt trigger circuit.