JPWO2007108406A1 - Error tolerant method and semiconductor integrated circuit capable of realizing the method - Google Patents

Abstract

A soft error tolerant method useful for a logic circuit unit and a semiconductor integrated circuit for realizing the soft error tolerant method, which suppresses a decrease in the operation speed of the circuit and further increases the soft error attenuation capability. An error tolerant method in which a signal including a soft error generated by a logic circuit unit is attenuated by a pass transistor and then masked by a Schmitt trigger circuit, and the logic circuit unit and a path electrically connected to the logic circuit unit A semiconductor integrated circuit including a transistor and a Schmitt trigger circuit electrically connected to the pass transistor is provided. [Selection] Figure 1

Description

  The present invention relates to an error tolerant method and a semiconductor integrated circuit capable of executing the method.

  Errors that occur in a semiconductor integrated circuit can be classified into soft errors and hard errors. A hard error is an error caused by the structure of the semiconductor integrated circuit itself, and once it occurs, the signal value continues to be errored semipermanently. On the other hand, a soft error is an error that occurs temporarily during the operation of the semiconductor integrated circuit although the configuration of the semiconductor integrated circuit is normal, and recovers to its normal state over time. To do. Soft errors occur when, for example, radiation such as alpha rays or neutrons emitted from a semiconductor integrated circuit in a space or a package enclosing VLSI collides with VLSI. It tends to occur on memory.

  As a technique relating to soft error countermeasures (hereinafter referred to as “soft error tolerant”), for example, the following Non-Patent Document 1 discloses a latch circuit in a semiconductor integrated circuit having a logic circuit portion and a latch circuit portion connected to the logic circuit portion. A technique is disclosed in which a latch structure with a doubled portion is provided.

  Non-Patent Document 2 below discloses a logic circuit unit and a first delay circuit that delays the output of the logic circuit unit by a delay time δ (where δ is the maximum time affected by a soft error). And a second delay circuit that is delayed by a delay time 2δ, an output of the logic circuit section, an output of the first delay circuit and an output of the second delay circuit, and a majority circuit that makes a majority decision, and an output of the majority circuit A technology relating to a semiconductor integrated circuit having a latch circuit portion for storing the signal is disclosed.

  Further, the following Non-Patent Document 3 includes a logic circuit unit, a plurality of pass transistors connected to the logic circuit unit, and a latch circuit unit connected via the pass transistors. A technique for attenuating a soft error generated in the section is described.

M.M. Omana, D.H. Rossi, C.I. Metra, “Novel Transient Fault Hardened Static Latch”, ITC, pp 886-892, 2003. Nicolidis, “Time Redundancy-Based Soft-Error Tolerance to Rescue Nanometer Technologies”, Proc. IEEE VLSI Test Symp. Pp 86-94, 1999 J. et al. Kumar, Mehdi B. et al. Tahoori, “Use of pass transistor logic to minimize the impact of soft errors in comboir citrics”, Workshop on Systems Effects.

  However, although the technique described in Non-Patent Document 1 can prevent a soft error that has occurred in the latch unit, it cannot prevent a soft error that has occurred in the logic circuit unit.

  In the technique described in Non-Patent Document 2, it is necessary to increase the clock cycle by 2δ, which may reduce the operation speed of the circuit. Although this technique uses a majority circuit, there is a problem that the circuit is complicated and has a large area.

  Further, the technique described in Non-Patent Document 3 has a limit in the ability to be attenuated by the pass transistor, and a problem remains in the ability when a large soft error pulse is generated.

  Accordingly, the present invention provides a soft error tolerant method useful for a logic circuit unit and a semiconductor integrated circuit that realizes the soft error tolerant method, and aims to increase soft error attenuation capability while suppressing a decrease in the operation speed of the circuit. To do.

  That is, an error tolerant method as one means for solving the above-mentioned problem is characterized in that a signal including a soft error generated by a logic circuit unit is attenuated by a pass transistor and further masked by a Schmitt trigger circuit. .

  Although not limited, it is also desirable to use an inverter type Schmitt trigger circuit as the Schmitt trigger circuit in this means.

  A semiconductor integrated circuit as another means for solving the above problems includes a logic circuit portion, a pass transistor electrically connected to the logic circuit portion, and a Schmitt trigger circuit electrically connected to the pass transistor. One of the characteristics is to have.

  Although not limited thereto, it is also desirable to have a latch circuit portion electrically connected to the Schmitt trigger circuit in this means, and a pass transistor arranged in parallel with the Schmitt trigger circuit. It is also desirable to have.

  As described above, the present invention is a soft error tolerant method useful for a logic circuit unit and a semiconductor integrated circuit that realizes the soft error tolerant method, and can further increase the soft error attenuation capability while suppressing a decrease in the operation speed of the circuit. .

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention can be implemented in many different forms and is not limited to the following embodiments and examples.

(Embodiment 1)
FIG. 1 is a functional block diagram of the semiconductor integrated circuit according to the present embodiment.
As shown in FIG. 1, the semiconductor integrated circuit 1 according to this embodiment includes a logic circuit unit 2, a soft error tolerant circuit unit 3 connected to the logic circuit unit, and a latch connected to the soft error tolerant circuit unit 3. And a circuit unit 4.

  The logic circuit unit 2 is a circuit unit for performing calculation based on input data and outputting the result. For example, the logic circuit unit 2 combines an AND gate, an OR gate, a NOT gate, a NAND gate, and the like. Of course, the logic circuit 2 may have a latch circuit.

  The soft error tolerant circuit unit 3 is a circuit unit 3 for correcting a soft error that occurs in the logic circuit unit 2. Specifically, for example, as shown in FIG. And a Schmitt trigger circuit 32.

  The pass transistor 31 is a transistor that connects the logic circuit unit 2 and the Schmitt trigger circuit 32 via the source / drain regions in the transistor, and is not limited, but according to the present embodiment as shown in FIG. The pass transistor 31 includes an NMOS transistor 311 and a PMOS transistor 312, and the source / drain region in each transistor is electrically connected to the source / drain region in the other transistor. Note that the gate of the NMOS transistor 311 is grounded to the external power source Vcc, the gate of the PMOS transistor 312 is grounded, and the gates of both transistors are in the on state. The pass transistor 31 in the present embodiment is a combination of the NMOS transistor 311 and the PMOS transistor 312, but is not limited as long as it exhibits the above-described functions. For example, only the NMOS transistor or only the PMOS transistor is used. It may be present and is not limited to this embodiment.

  The Schmitt trigger circuit 32 is a circuit mainly used to remove noise at the rise and fall of a signal. Although not limited, the Schmitt trigger circuit 32 is connected in series with a common source / drain region as shown in FIG. An NMOS transistor 321 and a PMOS transistor 322 connected to each other, an NMOS transistor 323 and a PMOS transistor 324, and an inverter 327 electrically connected to source / drain regions 325 and 326 common between these transistors, The output of the inverter 327 is connected to the gates of the NMOS transistor 323 and the PMOS transistor 324. The non-common source / drain of the NMOS transistors 321 and 323 are grounded, and the non-common source / drain of the PMOS transistors 322 and 324 are connected to Vcc. In this embodiment, the output of the inverter 327 is also the output of the Schmitt transistor circuit.

  An example of the Schmitt trigger circuit 32 of the present embodiment is shown in FIG. 2, but for example, a configuration as shown in FIG. 3 can be adopted, and is not limited to the configuration described in the present embodiment. Absent. The Schmitt trigger circuit 32 shown in FIG. 3 includes a plurality of PMOS transistors 3211 and 3212 and a plurality of NMOS transistors 3213 and 3214 which are connected in series in order with a common source / drain region, a plurality of PMOS transistors 3211, A PMOS transistor 3216 connected to a common source / drain region 3215 of 3212 and an NMOS transistor 3218 connected to a common source / drain region 3217 of a plurality of NMOS transistors 3213 and 3214 are configured. Note that the Schmitt trigger circuit 32 in this figure has a source / drain region 3219 between the PMOS transistor 3212 and the NMOS transistor 3213 as an output, and is connected to the gates of the PMOS transistor 3216 and the NMOS transistor 3218 described above.

  Here, the principle of noise removal by the Schmitt trigger circuit 32 will be described with reference to FIG. In general, a digital circuit determines and handles whether an input signal is “1” or “0” (“High”, “Low”, “high potential”, or “low potential” depending on the expression). Specifically, “1” is determined for an input of a predetermined voltage or higher, and “0” is determined for an input signal lower than the predetermined voltage (this predetermined voltage is referred to as “threshold voltage”). However, noise is usually added to these input signals, and this becomes a significant problem at voltages near the threshold voltage. That is, depending on the magnitude of the noise, the input signal that should originally be “1” becomes “0” due to noise, or the input signal that should originally be “0” becomes “1” (FIG. 4 (A)). On the other hand, the Schmitt trigger circuit has two threshold voltages to give directionality to the judgment on the input signal. According to this circuit, when the input signal is equal to or higher than Vth + and is determined to be “1”, “1” is maintained even if the input signal falls below Vth +, and “0” is not determined unless the input signal is equal to or lower than Vth−. Thus, noise near the threshold voltage can be prevented (see FIG. 4B).

  The latch circuit unit 4 is a circuit unit for holding the output from the soft error tolerant circuit unit 3 based on the logic circuit unit 2, and is not limited as long as the output can be stored. An example of the circuit configuration is shown in FIG. 5, for example. The latch circuit 4 desirably stores output temporarily for data processing. However, the latch circuit 4 may be omitted if the latch circuit 4 has a configuration that does not require latching such as direct input to another logic circuit unit.

  Next, an error tolerant method using the semiconductor integrated circuit according to the present embodiment will be described. First, it is assumed that a soft error has occurred in the logic circuit unit 2. Then, a signal including the soft error (hereinafter referred to as “soft error signal”) is input to the pass transistor 31 and the voltage is attenuated. The pass transistor 31 normally outputs the signal from the logic circuit unit 2 to the Schmitt trigger circuit 32 as it is. However, when a temporary soft error is input, the magnitude of the input soft error is attenuated, and the Schmitt The trigger circuit 32 can be within a range of noise that can be masked (the attenuation factor of the pass transistor is approximately 10%). The Schmitt trigger circuit 32 can mask the soft error based on the input signal in which the soft error is attenuated. More specifically, in the pass transistor 31, for example, as shown in FIG. 6, the initial magnitude of the soft error generated in the logic circuit unit 2 sometimes exceeds the threshold voltage (Vth +). However, the voltage of the soft error can be attenuated until the noise can be masked by the pass transistor 31, and can be suppressed to a range that can be masked by the Schmitt trigger circuit. By doing in this way, it becomes a soft error tolerant method useful for the logic circuit unit according to the present embodiment, and it is possible to further increase the soft error attenuation capability while suppressing a decrease in the operation speed of the circuit. In particular, according to the present circuit, since there is no need to provide a delay circuit as in the prior art, the operation speed is not reduced, and a majority circuit is not required, and the semiconductor integrated circuit does not increase in area. Needless to say, when a soft error does not occur in the logic circuit unit 2, the output signal from the logic circuit unit 2 can be output to the latch circuit unit 4 as it is.

(Embodiment 2)
The present embodiment is substantially the same as that of the first embodiment, except that the soft error tolerant circuit unit 3 has a function as a latch. FIG. 7 shows a functional block diagram of the semiconductor integrated circuit 1 according to the present embodiment, and FIG. 8 shows an example of an equivalent circuit of the soft error tolerant circuit unit 3 according to the present embodiment.

  As shown in FIG. 7, the soft error tolerant circuit unit 3 of the semiconductor integrated circuit according to the present embodiment has a latch function, and is configured integrally with the latch circuit unit 4 in the first embodiment. Different.

  As shown in FIG. 8, the soft error tolerant circuit unit 3 according to the present embodiment is substantially the same as the example of the first embodiment shown in FIG. 2, but the pass transistor 31, the Schmitt trigger circuit 32, and the Schmitt trigger. And a pass transistor 33 connected in parallel with the circuit 32.

  The pass transistor 31 has substantially the same configuration as that of the first embodiment, but the gate of the NMOS transistor 321 is connected to the clock signal clk, and the gate of the PMOS transistor 322 is connected to the inverted clock signal inverted from the clock signal clk. Is different. That is, the pass transistor 31 can control the input to the Schmitt trigger circuit 32 or the pass transistor 33 arranged in parallel with the Schmitt trigger circuit 32 in this way.

  Further, the pass transistor 33 connected in parallel to the Schmitt trigger circuit 32 in the present embodiment has the same configuration as the pass transistor 31 in the preceding stage, but the signal input to the gate is different. Specifically, an inverted clock signal is input to the gate of the NMOS transistor 331 and the clock signal clk is input to the gate of the PMOS transistor 332. As a result, when the gate of the pass transistor 31 in the previous stage is in the on state, it is in the off state, and when it is in the off state, it is in the on state.

  Of course, the Schmitt trigger circuit 33 is not limited to the example of FIG. 8 as in the above-described embodiment, and may be configured as shown in FIG. 9, for example. The Schmitt trigger circuit 32 shown in FIG. 9 is substantially the same as the Schmitt trigger circuit shown in FIG. 4, but is connected in series with a common source / drain region on the output side of the Schmitt trigger circuit shown in FIG. The difference is that the PMOS transistor 3220 and the NMOS transistor 3221 are arranged. The non-common source / drain region of the PMOS transistor 3220 is provided at Vcc, and the non-common source / drain region of the NMOS transistor 3221 is provided. A common source / drain region 3222 is the output of the Schmitt trigger circuit 33.

  As described above, the semiconductor integrated circuit according to the present embodiment has not only the same effects as in the first embodiment, but also a separate pass transistor 33 in parallel between the pass transistor 31 and the Schmitt trigger circuit 32. In addition, an error mask function can be provided by forming a loop, and a latch function can be achieved by configuring a latch circuit. Thereby, the area can be further reduced.

It is a figure which shows the functional block of the semiconductor integrated circuit which concerns on embodiment. It is a figure which shows the detailed circuit of the pass transistor which concerns on embodiment, and a Schmitt trigger circuit. It is a figure explaining operation | movement of the Schmitt trigger circuit which concerns on embodiment. It is a figure which shows the example of the other structure of the Schmitt trigger circuit which concerns on embodiment. It is a figure which shows the detailed circuit of the latch circuit which concerns on embodiment. It is a figure explaining operation | movement of a pass transistor and a Schmitt trigger circuit. 6 is a functional block diagram of a semiconductor integrated circuit according to a second embodiment. FIG. It is a figure which shows the detailed circuit of a pass transistor and a Schmitt trigger circuit. It is a figure which shows the other example of a Schmitt trigger circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit, 2 ... Logic circuit part, 3 ... Error tolerant circuit part, 4 ... Latch circuit part, 31 ... Pass transistor, 32 ... Schmitt trigger circuit, 33 ... Pass transistor, 311, 321, 323 ... NMOS transistor, 312 322 324 PMOS transistor

Claims (5)

  An error tolerant method in which a signal including a soft error generated by a logic circuit unit is attenuated by a pass transistor and further masked by a Schmitt trigger circuit.   2. The error tolerant method according to claim 1, wherein an inverter type Schmitt trigger circuit is used as the Schmitt trigger circuit. A logic circuit section;
A pass transistor electrically connected to the logic circuit unit;
A Schmitt trigger circuit electrically connected to the pass transistor.   4. The semiconductor integrated circuit according to claim 3, further comprising a latch circuit portion electrically connected to the Schmitt trigger circuit.   4. The semiconductor integrated circuit according to claim 3, further comprising a pass transistor arranged in parallel with the Schmitt trigger circuit.