WO2007108163A1

WO2007108163A1 - Frequency converting circuit

Info

Publication number: WO2007108163A1
Application number: PCT/JP2006/322685
Authority: WO
Inventors: Kazuhisa Ishiguro; Yoshiaki Takahashi
Original assignee: Niigata Seimitsu Co., Ltd.; Ricoh Co., Ltd.
Priority date: 2006-03-22
Filing date: 2006-11-08
Publication date: 2007-09-27
Also published as: JP2007258861A; CN101401298A

Abstract

A single constant current source (IO) is connected, in a common source fashion, to first and second differential amplifiers (10I,10Q) that perform a differential amplification based on the same input signal. The single constant current source (IO) is used to drive both of the differential amplifiers (10I,10Q), thereby establishing an appropriate gain of each of the differential amplifiers (10I,10Q) so as to obtain a desired noise factor (NF). Additionally, the arrangement in which these differential amplifiers (10I,10Q) operate only by use of the single constant current source (IO) can suppress the increase of current consumption though the two differential amplifiers are existent.

Description

Frequency conversion circuit

Technical field

The present invention relates to a frequency conversion circuit, and is particularly suitable for use in an IQ mixer constituting a quadrature modulator. Thread

Rice field 1

Background art

book

Conventionally, as a frequency conversion circuit configured on a MOS integrated circuit, one using a gilbert cell (for example, see Patent Document 1) or one using a MOS switch is known.

Patent Document 1: Japanese Laid-Open Patent Publication No. 10 — 2 0 0 3 3 7 ^

In general, the IQ mixer that constitutes the quadrature modulator can be composed of a Gilbert cell mixer that combines multiple Gilbert cells, or a passive mixer that combines a few MOS switches. Fig. 1 is a diagram showing the configuration of a conventional gilt cell type IQ mixer. Fig. 2 is a diagram showing the configuration of a conventional passive I Q mixer.

As shown in Figure 1, Giruba Toseru type IQ mixer is provided with two Girupa Toseru 5 0 ,, 5. 0 _Q. In the Gilbert cell 50 for in-phase signal (I signal), the input signals V, _N , V, _N -(— are out of phase with each other by 180 degrees. The first differential amplifier 5 1, which is composed of a pair of differential pair transistors (M 1, M 2,), is disposed between the input terminal pair of the first differential amplifier 5 1. The first differential amplifier 5 1, is driven by a first constant current source I i. In addition, two differential pair transistors are connected between the input terminal pairs of the local signals V 1, V 2, — that are 180 degrees out of phase with each other. A double-balanced first mixer circuit 5 2 made up of registers {(M 3 j, M 4,), (Μ 5,, Μ 6,}) is arranged.

Specifically, the first mixer circuit 5 2 is configured as follows. That is, the drains of one differential pair transistor (Μ 3 _Ι; Μ 4 j) and the drains of the other differential pair transistor (Μ 5, 6,) are connected in common. . In addition, the gate of transistor と 3 and the gate of transistor Μ6i are connected in common, and the inverted low power signals V,-are input to this common gate. Further, the gate of the transistor M 4 j and the gate of the transistor M 5, are connected in common, and the local signal V _t is input to this common gate. The sources of the transistors M 3!, M 4 j, M 5 j and M 6! Are connected to the power supply VDD. .

'The first differential amplifier 5 1 is specifically configured as follows. That is, one transistor M l, its drain is connected to the common drain of one differential pair transistor (M 3, M 4,), and its source is the first constant current source I! It is connected to the. Input signals V and _N are input to the gate. The other transistor M 2 has its drain connected to the common drain of the other differential pair transistor (M 5, M 6!) And its source connected to the first constant current source I. . Inverted input signals V and _N — are input to the gate.

Similarly, in Girupa Toseru 5 0 _Q for the quadrature signal (Q signal), the input signal V _{1 N} in a shifted state-of-phase 1 8 0 degrees with respect to each other, V _{1 N} - between the input terminal pair, 1 A second differential amplifier 5 1 _Q composed of a pair of differential pair transistors (M 1 _Q , M 2 _Q ) is arranged. The second differential amplifier 5 1 _Q is driven by the _second constant current source I ₂ . In addition, there are two differential pair transistors between the input terminal pairs of local signals V _Q and V _Q — that are 180 degrees out of phase with each other. A double-balanced second mixer circuit 52 _Q consisting of {{M 3 _Q , M 4 _Q ), (M 5 _p , M 6 _Q )} is arranged.

Specifically, the second mixer circuit 5 2 _Q is configured as follows. That is, the drains of one differential pair transistor (M 3 _Q , M 4 _Q ) and the drains of the other differential pair transistor (M 5 _Q , M 6 _Q ) are connected in common. ing. In addition, the gate of the transistor M 3 _{Q and} the gate of the transistor M 6 _Q can be connected in common, and the inverted low power signal V _Q — is input to this common gate. In addition, the gate of the transistor M 4 Q and the gate of the transistor M 5 _Q are connected in common, and the local signal V _Q is input to this common gate. The sources of the transistors M 3 _Q , M 4 _Q , M 5 _Q , and M 6 _Q are connected to the power supply VDD. , '

'Moreover, the second differential amplifier 5 1 _Q is specifically configured as follows. That is, one transistor M 1 _Q has its drain connected to the common drain of one differential pair transistor (M 3 _Q , M 4 _Q ) and its source connected to the second constant current source I _2. ing. Input signals V and _N are input to the gate. The other transistor M 2 _Q has its drain connected to the common drain of the other differential pair transistor (M 5 _Q , M 6 _Q ) and its source connected to the second constant current source I ₂ Has been. The inverted input signal V _IN — is input to the gate.

In the Gilbert cell type IQ mixer configured as described above, the input signals V _IN and V _IN — are input to the first and second differential amplifiers 5 1 and 5 1 _Q , and their outputs are They are entered in the first and second mixer circuits 5 2 There 5 2 _Q. Then, in-phase signals I and I — having a phase difference of 180 degrees are extracted from the output of the first mixer circuit 5 2, and the phases of the signals from the output of the second mixer circuit 5 2 _Q are 1 8. Quadrature signals Q and Q— differing by 0 degrees are extracted. In addition, as shown in FIG. 2, the noisy IQ mixer includes two switch circuits 60, 6 0 «3. In the common-mode signal switch circuit 60, the input signal V _IN is input to the first and second switches SW 1!, SW 2. The input signal V _IN inverted input signal phase situations that near shifted 1 8 0 degrees with respect to V _IN - third Oyopi fourth sweep rate Tutsi SW 3,, SW 4! Is entered.

The second and third switches SW 2 and SW 3 are controlled to be turned on and off by the local signal V. Also, 1st and 4th switch SW 1! , SW 4, ONZO FF is controlled by the inverted local signal V 1, which is 180 degrees out of phase with the local signal V 1. The outputs of the first and third switches SW 1, SW 3 are mixed and the second and fourth switches SW 2,! , SW 4, output is mixed and extracted as in-phase signals I and I. Also, a quadrature signal switch circuit 60. In this case, input signals V and _N are input to the first and second switches SW 1 _Q and SW 2 _Q , respectively. The inverting input signal V _IN in phase to the input signal V _IN is in a shifted state 1 8 0 degree - are input to the third Oyopi fourth sweep rate Tutsi SW 3 _Q, SW 4 _Q .

The second and third switches SW 2 _Q and SW 3 _Q are ON / OFF controlled by the local signal V _Q. The first Oyopi fourth sweep rate pitch SW 1 _Q, SW4 _Q is inverted local signal V _Q of phase relative to the local signal V _Q is in 1 8 0 degrees out of state - the Yotsute ON / OFF is controlled. The outputs of the 1st and 3rd switches SW 1 _Q and SW 3 _Q are mixed and the 2nd and 4th switches SW 2 _Q and SW 4 Q Output is mixed and extracted as quadrature signals Q and Q- Disclosure of the invention

In the case of a Gilbert cell type IQ mixer as shown in Fig. 1, the gain is determined by the transconductance gm of the differential amplifiers 51 and 51 _Q and the load resistance. Therefore, it is possible to set an appropriate gain to obtain a desired NF (noise figure). However, to extract the in-phase and quadrature signals, two Gilbert cells 5 0 and 5 0. There is a problem that requires 2 times more current and consumption than a simple mixer circuit.

On the other hand, in the case of a passive type 'I Q mixer as shown in Fig. 2, the current consumption is zero because no direct current flows through the mixer section. However, since it does not have a differential amplifier that can control the gain, the gain is almost 1 (0 [dB]). Therefore, the desired NF could not be obtained, and there was a problem that the NF deteriorated.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a frequency conversion circuit that consumes less current and can improve the noise figure NF. Chiru.

In order to solve the above-described problem, in the frequency conversion circuit of the present invention, one constant current source is provided for the first differential amplifier and the second differential amplifier that perform differential amplification operation based on the same input signal. Are connected in common by a common source, and both differential amplifiers are driven by a single constant current source.

Further, a frequency conversion circuit is configured by a combination of the first and second differential amplifiers and the first and second switch circuits connected to these outputs. The switch circuits may be driven based on local signals that are 90 degrees out of phase with each other. According to the present invention configured as described above, the first and second differential amplifiers In order to obtain a desired noise figure NF, it is possible to set an appropriate gain. However, since these differential amplifiers operate with only one constant current source, it is possible to suppress an increase in current consumption while having two differential amplifiers. Brief Description of Drawings

FIG. 1 is a diagram showing the configuration of a conventional Gilpa single cell type IQ mixer. FIG. 2 is a diagram showing the configuration of a conventional passive IQ mixer.

FIG. 3 is a diagram showing a configuration example of the frequency conversion circuit according to the present embodiment. FIG. 4 is a diagram illustrating an operating current of the frequency conversion circuit according to the present embodiment. FIG. 5 is a diagram illustrating another configuration example of the frequency conversion circuit according to the present embodiment. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a diagram illustrating a configuration example of the frequency conversion circuit according to the present embodiment. As shown in FIG. 3, the frequency conversion circuit of this embodiment has two differential amplifiers 1 0 and 1 0. Per cent spare two and a sweep rate latch circuit 2 0 have 2 0 _Q.

The first differential amplifier 10 0 is composed of a pair of differential pair transistors (M l,, M 2), which are input from the two input terminals 1, 2, and whose inputs are 180 degrees different from each other. The differential amplification operation of the signals V _IN and V _IN — The second differential amplifier 10 0 _Q consists of a pair of differential pair transistors (M 1 _Q , M 2 _Q ). Differential amplification operation is performed on the signals V _{1 N} , V, _N — input from the two input terminals 1 and 2 that are the same as the differential amplifier 10.

The first differential amplifier 10 is configured as follows. That is, One transistor M l, whose drain is the first switch circuit 2 0! Are connected to the first and second switches SW 1, SW 2, and the source is a constant current source I. It is connected to the. The input terminal 1 for input signals V and _Ν is connected to the gate. The other transistor Μ 2 has its drain connected to the third and fourth switches SW 3, SW 4 J of the first switch circuit 20, and its source connected to the constant current source I. It is connected to the. The input terminal 2 of the inverted input signal V _IN — is connected to the gate.

The second differential amplifier 10 _Q is configured as follows. That is, the drain of one transistor M 1 _Q is connected to the first and second switches SW 1 _Q and SW 2 _Q of the second switch circuit 20 _Q , and the source is Constant current source I. It is connected to the. Input terminal 1 for input signals V and _N is connected to the gate. The other 'DOO La Njisuta M 2 _Q, the drain • emission third Oyopi fourth sweep rate Tutsi SW 3 _Q of the second sweep rate Tutsi circuit 2 0 _Q, is connected to S W4 _Q, a source Is the constant current source I. It is connected to the. The input terminal 2 of the inverted input signal V _IN — is connected to the gate.

Thus, in this embodiment, the first and second differential amplifiers 10! , 10 _Q 4 transistors M l, M 2,, M 1 _Q , M 2. The common source is connected to one common current source I. Are connected in common. The first differential amplifier 10 and the second differential amplifier 10 _Q are connected to one constant current source I. It is trying to drive with.

The first switch circuit 20 includes first to fourth switches SW 1 to SW 4. The first switch SW 1 and the third switch SW 3 are connected between the output of the first differential amplifier 10 and the output terminal 3 of the common-mode signal I. . As a result, the outputs of the transistors M 1, M 2, constituting the first differential amplifier 10, are mixed and taken out from the output terminal 3 as the in-phase signal I. It is summer. In addition, the first switch SW 1 and the first switch The output of switch 3 of switch 3 is connected to power supply VDD via resistor R 1.

The second switch and the fourth switch SW4 are connected between the output of the first differential amplifier 10 and the output terminal 4 of the inverted common-mode signal I and the first switch SW4. The outputs of the transistors ΙΟΙ,,, M 2, which constitute the differential amplifier 10, are mixed and taken out from the output terminal 4 as the inverted common-mode signal I. The second switch SW 2! When the fourth sweep rate Tutsi SW4, the output of which is connected to the power source VDD through a resistor R 2 _t.

Here, the second switch SW 2 and the third switch SW 3 are driven by a local signal V input from one local input terminal 5, and the ON / OFF thereof is controlled. The Also, the 1st and 4th switches SW 1! , SW 4, is the local signal V! Is driven by a reversing port ^ "cal signal V ^ — whose phase is shifted by 180 degrees relative to the ON / OFF state. The inversion local signal V 1, — Input from the local input terminal 6 of.

Similarly, the second sweep rate latch circuit 2 0 _Q includes first to fourth sweep rate pitch SW 1 _{_Q} ~SW4 _Q. The first sweep rate pitch SW 1 _Q and the third sweep rate pitch SW '3 _Q is connected between the output terminal 7 and output quadrature signal Q of the second differential amplifier 1 0 _Q. As a result, the outputs of the transistors M 1 _Q and M 2 _Q constituting the second differential amplifier 10 _Q are mixed and taken out from the output terminal 7 as the quadrature signal Q. It is summer. The outputs of the first switch SW 1 _Q and the third switch SW 3 _Q are connected to the power supply VDD via the resistor R 1 _Q.

2nd switch SW 2 _Q and 4th switch SW4. Is connected between the second differential amplifier 1 0 _Q output and the inverted quadrature signal Q- output terminal 8 of the preparative transistors M 1 _Q constituting a second differential amplifier 1 0 _Q, M 2 _Q issue The force is mixed and taken out from output terminal 8 as inverted quadrature signal Q—. The outputs of the second switch SW '2 _Q and the fourth switch SW 4 _Q are connected to the power supply VDD via the resistor R 2 _Q. The second switch SW 2 is here. The third switch SW 3 Q is driven by a local signal V _Q input from one local input terminal 9 and its ONZOFF is controlled. The first and fourth switches SW 1 _Q> SW 4 _Q are driven by the inverted local signal νά— which is 180 degrees out of phase with the local signal V _Q. OFF is controlled. The inverted local signal V _Q — is input from the other local input terminal 1 0.

FIG. 4 is a diagram showing the operating current of the frequency conversion circuit according to the present embodiment configured as described above. As described above, the MOS switch circuit 2 0 after the differential amplifier 10 0 1 0 _Q ! , 2 0 _Q are connected, and the switch circuit 2 0,, 2 0 _Q is driven by local signals that are 90 degrees out of phase (V! And V _Q , V! — And V _Q — are The phase of the phase difference is 90 degrees.). Differential amplifiers 10,, 10 _Q transistors M l J, 2,, M 1 _Q , M 2 _Q Figure 4 shows. ■

In FIG. 4, I, is the current required to produce the in-phase signals I, I — using the first differential amplifier 10 0, and I _q is the second differential amplifier 10 _Q. This is the current required to produce the direct signals Q and Q-. Here, I i = I _q . In this case, a constant current source I connected to these differential amplifiers 10,, 10 _Q by a common source. Required current I. That is, the common current I required in the circuit of Figure 3. Is

I 0 = ^ 2 I i

It becomes. On the other hand, the signal current I ₄ required in the conventional example of FIG.

1 ₄ = 1 1 + 1 2 = 1! + 1, = 2 1; It becomes. Therefore, in this embodiment, an IQ mixer can be realized with a current consumption of about 70% of the conventional example. '

In this embodiment, since the gains of the differential amplifiers 10,, 10 _Q can be set so as to secure a desired noise figure NF, the passive type I as in the conventional example shown in FIG. Q It is possible to suppress the deterioration of the noise figure NF, which is a problem with mixers.

In the above embodiment, the common source point of the differential amplifiers 10 and 10 _Q is a constant current source I. Although it is connected to the virtual ground point via the, it is not limited to this. Input signal V! N, V! _Since the phase of _N — is 180 degrees different, it may be connected to ground. In this case, low voltage operation is improved. FIG. 5 is a diagram showing another configuration example of the frequency conversion circuit according to the present embodiment. The frequency conversion circuit shown in FIG. 5 shows a configuration example when the input signal itself is composed of a combination of an in-phase signal and a quadrature signal. In FIG. 5, components having the same functions as those shown in FIG. 3 are denoted by the same reference numerals. The frequency conversion circuit shown in Fig. 5 has four differential amplifiers 10 0 1 0 _Q , 1 1,, 1 1 _Q and 4 'switch circuits 2 0! Has SOQSISIQ. '.'

The first differential amplifier 10 0 is composed of a pair of differential pair transistors (M l!, M 2 J, which are input from the two input terminals 1 and 2 and have a phase of 180 degrees relative to each other. Performs differential amplification of different input common-mode signals V, _N I, V, _N I — The second differential amplifier 10 0 _Q is a pair of differential pair transistors (M 1 _Q , M 2 _Q ) and performs differential amplification of input quadrature signals V _IN Q and V _IN Q— that are input from the two input terminals 1 ′ and 2 ′ and that are 180 degrees out of phase with each other. The differential amplifier 1 1, 3 consists of a pair of differential pair transistors (M 3,, M 4,), and is input from the same two input terminals 1 and 2 as the first differential amplifier 1 0, Differential amplification of the common-mode signals V, _N I, V, _N I — The fourth differential amplifier 1 1 _Q is a pair of differential transistors (M 3 _Q , M

4 _Q ) and the second differential amplifier 1 0 _Q , the same as the two input terminals 1,, 2

The differential signals V, _N Q, V, _N Q— are input from quadrature signals. The first differential amplifier 10 is configured as follows. That is — the transistor M l! The drain is connected to the first and second switches SWIH and SW 2 M of the first switch circuit 20, and the source is the constant current source I. It is connected to the. The input terminal 1 of the input common-mode signal V _IN I is connected to the gate. The other transistor M 2! Is connected to the third and fourth switches SW S! I and SWA! I of the first switch circuit 2.0, and the source is the constant current source I. It is connected to the. The input terminal 2 of the inverting input common-mode signals V and _N I — is connected to the gate.

The second differential amplifier 10 _Q is configured as follows. Ie, one bets transistor M 1 _Q, the drain is connected to the sweep rate pitch SW 1 _{Q 1,} SW 2 _{Q 1} first and second of the second sweep rate latch circuit 2 0 _Q The source is constant current source I. It is connected to the. Input terminals 1 and of the input quadrature signals V and _N Q are connected to the gate. The other transistor M2. The drain is connected to the third and fourth switches SW 3 _{Q 1} and SW4 _{Q 1} of the second switch circuit 20 _Q , and the source is the constant current source I. It is connected to the . Inverted input quadrature signals V and _N Q— input terminals 2 'are connected to the gate.

3rd differential amplifier 1 1! Is structured as follows. That is, the first transistor M 3 has its drain connected to the first and second switches SW 1 _{I 2} and SW 2 _{I 2} of the third switch circuit 21, Is the constant current source I. It is connected to the. The input terminal 1 for input common-mode signals V and _N I is connected to the gate. The other transistor M 4 is connected to the third and fourth switches SW 3 J ₂ of the third switch circuit 21. , SW 4 _{I 2} is connected and the source is constant current source I. It is connected to the. The input terminal 2 of the inverting input common mode signal V _IN I is connected to the gate.

The fourth differential amplifier 1 1 _Q is configured as follows. In other words, the drain of one transistor M 3 _Q is the fourth switch circuit 2 1. The first and second switches SW 1 _{Q 2} and SW 2 _{Q 2} are connected to the constant current source I. It is connected to the. The input terminal 1 'for input quadrature signals V and _N Q is connected to the gate. Also, the other transistor M 4 _Q, the drain is connected the fourth sweep rate latch circuit 2 1 3 Oyopi fourth sweep rate Tutsi of _Q SW 3 _{Q 2,} the SW 4 _{Q 2,} source Constant current source I. It is connected to the . Inverted input quadrature signals V and _N Q input terminals 2 'are connected to the gate. .

Thus, in the frequency conversion circuit shown in FIG. 5, the eight transistors M 1, 1 1 to 4 _Q constituting the first to fourth differential amplifiers 10 0 to 10 _Q , 1 1. , M 2 _,, M 3 _,, M 4 _,, M 1 _Q , M 2 _Q , M 3 _Q , M 4. The common source is connected to one common current source I. Are connected in common. The first to fourth differential amplifiers 10 0,, 10 0 _Q , 1 1 _,, 1 1 _Q are connected to one constant current source I. It is trying to drive with.

The first switch circuit 20 includes first to fourth switches SW1H to SW4M. The first switch SW 1 and the third switch SW 3, i are connected between the output of the first differential ft amplifier 10 and the output terminal 3 of the first common-mode signal I i. It is connected. As a result, the outputs of the transistors M 1, M 2 constituting the first differential amplifier 10 are mixed and taken out from the output terminal 3 as the first in-phase signal. It is getting ready. The outputs of the first switch SW 1 M and the third switch SW 3 are connected to the power supply V DD via the resistor R 1.

In addition, the second switch SW 2 H and the fourth switch SW 4 are connected to the first switch SW 2 H. It is connected between the output of the differential amplifier 10, and the output terminal 4 of the first in-phase signal I i—. As a result, the outputs of the transistors M 1 and M 2! Constituting the first differential amplifier 10 are mixed and taken from the output terminal 4 as the first inverted common-mode signal —. It is getting out. The outputs of the second switch SW 2 M and the fourth switch SW 4 are connected to the power supply VDD via a resistor R 2!.

Here, the second switch S W S! I and the third switch S W S! I have a local signal V! It is driven by the ONZOF F. The first and fourth switches SW 1 J α and SW 4 H are driven by the inverted local signal V 1, − which is 180 degrees out of phase with the local signal V 1, and ON / OFF is controlled. The inverted local signal V 1, − is input from the other local input terminal 6.

Similarly, the second switch circuit 20 _Q includes first to fourth switches SW 1 _Q _{1 to} SW 4 _{Q 1} . The first switch SW 1 _{Q 1} and the third switch SW 3 _{Q 1} are connected between the output of the second differential amplifier 10 _Q and the output terminal 7 of the first orthogonal signal. ing. As a result, the outputs of the transistors M 1 _Q and M 2 _Q constituting the second differential amplifier 10 _Q are mixed and the first quadrature signal Q! As a result, it comes out from the output terminal 7. The outputs of the _first switch SW 1 _{Q 1} and the third switch SW 3 _{Q 1} are connected to the power supply VDD via a resistor R 1 _Q.

In addition, the second switch SW 2 _{Q 1} and the fourth switch SW 4 _{Q 1} are connected to the output terminal of the second differential amplifier 10 _Q and the output terminal 8 of the first inverted orthogonal signal Q i—. Is connected between. As a result, the outputs of the transistors M 1 _{Q 1} and M 2 _Q constituting the second differential amplifier 10 _Q are mixed and output as the first inverted quadrature signal —. It is getting taken out of. In addition The outputs of 2 switch SW 2 _{Q 1} and 4th switch SW 4 _{Q 1} are connected to power supply VDD via resistor R 2 _Q.

Here, the second switch SW 2 _{Q 1} and the third switch SW 3 _{Q 1} are driven by the oral signal V _Q inputted from one oral input terminal 9, Its ONZOFF is controlled. The first and fourth switches SW 1 _{Q 1} and SW 4 _{Q 1} are driven by the inverted local signal VQ— which is 180 degrees out of phase with the local signal V _Q. The ON and OFF are controlled. The inverted inversion signal V _Q — is input from the other local input terminal 10 units.

Similarly, the third switch circuit 21, includes first to fourth switches SW 1, _{2 to} SW 4 _{I 2} . The first switch SW 1] ₂ and the third switch SW 3, ₂ are connected to the output of the third differential amplifier 11 1, the output terminal 3 of the _second common-mode signal I ₂ , and Connected between. As a result, the outputs of the respective transistors Μ 3, M 4, constituting the third differential amplifier 11 i are mixed and output from the output terminal 3 as the second in-phase signal I _2. It is getting taken out. The outputs of the first switch SW 1 _{I 2} and the third switch SW 3 _{I 2} are connected to the power supply VDD via a resistor R 3.

Also, the second switch SW 2 _{I 2} and the fourth switch SW 4 _{I 2} are the output terminals of the output of the third differential amplifier 1 1, and the second inverted common-mode signal I ₂ —. Connected between 4 '. As a result, the outputs of the transistors M 3, M 4, constituting the third differential amplifier 1 1, are mixed and the second inverted common-mode signal 1 ₂ — is output as the output terminal 4 'Is getting taken out of. The outputs of the _second switch SW 2 _{1 2} and the fourth switch SW 4 _{1 2} are connected to the power supply VDD via a resistor R 4.

Here, the second switch SW 2 _{I 2} and the third switch SW 3 _{1 2} are driven by the inverted local signals V 1, -2 input from one inverted local input terminal 5. The O NZ OFF is controlled. In addition, the first and fourth switches SW 1 _{I 2} and SW 4 ₁₂ are connected to the local signal V whose phase is shifted by 180 degrees with respect to the reversal opening signal V,-. Driven by〗, its O NZ OFF is controlled. The local signal V, is input from the other inverting power input terminal 6 ′.

Similarly, the fourth sweep rate latch circuit 2 1 _Q includes first to fourth sweep rate pitch SWIQ _₂ ~SW 4 _Q _2. The first switch SW 1 _{Q 2} and the third switch SW 3 _{Q 2} are connected between the output of the fourth differential amplifier 1 1 _Q and the output terminal 7 ′ of the _second quadrature signal Q ₂ Has been. As a result, the outputs of the transistors M 3 _Q and M 4 _Q constituting the fourth differential amplifier 1 1 _Q are mixed and output as the second quadrature signal Q ₂ to the output terminal 7 ′. It is getting taken out of. The outputs of the first switch SW 1 _{Q 2} and the third switch SW 3 _{Q 2} are connected to the power supply VDD through the resistor R 3 _Q. '

The second switch SW 2 _{Q 2} and the fourth switch SW 4 _{Q 2} are connected to the output terminal of the fourth differential amplifier 11 _Q and the output terminal 8 of the _second inverted quadrature signal Q ₂ —. 'Is connected between As a result, the outputs of the transistors M 3 _{Q 2} and M 4 _{Q 2} constituting the fourth differential amplifier 1 1 _Q are mixed and output as the second inverted quadrature signal Q ₂ —. 8 'is getting taken out of. The outputs of the _second switch SW 2 _{Q 2} and the fourth switch SW 4 _{Q 2} are connected to the power supply VDD via the resistor R 4 _Q.

Here, the second switch SW 2 _{Q 2} and the third switch SW 3 _{Q 2} are driven by the inverted local signal V _Q — input from one of the inverted local input terminals 9 ′. The ON / OFF is controlled. The first and fourth switches SW 1 _{Q 2} and SW 4 _{Q 2} are inverted local signals V. Local signal V with phase shifted by 180 degrees relative to 1. The ON / OFF is controlled. The local signal V _Q is Input from 1 0 '.

When the frequency conversion 0 path is configured as shown in FIG. 5 above, each of the differential amplifiers 10,, 10 _Q) 1 1 1 1 1 _Q is connected to the constant current source I by a common source. Required current I. That is, the common current I required in the circuit of Figure 5. Is

I ₀ = 2 2 I i = 2 I i

It becomes. On the other hand, when the Configure the IQ mixer at Yo I Do normal Giruba Toseru the conventional example, since the circuit of Figure 1 is two required signal current 1 ₄ necessary,

I 4 = 2 (I! + I ₂ ) = 4 I _;

It becomes. Therefore, in this embodiment, an IQ mixer can be realized with a current consumption of 50% of the conventional example.

In the frequency conversion circuit of Fig. 5, eight M l M 2,, M 3,, M 4 _,,, M 1 _Q , M 2 _Q , M 3 _Q , M4 _Q are all common sources. One constant current source I. The example of connecting to is explained, but it is not always necessary to have all eight as common sources.

In the above embodiment, the example in which the frequency conversion circuit is configured by the combination of the differential amplifier that operates linearly and the MOS switch has been described. It is also possible to connect to a constant current source with a single switch.

In addition, each of the above-described embodiments is merely an example of the embodiment for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereby. is there. That is, the present invention can be implemented in various forms without departing from the spirit or the main features thereof. Industrial applicability

The present invention is useful for an IQ mixer constituting a quadrature modulator.

Claims

The scope of the claims

1. A first differential amplifier that performs differential amplification of signals that are input from two input terminals and differing in phase by 180 degrees, and the two inputs that are the same as the first differential amplifier. A frequency conversion circuit including a second differential amplifier that performs differential amplification of a signal input from a terminal,

One constant current source is commonly connected to the source of the transistor constituting the first differential amplifier and the source of the transistor constituting the second differential amplifier, and the first differential amplifier is connected. A frequency conversion circuit, characterized in that the amplifier and the second differential amplifier are driven by the one constant current source.

2. a first differential amplifier and a second differential amplifier that are connected in common to one constant current source and perform differential amplification operations of input signals that are 180 degrees out of phase with each other;

A first switch circuit and a second switch circuit which are connected to outputs of the first differential amplifier and the second differential amplifier and are driven based on local signals whose phases are 90 degrees different from each other. And

A frequency conversion circuit characterized in that an in-phase signal and a quadrature signal are extracted from the output of the second switch circuit and the first switch circuit.

3. The first differential amplifier and the second differential amplifier are connected to a virtual ground point through the one constant current source, according to claim 2, Frequency conversion circuit.

4. The frequency according to claim 2, wherein the first differential amplifier and the second differential amplifier are connected to a ground point through the one constant current source. Conversion circuit.

5. A first differential amplifier and a third differential amplifier, which are connected in common to one constant current source and perform differential amplification of input common-mode signals that are 180 degrees out of phase with each other,

A second differential amplifier and a fourth differential amplifier that are connected in common to one constant current source and that perform differential amplification operations of input quadrature signals that are different in phase by 180 degrees;

The first switch circuit connected to the outputs of the first differential amplifier and the second differential amplifier and driven based on local common-mode signals that are 90 degrees out of phase with each other. The switch circuit of

A third switch circuit connected to the outputs of the third differential amplifier and the fourth differential amplifier and driven based on mouth-single quadrature signals that are 90 degrees out of phase with each other; and A fourth switch and circuit,

Two common-mode signals are extracted from the output of the first switch circuit and the third switch circuit, and from the output of the fourth switch circuit. A frequency conversion circuit characterized by taking out two types of quadrature signals.