WO2007089366A2 - Warpage-reducing packaging design - Google Patents
Warpage-reducing packaging design Download PDFInfo
- Publication number
- WO2007089366A2 WO2007089366A2 PCT/US2006/061849 US2006061849W WO2007089366A2 WO 2007089366 A2 WO2007089366 A2 WO 2007089366A2 US 2006061849 W US2006061849 W US 2006061849W WO 2007089366 A2 WO2007089366 A2 WO 2007089366A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- flange
- die
- lip
- region
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/20—Conductive package substrates serving as an interconnection, e.g. metal plates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5453—Dispositions of bond wires connecting between multiple bond pads on a chip, e.g. daisy chain
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Definitions
- the present invention relates generally to semiconductor device fabrication. More particularly, the present invention relates to semiconductor packaging for reduction of thermal-mechanical deformation of the flange known as "warpage.”
- the wafer is sawn (also referred to as “diced") to separate the individual semiconductor die (also known as “dice” or “chips” or “device”) on the wafer. These separated die are then each packaged to facilitate safe die handling, and attachment to circuit boards, heat sinks, and the like.
- the die is attached or mounted to a packaging substrate (also known as a "flange").
- a packaging substrate also known as a "flange”
- the die with packaging substrate backing is then mounted or attached to a heat sink that acts to remove generated heat by conduction away from the device in use.
- the die is attached to the flange by any suitable method, for example by soldering or using an adhesive. This process is carried out at elevated temperature, and the die-flange combination is subsequently cooled to room temperature.
- US patent publication 20050012118 describes a package that can withstand high die-attach temperatures and that can provide a hermetically sealed air cavity for a die, without the use of adhesives. It discusses a circuit package for housing semiconductor that has a metallic flange, one or more high-copper leads and a liquid crystal polymer frame molded to the flange and the leads.
- the flange includes a dovetail-shaped groove that mechanically interlocks with the molded frame. During molding, a portion of the frame forms a key that freezes in or around the frame retention feature. There is no discussion of heat-induced flange deformation.
- the art recognizes that heat transfer from die to flange poses a challenge in operations where the die is attached at high temperature, and the combination is subsequently cooled to room temperature and thermal-mechanical deformation is induced.
- FIG. 1 is a schematic depiction of half of a prior art air cavity package
- FIG. 2 is a schematic depiction of half of another prior art air cavity package with a bonded ceramic insulator frame
- FIG. 3 is a schematic depiction of the half of the prior art assembly product of FIG. 2 with attached leads;
- FIG. 4 is a schematic perspective view of half of an embodiment of the invention showing a flange with stiffening lip and die on a die pedestal;
- FIG. 5 is a schematic perspective view of half of an embodiment of the invention showing a raised stiffening lip and multiple die, each disposed on its own pedestal;
- FIG. 6 is a schematic perspective view of half of an embodiment of the invention with embedded leads extending through a molded, stiffening lip;
- FIG. 7 is a perspective view of half of an embodiment of the invention with embedded leads configured to maintain a standard seating plane and die on multiple pedestals;
- FIG. 8 is a top view of the embodiment of the invention showing a thicker flange with embedded leads, extending through a lip in a peripheral region of the frame, while seating plane s is maintained;
- FIG. 9 is a schematic cross sectional view of the embodiment of FIG. 8 with a single pedestal
- FIG. 10 is an alternative embodiment to FIG. 9 with multiple pedestals.
- FIG. 11 is a graphical representation of the improvement in flange stiffness over a control achieved in accordance with the invention, for particular lip and pedestal configurations and under specified conditions.
- a predominant cause of loss of heat transfer efficiency from a die to the flange is physical deformation or "warpage" of the flange leading to separation between the die and the flange along their interface.
- the warpage often arises during the die attachment process, which is carried out at elevated temperatures.
- the warpage can be in excess of 5 mil.
- the extent of warpage varies, based on several factors (die attachment temperature, flange thickness, number of die attached, semiconductor and packaging material properties, etc.) but can be significant.
- warpage has undesirable effects in fabrication as well as subsequent use of the device.
- warpage must be minimized to avoid deleterious effects on subsequent assembly operations that must be performed on the package.
- the physical separation between die and flange results in a gap that, whether air-filled or not, disrupts heat transfer by conduction from die to flange (which then transfer heat to the heat sink). The gap reduces the area of the die in direct contact with the flange and thereby reduces conductive heat transfer.
- Heat transfer rates from die to flange can be maintained by preventing or minimizing the extent of flange warpage that causes separation during die attachment processes. Warpage can be reduced to some extent by appropriate selection of materials.
- flange materials may be selected from those that have a coefficient of thermal expansion (“CTE") that closely approximates or more closely matches the CTE of the die. This selection will avoid or minimize the build up of thermally-induced mechanical stresses at the die-flange interface that may cause physical separation of die and flange along at least a part of the interface.
- CTE coefficient of thermal expansion
- TC thermal conductivity
- a high TC is essential for high rates of heat transfer from die to flange and then through the flange to the heat sink. This means that a flange material with a poor TC may allow the die temperature to rise (because of inability to conduct heat away) and the temperature may reach a point that could result in adverse performance, diminished reliability, or even die damage.
- the invention provides modified flanges that have physical features to reduce the tendency of the flange to warp under thermally induced stresses, and that reduces the tendency for separation at the interface between the flange and the die.
- the invention provides a packaging substrate base (also known as a "flange") that has a structural lip configured to impart "stiffness" to the substrate base.
- the term “stiffness” here means the degree of resistance to thermally-induced warpage, where the warpage results from attachment of die to a flange that has a different coefficient of thermal expansion from the die.
- the flange-stiffening lip may be made from a variety of materials but commonly would be the same as the flange body.
- the flange may be made of a conductive material such as copper-tungsten, copper-molybdenum, copper, and high conductivity ceramics.
- the stiffness of the raised lip is achieved through appropriate configuration of the lip (height, width and shape) and is sufficient to at least partially counteract the warpage-inducing stresses generated from coefficient of thermal expansion differentials between the flange and a die attached to it.
- the lip may be molded or otherwise formed with the flange as a unitary lip-stiffened flange, or may be a separate structure that is affixed to the flange.
- the packaging flange has a first surface that has a first region having the stiffening lip.
- the first surface also has a second region for die attachment.
- the second region is a region that is stiffened by the lip, and may be raised above the first surface of the flange.
- the second region may be in the form of a single pedestal supporting a single or multiple die, or may be a series of raised pedestals, each supporting one or more die.
- the invention provides an assembly of die on the lip- stiffened flange.
- the assembly also includes at least one die in the second region of the flange.
- the assembly includes leads for electrical contact with the die.
- the leads and flange are insulated from each other by means of an intermediate material, such as a (non-conductive) ceramic layer, interposed between the flange and the leads.
- the leads are configured to preserve a seating plane at the desired height and configuration.
- the leads may be embedded in an organic composition. Further, the leads may have an end-portion embedded in and extending along a length of the lip; or the lead end portions may be attached along an upper surface of a length of the lip.
- the stiffening lip may take any of a variety of suitable shapes.
- the lip is a raised wall that extends around a peripheral area of the flange. Taking into account that the flange is laterally divided in the accompanying drawings, the lip is shown U-shaped, but should be understood to include its mirror image to form a frame-shape. Other raised configurations that also provide resistance to heat-induced stress deformation of the flange are, of course, also useful and contemplated in the invention.
- the lip may be in the shape of a rectangular array of a pair of spaced apart longitudinal and a pair of spaced apart lateral rails, where the rails are not connected up to form a frame.
- the stiffening features could be a series of longitudinally extending rails, such as two or three or more parallel rails.
- the flanges are symmetrical about a lateral axis at their mid points. Each depicted flange has been cut in half laterally at the midpoint, so that only one half is shown, for simplicity.
- a flange 10 is a planar substantially rectangular block of appropriate conductive material such as copper, to which are attached die 12, which is but not limited to semiconductor device like silicon. In this particular case there are six die arrayed in two rows of three each (i.e. twelve in the entire package). Note that upper surface 14 of the flange 10 is planar and devoid of raised features.
- the flange 20 is similar to that of FIG. 1, but has an adhered non-conductive ceramic frame 22 extending at the periphery and around a central area of the flange where the die 24 are attached.
- leads 26 attached to the upper surface 23 of the ceramic frame 22.
- the leads extend outboard away from the flange at a height and in a plane that defines the "seating plane" for the leads to facilitate subsequent processes involving the leads.
- FIG. 4 is half of a symmetrical device, cut along a lateral plane of symmetry.
- FIG. 4 depicts half a flange 100 with an upper surface 102 and an under surface (not shown) 104.
- a stiffening lip 200 extends along a periphery of the upper surface 102.
- the lip has a U- shape when halved laterally (i.e. in full shape it is a frame), although other shapes may also be useful and are within the scope of the invention.
- the lip has a width w and a thickness or height h above surface 102. The height h and width w are selected to enhance stiffness.
- a greater height h provides more stiffness than a lower height, in general, all other factors being equal.
- a greater width w provides more stiffness to the flange than a lesser width, in general, all other factors being equal.
- the height h of the lip would be in the range from about 10 to 25 mil for a copper flange.
- the height h of the lip will vary with materials and geometry of the flange and die, and materials with smaller CTE differences from the die should require smaller h. Smaller h would also be expected for comparatively thicker flanges or when using comparatively thin die, all other factors being equal.
- the stiffening lip may be molded with the flange as a one piece unit, or may be subsequently attached to the flange.
- the stiffening lip may be of the same or different material from the flange.
- the lip is preferably of the same material as the flange, or of a material with similar CTE.
- the location and size of the area that is stiffened by the lip also depends upon the configuration and location of the lip.
- the die may be attached in the stiffened area for best effect.
- a pedestal 300 is disposed in the lip-stiffened area of the flange 100, and is shown in the form of a raised platform.
- the raised pedestal 300 provides some enhancement of flange stiffness as well, as shown in the Example provided here below.
- Die (six die 400 are shown in this example, twelve in the symmetrical device) are attached to the pedestal to take advantage of the stiffened structure in that region that is at least partially surrounded by the stiffening lip 200.
- FIG. 5 depicts another embodiment of the invention, this one also shown in symmetrical half view like that of FIG. 4.
- the pedestal on flange 100 is not a single pedestal but a plurality of raised pedestals 330, each having an upper surface adapted for die attachment.
- the pedestals 330 are sized to conform to and register with the size of the die, however, the pedestals may each be oversized relative to the die.
- more than one die may be attached to each pedestal 330, depending upon selected die and pedestal sizes.
- FIG. 6 is a schematic depiction, according to an embodiment of the invention, of half of a symmetrical product assembly.
- the half of the raised lip 200 is of a U-shape (the complete lip is a frame) and disposed to surround die 400 that are disposed on the upper surface 102 of flange 100.
- the leads 500 have inboard end portions 502 that are embedded into and extend along the length of the wall 210 of the lip 200. Lead end portions 502 are isolated from flange 100 by surrounding non-conductive materials, such as ceramic layers 540, shown.
- leads 500 are configured so that when end portions 502 are embedded into the lip 200, lead outboard end portions 504 are at a height s (the seating plane) from a plane that is co-extensive with flange under surface 104. Accordingly, very few if any tooling modifications are necessary to accommodate the design for subsequent processing.
- FIG. 7 depicts another (lateral symmetrical half of) embodiment of a product assembly of the invention.
- flange 100 has a stiffening lip 206 and die 400 are each attached to one of a plurality of pedestals 330.
- a single raised pedestal with one or a plurality of die attached may also be used.
- the leads 500 are shaped such that when inboard end portions 502 are attached to the assembly, outboard end portions 504 are in the seating plane s.
- the inboard end portions 502 of leads 500 are embedded in the proximity of the upper surface of the lip 206 on ceramic inter-layer 540. Alternatively, the lead end portions may be embedded into and extend along the lip wall itself 210, while ensuring electrical isolation from the flange.
- the leads 500 are shaped so that outboard end portions 504 are at an elevation below the inboard end portions 502 when the leads are attached. End portions 504 will lie in a plane that is a height s (the desired seating plane) above flange undersurface 104, as also shown in FIG. 6.
- FIGS. 8, 9 and 10 represent top and alternative cross sectional views, respectively, of embodiments of the invention.
- the flange 100 has a raised lip (shown here as a pair of walls 200 extending longitudinally on each side of the flange 100) that stiffens the area between the lip walls 200.
- a plurality of die 400 is attached in the stiffened area, on a raised platform 300, as seen from FIG. 9.
- the need for raised platform 300 is discretionary since the flange thickness t could be increased to provide identical stiffness as provided by the coupled system of flange 100 and raised platform 300. From FIGS.
- inboard end portions 502 of leads 500 are embedded in opposing lip wall sides 210, and extend upward through the lip walls 210 to be exposed on the upper surface of the lip walls for attachment of connecting leads 550 to die 400.
- Walls 200 may be of a nonconductive material, such as ceramic or a polymeric material, to ensure isolation of leads 500 from flange 100.
- the leads may be isolated electrically from the lip walls 200 by a coating or intermediate layer of a non conductive of material.
- Leads 500 are configured so that outboard end portions 504 are in the desired seating plane s.
- the seating plane s can be adjusted by controlling the shape of leads 500 taking into account the shape of the device and the seating plane necessary. [0040] As shown in FIG.
- the flange 100 is of greater thickness t than prior art flanges.
- the thickness t is sufficient to provide resistance to thermally-induced warpage, and is typically in the range from about 65 to 100 mil.
- the flange 100 has a pair of raised walls 200 that extend around the sides of the flange 100 to form outer side walls 210.
- the raised walls 200 are penetrated by lead end portions 502 that extend through the walls 200 (all along the length of the walls) to be exposed, for electrical connection, above walls 200 to lead wires 550.
- lead wires 550 also connect to the die 400 that are all attached to a single raised pedestal 300.
- each die 400 might also be attached to one of a multiplicity of raised pedestals 330, as shown in FIG. 10.
- the need for raised pedestal 330 is discretionary since the flange thickness t could be increased to provide identical stiffness as provided by the coupled system of flange 100 and raised platform 330.
- FIG. 10 The embodiment of FIG. 10 is similar to the embodiment of FIG. 9 except that the raised walls 200 rest upon a platform 120 on the perimeter of the flange 100.
- the sides of the device are made up of: (1) upper sidewalls that are the sidewalls 210 of the walls 200; and (2) and lower sidewalls that are the flange sidewalls 110, 112. Leads penetrate the walls 200 as in FIG. 9. Above comments, with reference to FIG. 9, regarding lead electrical isolation from the flange apply here as well.
- the invention provides a packaging flange that has a first surface and a second surface opposed to the first.
- the first surface of the flange includes a first region that has a raised lip extending thereon.
- the first region is spaced from a second region that is adapted to receive at least one die.
- the lip is configured to impart stiffness to the flange, the stiffness sufficient to at least partially counteract thermally-induced stresses generated from coefficient of thermal expansion differentials between the flange and a die during an elevated temperature die attachment process.
- the second region may include a pedestal that has a surface sized and shaped to support at least one die thereon. Or, the second region may include a plurality of pedestals.
- the lip may extend around a peripheral region of the first surface of the flange to form a frame surrounding the second region.
- the flange and the lip may be molded in one piece.
- the ratio of stiffening lip height h to flange thickness t for a configuration like that shown in FIG. 8, using copper flanges would be in the range from about 0.15 to about 0.25 for a 100 mil thickness flange. The ratio will vary based on several considerations, including flange configuration, materials, and the like.
- the invention also provides a die assembly that has a flange having a first surface and a second surface opposed to the first.
- the first surface of the flange includes a first region having a lip extending thereon.
- the first region is spaced from a second region that is adapted to receive at least one die.
- the lip is configured to impart stiffness to the flange, the stiffness sufficient to at least partially counteract thermally-induced stresses generated from coefficient of thermal expansion differentials between the substrate and a die to be mounted thereon in an elevated temperature die attachment process.
- the flange has at least one die mounted in the second region.
- the assembly includes leads for electrical contact with the die.
- the leads may be configured to preserve a seating plane, which is spaced from a plane of the second surface of the flange.
- the leads may be embedded in an organic composition, with inboard end-portions embedded in the lip.
- the leads may be embedded in an organic composition so that the molded leads extend from raised inboard end portions nearest the die to lower outboard end portions that are aligned substantially within the seating plane.
- the inboard end portions of the leads may be exposed for electrical communication with the die.
- the second region may include a pedestal having a surface adapted to support at least one die thereon.
- the second region may have a plurality of pedestals. Each of the pedestals has a surface that may be adapted to support at least one die thereon.
- the die assembly includes: a packaging flange having a first surface and a second surface opposed to the first, the first surface of the flange comprising a first region having a lip extending thereon, the first region spaced from a second region adapted to receive at least one die, the flange having a body configured to impart stiffness to the flange, the stiffness sufficient to at least partially counteract thermally-induced stresses generated from coefficient of thermal expansion differentials between the flange and a die to be attached thereon during an elevated temperature die attachment process.
- the assembly of Claim 14 wherein the body of the flange has thickness in the raege from about 65 to about 100 mils.
- the first region may extend along a side of the flange and the lip may extend upward as a wall above the upper surface of the flange.
- the first region may alternatively extend along a side of the flange, where the flange has a platform so that the lip rests on the platform.
- There may be at least one pedestal in the second region, or none.
- the assembly may have leads with inboard end portions embedded along a length of a lip wall and extending to an upper surface of the lip to permit attachment of connections to die on the flange.
- Tests were conducted to quantify the improvement in stiffness (resistance to warpage from heat-induced stress) of flanges made according to the invention as compared to a control without any stiffening structure.
- the flanges were all made of copper and 100 mil thick. In these tests the following were compared: [0047] A. A 100 mil thick flange as control
- each flange was measured for planarity to eliminate any that had inherent warpage. Testing was then conducted according to the following: the flanges were each heated to 380 degrees Centigrade for die attachment. Twelve die were attached to each flange, and each was then cooled to room temperature at approximately the same rate. After cooling, each flange was measured from center to edge for extent of warpage. The results are graphically illustrated in FIG. 11, with reference to the alphabetic designations, above, for each flange. As can be seen, each of the frame-bearing stiffened flanges (B, D, and E) had less warpage than the control flange A. Further, the flanges that had both frame and raised pedestal (D, E) had less warpage than those with only a frame (B). Finally, the flange with frame and multiple pedestals E had the best result (lowest warpage).
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
- Packaging Frangible Articles (AREA)
- Extrusion Moulding Of Plastics Or The Like (AREA)
Abstract
Description
Claims
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006800517755A CN101375394B (en) | 2006-01-27 | 2006-12-11 | Package design with reduced warpage |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/341,991 | 2006-01-27 | ||
| US11/341,991 US20070175660A1 (en) | 2006-01-27 | 2006-01-27 | Warpage-reducing packaging design |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2007089366A2 true WO2007089366A2 (en) | 2007-08-09 |
| WO2007089366A3 WO2007089366A3 (en) | 2008-09-18 |
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ID=38320907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2006/061849 Ceased WO2007089366A2 (en) | 2006-01-27 | 2006-12-11 | Warpage-reducing packaging design |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US20070175660A1 (en) |
| CN (1) | CN101375394B (en) |
| TW (1) | TW200802738A (en) |
| WO (1) | WO2007089366A2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5597727B2 (en) * | 2011-01-20 | 2014-10-01 | 京セラ株式会社 | Semiconductor element storage package and semiconductor device including the same |
| US20130027894A1 (en) * | 2011-07-27 | 2013-01-31 | Harris Corporation | Stiffness enhancement of electronic substrates using circuit components |
| US8698291B2 (en) * | 2011-12-15 | 2014-04-15 | Freescale Semiconductor, Inc. | Packaged leadless semiconductor device |
| US8803302B2 (en) | 2012-05-31 | 2014-08-12 | Freescale Semiconductor, Inc. | System, method and apparatus for leadless surface mounted semiconductor package |
| KR101686745B1 (en) * | 2015-08-07 | 2016-12-15 | 재단법인 다차원 스마트 아이티 융합시스템 연구단 | Power amplifier module package and packaging method thereof |
| WO2017201260A1 (en) * | 2016-05-20 | 2017-11-23 | Materion Corporation | Copper flanged air cavity packages for high frequency devices |
| WO2019006101A1 (en) * | 2017-06-30 | 2019-01-03 | Kyocera International, Inc. | Microelectronic package construction enabled through ceramic insulator strengthening and design |
| JP7102525B2 (en) * | 2018-11-29 | 2022-07-19 | コステックシス カンパニー リミテッド | How to manufacture a package for a power amplifier with a built-in input / output circuit |
| CN114582826A (en) * | 2020-11-30 | 2022-06-03 | 上海华为技术有限公司 | Packaging structure and packaging method |
Family Cites Families (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3784884A (en) * | 1972-11-03 | 1974-01-08 | Motorola Inc | Low parasitic microwave package |
| JPS5272170A (en) * | 1975-12-12 | 1977-06-16 | Nec Corp | Package for semiconductor elements |
| JPS5896757A (en) * | 1981-12-04 | 1983-06-08 | Hitachi Ltd | Semiconductor device |
| JPS6022345A (en) * | 1983-07-19 | 1985-02-04 | Toyota Central Res & Dev Lab Inc | Semiconductor device |
| JPH0770641B2 (en) * | 1989-03-17 | 1995-07-31 | 三菱電機株式会社 | Semiconductor package |
| US4994897A (en) * | 1989-10-26 | 1991-02-19 | Motorola, Inc. | Multi-level semiconductor package |
| JPH0732208B2 (en) * | 1989-10-31 | 1995-04-10 | 三菱電機株式会社 | Semiconductor device |
| JP2527828B2 (en) * | 1990-02-27 | 1996-08-28 | 三菱電機株式会社 | Semiconductor package |
| US5309014A (en) * | 1992-04-02 | 1994-05-03 | Motorola Inc. | Transistor package |
| US6056186A (en) * | 1996-06-25 | 2000-05-02 | Brush Wellman Inc. | Method for bonding a ceramic to a metal with a copper-containing shim |
| US5877555A (en) * | 1996-12-20 | 1999-03-02 | Ericsson, Inc. | Direct contact die attach |
| US6335863B1 (en) * | 1998-01-16 | 2002-01-01 | Sumitomo Electric Industries, Ltd. | Package for semiconductors, and semiconductor module that employs the package |
| US6211463B1 (en) * | 1998-01-26 | 2001-04-03 | Saint-Gobain Industrial Ceramics, Inc. | Electronic circuit package with diamond film heat conductor |
| US6261868B1 (en) * | 1999-04-02 | 2001-07-17 | Motorola, Inc. | Semiconductor component and method for manufacturing the semiconductor component |
| US6462413B1 (en) * | 1999-07-22 | 2002-10-08 | Polese Company, Inc. | LDMOS transistor heatsink package assembly and manufacturing method |
| JP3533159B2 (en) * | 2000-08-31 | 2004-05-31 | Nec化合物デバイス株式会社 | Semiconductor device and manufacturing method thereof |
| JP2003068919A (en) * | 2001-08-27 | 2003-03-07 | Nec Yamagata Ltd | Semiconductor device |
| US20040046247A1 (en) * | 2002-09-09 | 2004-03-11 | Olin Corporation, A Corporation Of The Commonwealth Of Virginia | Hermetic semiconductor package |
| US7298046B2 (en) * | 2003-01-10 | 2007-11-20 | Kyocera America, Inc. | Semiconductor package having non-ceramic based window frame |
| SG157957A1 (en) * | 2003-01-29 | 2010-01-29 | Interplex Qlp Inc | Package for integrated circuit die |
| US20040246682A1 (en) * | 2003-06-09 | 2004-12-09 | Sumitomo Metal (Smi) Eectronics Devices Inc. | Apparatus and package for high frequency usages and their manufacturing method |
| US7075174B2 (en) * | 2004-02-26 | 2006-07-11 | Agere Systems Inc. | Semiconductor packaging techniques for use with non-ceramic packages |
| CN100353512C (en) * | 2004-07-07 | 2007-12-05 | 日月光半导体制造股份有限公司 | Package structure for preventing warping and manufacturing method thereof |
| US7445967B2 (en) * | 2006-01-20 | 2008-11-04 | Freescale Semiconductor, Inc. | Method of packaging a semiconductor die and package thereof |
-
2006
- 2006-01-27 US US11/341,991 patent/US20070175660A1/en not_active Abandoned
- 2006-12-11 CN CN2006800517755A patent/CN101375394B/en not_active Expired - Fee Related
- 2006-12-11 WO PCT/US2006/061849 patent/WO2007089366A2/en not_active Ceased
- 2006-12-22 TW TW095148552A patent/TW200802738A/en unknown
-
2010
- 2010-02-12 US US12/704,941 patent/US7989951B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| WO2007089366A3 (en) | 2008-09-18 |
| CN101375394B (en) | 2010-06-23 |
| US20100142168A1 (en) | 2010-06-10 |
| CN101375394A (en) | 2009-02-25 |
| TW200802738A (en) | 2008-01-01 |
| US20070175660A1 (en) | 2007-08-02 |
| US7989951B2 (en) | 2011-08-02 |
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