WO2007088426A1 - Dispositif et procédé pour accéder à des unités mémoire dynamiques - Google Patents

Dispositif et procédé pour accéder à des unités mémoire dynamiques Download PDF

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Publication number
WO2007088426A1
WO2007088426A1 PCT/IB2006/050334 IB2006050334W WO2007088426A1 WO 2007088426 A1 WO2007088426 A1 WO 2007088426A1 IB 2006050334 W IB2006050334 W IB 2006050334W WO 2007088426 A1 WO2007088426 A1 WO 2007088426A1
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Prior art keywords
dma
requests
dma task
row
task
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PCT/IB2006/050334
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English (en)
Inventor
Uri Shasha
Norman Goldstein
Sagi Gurfinkel
Gilad Hassid
Eran Kahn
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Freescale Semiconductor, Inc.
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Priority to PCT/IB2006/050334 priority Critical patent/WO2007088426A1/fr
Publication of WO2007088426A1 publication Critical patent/WO2007088426A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison

Definitions

  • the present invention relates to devices and methods for accessing dynamic memory units.
  • DMA controller can manage multiple data transfers while reducing the load from the integrated circuit cores (processors) . Nevertheless, DMA controllers can still load these cores by issuing an interrupt whenever certain DMA tasks are completed.
  • patent 6041060 ofchty et al . U.S. patent applications serial number 2004/0073721A1 of Goff et al, U.S. patent applications serial number 20040037156Al of Takashi et al .
  • U.S. patent application publication number 2004021618Al of Cheung Japanese patent publication number JP07168741A2 of Hedeki et al .
  • Japanese patent publication number JP06187284A2 of Masahiko Japanese patent application publication number JP2004252533A2 of Yoshihiro
  • Japanese patent publication number JP04324755A2 of Tadayoshi et al Japanese patent publication number JP04324755A2 of Tadayoshi et al .
  • Dynamic memory units are characterized by a relatively long row switching penalties.
  • a DMA controller reads data from a first row of a dynamic memory unit and then switches to another row of the dynamic memory unit the first row has to be properly closed and just then the second row can be opened.
  • Typical row switching operations are about 20nanoSecond long.
  • FIG. 1 illustrates a device, according to an embodiment of the invention
  • FIG. 2 illustrates a DMA controller, according to an embodiment of the invention
  • FIG. 3 illustrates a bus interface, according to an embodiment of the invention
  • FIG. 4 illustrates various registers of file register, according to an embodiment of the invention
  • FIG. 5 illustrates a buffer descriptor table according to an embodiment of the invention
  • FIG. 6 illustrates a DMA channel and a selected DMA channel logic, according to an embodiment of the invention
  • FIG. 7 is a flow chart of a method for controlling multiple DMA tasks, according to an embodiment of the invention.
  • FIG. 8 is a flow chart of a method for accessing a dynamic memory unit, according to an embodiment of the invention.
  • FIG. 9 is a flow chart of a method for accessing a dynamic memory unit, according to another embodiment of the invention.
  • FIG. 10 is a flow chart of a method for accessing a dynamic memory unit, according to a further embodiment of the invention.
  • a method includes: (i) receiving multiple requests to perform DMA transactions to the dynamic memory unit, ( ⁇ ) searching for a row filling group of DMA task requests within the received requests; and (iii) executing, in a consecutive manner, multiple DMA transactions associated with the row filling group of DMA task requests.
  • the method includes selecting between multiple row filling groups of DMA task requests associated with different rows of the dynamic memory unit .
  • the method includes determining a size of a vacant row portion.
  • the stage of receiving includes receiving a DMA task request and partitioning the DMA task request to multiple DMA transaction requests.
  • the method includes arbitrating between multiple DMA task requests and delaying an execution of DMA task requests that won the arbitration until they form a row filling group of DMA task requests.
  • the method includes receiving requests to perform DMA transactions from the dynamic memory unit; searching for a complete row read group of DMA task requests out of the received requests; and executing, in a consecutive manner, multiple DMA transactions associated with the complete row read group of DMA task requests.
  • a device is provided.
  • the device includes a dynamic memory unit and a DMA controller that is adapted to: (i) receive multiple requests to perform DMA transactions to the dynamic memory unit, (ii) to search for a row filling group of DMA task requests within the received requests; and (iii) to execute, in a consecutive manner, multiple
  • the DMA controller is adapted to select between multiple row filling groups of DMA task requests associated with different rows of the dynamic memory unit .
  • the DMA controller is adapted to determine a size of a vacant row portion.
  • the DMA controller is adapted to receive a DMA task request and to partition the DMA task request to multiple DMA transaction requests.
  • the DMA controller is adapted to arbitrate between multiple DMA task requests and to delay an execution of DMA task requests that won the arbitration until they form a row filling group of DMA task requests.
  • the DMA controller is adapted to receive multiple requests to perform DMA transactions from the dynamic memory unit; search for a complete row read group of DMA task requests from the received requests; and execute, in a consecutive manner, multiple DMA transactions associated with the complete row read group of DMA task requests.
  • a DMA task includes a transfer of information from one location to another.
  • a DMA task may require many DMA transactions.
  • the number of DMA transaction per DMA task is responsive to the relationship between the overall size of data that should be transferred during a DMA task and the size of data that can be transferred during a single DMA transaction.
  • the size of a row of a dynamic memory unit that is accessed during one or more DMA transactions can dictate the size of a DMA transaction size, the size of a group of DMA transactions that should be performed in a consecutive manner (such as those DMA transactions that form a row filling group of DMA task requests) and even the size of a DMA task.
  • a row filling group of DMA task requests can include one or more DMA task requests.
  • a row filling group of DMA task requests can include one or more DMA task requests that if are fulfilled fill a row from a requested start address till the end of that row.
  • complete row read group of DMA task requests can include one or more DMA task requests.
  • a complete row read group of DMA task request includes one or more DMA task requests that if are fulfilled the content of a row from a requested start address till the end of that row. It is noted that the group can fill more than a row. If this is the case once the row is filled the DMA controller can check if this group of another group of DMA task requests can fill another row.
  • a DMA task that can fill multiple rows can be partitioned to multiple groups of DMA transactions, while each group fills a row or reads a content of an entire row.
  • DMA operations are executed in a manner that reduced the amount of accesses per dynamic memory unit. Especially, DMA operations are executed if they fill a whole dynamic memory row or if they read a content of a complete row. In some scenarios a row can be filled by executing multiple DMA task requests. In such a case the DMA controller can arbitrate between multiple DMA task requests to provide an arbitration winner. The DMA controller than checks if one or more pending DMA task requests can access the whole row. If the answer is positive these one or more DMA task requests are executed in a consecutive manner.
  • the DMA controller can delay the execution of a DMA task request that won an arbitration, and temporarily store it until it is executed. According to an embodiment of an invention once a
  • the DMA controller can prevent DMA task requests from participating in the arbitration process if they do not fill a row.
  • the FIFO 150 can provide the DMA task requests to an arbiter, thus it can also filter the DMA task requests.
  • a method for writing to a dynamic memory unit includes receiving multiple requests to perform DMA transactions to the dynamic memory unit, searching for a row filling group of DMA task requests within the received requests, and executing, in a consecutive manner, multiple DMA transactions associated with the row filling group of DMA task requests.
  • a device includes a dynamic memory unit and a DMA controller that is adapted to: receive multiple requests to perform DMA transactions to the dynamic memory unit, to search for a row filling group of DMA task requests within the received requests; and to execute, in a consecutive manner, multiple DMA transactions associated with the row filling group of DMA task requests.
  • the number of DMA transactions can be responsive to the success of the DMA transactions, as failed DMA transactions can be followed by re-transmission of the data that was supposed to be transferred during the failed DMA transaction.
  • FIG. 1 illustrates a system 90, according to an embodiment of the invention.
  • System 90 includes DMA controller 100 as well as additional components.
  • device 90 has a first DMA task controlling capabilities. It includes a memory unit and a DMA controller that is adapted to monitor an execution of the first DMA task that involves an access to the memory unit, and to perform a first possible timing violation responsive operation if the first DMA task was not completed during a first DMA task execution sub-interval.
  • DMA controller 100 can be connected to multiple memory mapped components and can be a part of various system on chip systems. The inventors used a thirty two channel DMA controller 100, but the number of DMA channels can be altered. Multiple registers and logic are associated with each DMA channel. Conveniently, multiple components such as but not limited to peripherals, cores and memory units can be connected to the DMA controller 100. Conveniently, the DMA controller can dynamically select which components to service. Thus the mere connection between the DMAS controller and a component does not necessarily mean that that a DMA channel is allocated to that component.
  • Bus 91 is connected to the DMA controller 100, bus media access controller (denoted MAC) 98, multiple cores 92, multiple memory units 94, external high level memory interface 95, and communication ports such as Ethernet port 97 and PCI 99.
  • bus media access controller denoted MAC
  • M peripherals 96
  • At least one of memory units 94 is a dynamic memory unit. It is noted different memory units can be characterized by different row widths. It is noted that different ports of the DMA controller 100 can be connected to different buses, and that bus 91 can be replaced by multiple busses, each conveniently having its own MAC.
  • System 90 includes multiple memory units, including internal memory units (not shown) within the DMA controller 100. Various information can be stored in various memory units. Conveniently, buffer descriptors stored in memory units 94. It is noted that at least one buffer descriptor can be stored within the DMA controller 100 itself, but this is not necessarily so. The buffers that are pointer by the buffer descriptors can be implemented within memory units 94 or the external high level memory unit 93.
  • the buffer descriptors are programmed in advance and include information that controls the DMA tasks.
  • FIG. 2 illustrates a DMA controller 100, according to an embodiment of the invention.
  • DMA controller 100 includes two I/O ports 172 and 174, I/O port interface 160, bus interface 140, multiple FIFOs 150, PRAM 130, DMA logic 120, channel logic and arbiter 110 and a register file 200.
  • the DMA logic 120 is connected to the bus interface 140, channel logic and arbiter 110, register file 200, a parametric RAM (PRAM) 130 and FIFOs 150.
  • the PRAM 130 is connected to the bus interface 140 and to the channel logic and arbiter 110.
  • the register file 200 is connected to the channel logic and arbiter 110.
  • the FIFOs 150 are connected to the bus interface 140. I/O port interface
  • I/O ports 172 and 174 are connected to I/O ports 172 and 174, and to the bus interface 140.
  • DMA controller 100 can include a bus interface and/or an I/O port interface for each I/O port, but for simplicity of explanation only one I/O port interface 160 and a single bus interface 140 are illustrated.
  • the two I/O ports 172 and 174 are connected to bus 176 that in turn is connected to external memory units such as memory units 94.
  • the dual I/O ports facilitate an execution of two DMA tasks in parallel. It is noted that the amount of I/O ports can differ from two.
  • Memory units 94 store buffer descriptors and are also used to implement buffers. These buffers can include single dimensional buffers or multidimensional buffers. Multidimensional buffers include multiple address ranges that are linked to each other. It is noted that the buffer descriptors can be stored in one or more memory units while one or more other memory units are used to implement the buffers.
  • the buffer descriptors define various characteristics of the DMA tasks, such as the location of a buffer, the remaining data to be transferred in order to complete a DMA task or a DMA sub- task (said size also referred to as residual size) , the number of buffer dimensions, timing of the DMA tasks, operations to perform once the DMA task ends and/or the buffer is full or empty, and the like.
  • a buffer descriptor can also include information about the allowed size of DMA transaction, allowed size of DMA task, and size of a row of a dynamic memory unit that stored the buffer that is associated with the buffer descriptor.
  • the size of the row is embedded within the allowed size of DMA transaction or DMA task size. But this is not necessarily so.
  • the inventors used a dedicated field to indicate the size of a row of a dynamic memory unit.
  • the rows of a dynamic memory unit are aligned, such that the lower bits of the address of each row are ⁇ 00000'. Accordingly, the DMA controller 100 can determine the amount of data required to fill a row by comparing between the address associated with the DMA task, and the size of the row. For example, assuming that each row of a dynamic memory unit 94 includes 512 bytes, that the first row starts at address 0 and that the following rows are aligned. If, for example, the DMA task has a start address of 128 then DMA controller 100 can determine the amount of data needed to fill the row by subtracting 128 from 512. Accordingly, the first group of DMA transactions will be executed if it fills these 384 bytes.
  • An exemplary buffer descriptor can include instructions or control information that cause the DMA controller to perform one of the following operations once the buffer is full: (i) shut down the DMA channel (for example by preventing that DMA channel to send DMA task requests to the arbiter) , (ii) reinitialize (thus implementing a cyclic buffer) , (iii) reinitialize once a certain re-write period expires (thus implementing a time-based cyclic buffer) , (iv) reinstall the buffer size (thus implementing an incremental buffer) , or (v) switch to another buffer (thus implementing a chained buffer) , and the like.
  • the buffer descriptors are defined by a user or by another entity and are stored in one or more memory units 94.
  • Each DMA channel can be associated with multiple buffer descriptors. These buffer descriptors can be arranged in various manners, such as but not limited to buffer descriptor tables (BDT) . Each DMA channel can be associated with a unique BDT.
  • BDT buffer descriptor tables
  • Various data retrieval methods can be applied in relation to the buffer descriptors. Conveniently, at the first time a certain DMA task request is selected by the arbiter, the associated buffer descriptor is retrieved from the memory units 94. The buffer descriptor is then stored in the PRAM 130, updated by the DMA controller
  • the FIFOs 150 send requests to retrieve buffer descriptor.
  • Each FIFO 150 entry (or a group of entries) is associated with a certain communication channel.
  • the FIFOs 150 requests the DMA logic 120 to initiate DMA transactions that provide to the PRAM 130 the buffer descriptors associated with communication channels that are serviced by FIFOs 150.
  • the FIFO 150 retrieves the buffer descriptor and determines if it can completely fill (in a write operation) an entire row, or whether it can read an entire row. If the answer is positive the DMA controller 100 can execute consecutive DMA transactions to fill the row, while updating the buffer descriptor.
  • the buffer descriptor update includes reducing the size of residual data (size of data to be transmitted in order to complete the DMA task) , as well as updating the pointer to the next vacant entry in the dynamic memory unit .
  • the DMA controller 100 determines that a whole row is completed the arbitration process can restart, allowing other communication channels to be involves in DMA transfers.
  • the arbitration is made on a DMA transaction basis.
  • a DMA task request that belongs to a group of row filling DMA task requests wins an arbitration the other DMA task request of the group should win the consecutive arbitration cycles. This can be done by freezing the priority of pending DMA task requests or assigning the other member of the group a high priority, in order to guarantee that the whole group of DMA task requests win consecutive arbitration cycles.
  • the channel logic and arbiter 110 includes an interface 420 and an arbiter 410. It receives DMA task requests from various memory-managed components, such as but not limited to peripherals 96, and performs an arbitration sequence to select one out of these DMA task requests .
  • the interface 420 can be adapted to check whether a DMA task can be serviced (if the associated DMA task request wins the arbitration session) before sending the DMA task request to the arbiter 410. This check can involve determining whether the DMA channel is enabled, not frozen, the I/O port can be serviced, whether the DMA task request is not temporarily masked, whether the DMA task request belongs to a row filling group of DMA task requests and the like. It is noted that the DMA task request can be masked by FIFOs 150, if they it does not belong to a row filling group of DMA task requests.
  • a DMA task request can be temporarily masked if, for example, a certain DMA task is time-based cyclic DMA task and if during a predefined DMA task period a previous DMA task was executed.
  • the arbiter 410 is adapted to select a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks.
  • the arbiter 410 is adapted to select between DMA task requests associated with substantially same timing deadlines in response to predefined priority.
  • the arbiter 410 is adapted to select between DMA task requests associated with substantially same timing deadlines by applying a timing indifferent arbitration scheme.
  • Such an arbitration scheme is not responsive to the timing deadline and can include any of the well known prior art arbitration schemes such as round robin, weighted round robin, fixed priority, dynamically assigned priority, weighted fair queuing, low latency queuing, and the like.
  • the dynamically assigned priority can change a priority of the DMA requests each one or more arbitration cycle. At least some of these arbitration schemes can limit the amount of bandwidth consumed by a certain DMA channel.
  • the arbiter 410 is adapted to select a DMA task in response to at least one available bandwidth parameter (ABP) .
  • the available bandwidth parameter can be the number of devices that are connected to a bus that is also connected to the DMA controller 100, the bus bandwidth, the state of that bus (whether the bus is busy), and the like.
  • the arbiter ignores DMA task requests that can not be executed once the arbitration ends. For example, some DMA tasks require that a bus is not busy and that a data recipient is available. If these conditions are not fulfilled the arbiter 410 can ignore a DMA request that involves transferring data over the busy bus and/or to a busy data recipient.
  • the arbiter 410 is adapted to select a DAM task in response to at least one requested bandwidth parameter (RBP) .
  • the requested bandwidth parameter can be the number of data transfer operations that are required for completing the DMA task, the size of data that is transferred during each data transfer, and the like.
  • the arbiter 410 can select a DMA task in response to one or more RBP and one or more ABP .
  • each DMA task can be associated with one of the I/O ports 172 and 174.
  • the arbiter 410 can perform two independent arbitrations sessions. The first arbitration session selects a DMA task that is associated with I/O port 172 while the other session selects a DMA task that is associated with I/O port 174. Both arbitration sessions can be executed in parallel.
  • the DMA tasks are not initially associated with certain I/O ports.
  • the arbiter 410 can select two DMA tasks and then the DMA controller 100 will decide which the I/O ports that will service the DMA tasks.
  • the arbitration process includes two stages. During the first stage the arbiter 410 sorts the DMA tasks to predefined timing deadlines ranges. Then, is selects between the DMA tasks that are associated with the shortest timing deadline range.
  • the inventors used an eight-bit timing deadline value and four timing deadline ranges (zero and one) , (two to seven) , (eight to sixty three) and (sixty four to two hundred and fifty five) , but other ranges can be defined.
  • the DMA controller 100 includes multiple FIFOs 150. Conveniently one FIFO is allocated to each DMA channel. The status of the FIFOs can be provided to the DMA logic 120 that can, in response to the status, send one or more DMA requests to the channel logic and arbiter 110.
  • a DMA request can be blocked if it does not belong to a row filling group of DMA requests. For example, is a certain FIFO is empty the DMA logic 120 can decide to fill it (by performing write operations) and when it is full is can decide to empty it (by performing read operations) .
  • the channel logic and arbiter 110 can decide to arbitrate between the DMA tasks or temporarily ignore them in response to the DMA channel status (frozen, disabled, defrosted, enabled) , the I/O port availability, the current capability of a component associated with the DMA channel to participate in a DMA transfer and the like.
  • a DMA task request does not enter the arbitration session if the I/O port that should be used during the DMA task is busy. It is noted that various parts of the DMA controller can perform this check. According to another embodiment of the invention the status of the I/O port is not checked and if such a DMA task request wins the arbitration session it can be stored within an internal queue of the DMA controller 100, be ignored or temporarily ignored.
  • FIG. 3 illustrates bus interface 140, according to an embodiment of the invention.
  • the bus interface 140 includes a DMA task request sample unit (RSU) 142, a write FIFO 144, a read FIFO 146 and a task manager 148.
  • RSU DMA task request sample unit
  • the RSU 142 samples DMA task requests provided by the DMA logic 120 and sends them to the I/O port interface 160.
  • the RSU 142 samples the DMA task requests sent by the DMA logic. Once a DMA task request is detected it is sent to the I/O port interface 160. If the I/O port associated with the DMA task request is not busy then the request is serviced. Conveniently, the request is serviced after one clock cycle, but this is not necessarily so. If the I/O port associated with the DMA task request is busy the RSU 142 can send a RSU-busy signal to the DMA logic 120. Conveniently, the DMA task request is stored in a queue of the task manager 148, until it is serviced.
  • the task manager 148 includes a queue that can store few (such as eight) DMA task requests. Once the queue of the task manager 148 is full it sends a task- manager- busy indication signal to the DMA logic in order to temporarily block new requests from the DMA logic. It is noted that a queue can be allocated to each I/O port.
  • the bus interface 140 includes an internal read FIFO 146 and write FIFO 148. These FIFOs relax timing constraints and provide a pipelined structure for read and write operation through the I/O port interface 160 and I/O ports 172 and 174.
  • the FIFOs help in monitoring the state of dynamic memory rows, by comparing between the row size, and the pointer located in the buffer descriptors.
  • FIG. 4 illustrates various registers of file register 200, according to an embodiment of the invention .
  • the file register 200 includes one or more shadow registers.
  • a shadow register is associated with a corresponding register and can allow to update the content of that register even when the register is being utilized.
  • File register 200 includes multiple programmable registers, such as DMA buffer descriptor base registers, DMA channel configuration registers, DMA global configuration register 220, DMA channel enable register 230, DMA channel disable register 232, DMA channel freeze register 234, DMA channel defrost register 236, DMA EDF resisters, DMA EDF mask register 250, DMA EDF status register 254, DMA error register 260, as well as various debug registers, profiling registers, additional status registers and update registers.
  • programmable registers such as DMA buffer descriptor base registers, DMA channel configuration registers, DMA global configuration register 220, DMA channel enable register 230, DMA channel disable register 232, DMA channel freeze register 234, DMA channel defrost register 236, DMA EDF resisters, DMA EDF mask register 250, DMA EDF status register 254, DMA error register 260, as well as various debug registers, profiling registers, additional status registers and update registers.
  • Each DMA channel is associated with a buffer descriptor table (BDT) .
  • the BDT includes multiple buffer descriptors.
  • Each DMA channel has a DMA buffer descriptor base register, such as register 202 that stores the base address of the buffer descriptor table of that DMA channel .
  • Each DMA channel is associated with a DMA channel configuration register, such as DMA channel configuration register 210. It includes the following fields: DMA channel active (ACTV) field 212, source I/O port (SPRT) field 213, destination I/O port (DPRT) field 214, source multidimensional (SMDC) field 215, destination multidimensional (DMDC) field 216, source BDT pointer 217, destination BDT pointer 218, round robin priority group (RRPG) field 219.
  • DMA channel active (ACTV) field 212 DMA channel active (ACTV) field 212
  • SPRT source I/O port
  • DPRT destination I/O port
  • SR source multidimensional
  • DMDC destination multidimensional
  • RRPG round robin priority group
  • registers can include fields such as source/destination latency or utilization optimization scheme, and the like.
  • ACTV 212 indicates if the DMA channel is active or not.
  • SPRT 213 indicates the source I/O port, and DPRT 214 indicates the destination I/O port.
  • SMDC 215 indicates if the source buffer is a multidimensional buffer.
  • DMDC 216 indicates if the destination buffer is a multidimensional buffer.
  • the source BDT pointer 217 includes an offset within a BDT to the source buffer descriptor.
  • the destination BDT pointer 218 includes an offset within a BDT to the destination buffer descriptor. The address of a selected buffer descriptor is calculated from the buffer descriptor base address and the offset.
  • the RRPG 219 indicates the priority of the DMA channel in a round robin arbitration scheme.
  • DMA global configuration register 220 includes various fields such as internal or external buffer descriptor enable field 222, arbitration type field 224, and the like.
  • the arbitration type field is configured such as to select between multiple available arbitration schemes. These arbitration schemes can include, for example, timing deadlines based arbitration scheme, timing deadline indifferent arbitration scheme, and/or a combination of both.
  • the DMA channel enable register 230 includes multiple bits. Each set bit indicates that the associated DMA channel is enabled. Reset bits are ignored.
  • the DMA channel disable register 232 includes a bit for each DMA channel. If that bit is set then the DMA channel is disabled. Reset bits are ignored.
  • DMA channel freeze register 234 includes a bit for each DMA channel. If that bit is set then the DMA channel is frozen. The difference between a frozen DMA channel and a disabled DMA channel is that the requests of a frozen DMA channel are considered but not serviced while requests of a disabled DMA channel are ignored. The DMA channel settings of a frozen DMA channel are not changed and remain valid.
  • the DMA channel defrost register 236 includes a bit for each DMA channel.
  • Each DMA channel is associated with a DMA EDF register, such as DMA EDF resister 240. It includes three timing fields.
  • the first timing field is referred to as current counter field 242 and it stores the current value (current time) of a timing counter that is associated with the DMA channel.
  • the second timing field in referred to as threshold field 244 and it stores a threshold value that reflects the value of the timing counter when the DMA task is due.
  • the third timing field is referred to as base counter field 246 and it is stores a base counter value that is loaded to the counter when the timing counter is initialized.
  • the DMA task execution period conveniently reflects the difference between the base counter value and the threshold value.
  • a timing deadline reflects the difference between the current counter value and the threshold value.
  • DMA EDF mask register 250 includes multiple bits that can either enable or mask a generation of an interrupt request once a timing deadline occurs or is about to occur. According to an embodiment of the invention an occurrence of a possible timing violation can be indicated if a certain DMA task was not completed within a predefined sub-period of a DMA task execution period.
  • the sub-period can be defined by a sub-period threshold.
  • the DMA controller 100 or another device can perform at least one of the following operations: (i) delete the DMA task, (ii) increase the priority of the DMA task, (iii) force the execution of the DMA task, (iv) allow more than a single DMA task to be executed during the next DMA task execution period, if this is a cyclic time based DMA task, (v) force the execution of one or more DMA transactions, (vi) force the execution of one or more DMA sub-task, and the like.
  • the DMA EDF status register 254 indicates whether one or more timing violation violations occurred.
  • the DMA error register 260 includes multiple fields that indicate the occurrence of various errors. These errors can include various I/O port errors, address errors, PRAM parity check failures, FIFO errors, timing violation errors, and the like.
  • FIG. 5 illustrates a buffer descriptor table 300 according to an embodiment of the invention.
  • Each DMA channel is associated with a buffer descriptor table (BDT) .
  • BDT 300 is conveniently stored within one or more memory units 94 and starts at a BTD base address.
  • BDT 300 includes a list of buffer descriptors that can be associated with various DMA tasks of the DMA channel.
  • the BDT 300 is programmed in advance although it can be updated in various manners .
  • Each of these buffer descriptors can be a single dimensional buffer descriptor or a multidimensional buffer descriptor.
  • BDT 300 includes multidimensional read buffer descriptors collectively denoted 302 and multiple single dimensional write buffer descriptors collectively denoted 304. It is noted that the read buffer descriptors can include one or more single dimensional buffer descriptors and/or one or more multidimensional buffer descriptors. The write buffer descriptors can include one or more single dimensional buffer descriptors and/or one or more multidimensional buffer descriptors.
  • each BDT can include a large number of buffer descriptors.
  • the inventors used a DMA controller that had up to one thousand and twenty four single dimensional write buffer descriptors, but other amount and types of buffer descriptors can be used.
  • buffer descriptors can be stored within the DMA controller 100.
  • a single dimensional buffer descriptor, such as BD 310 includes four fields, BD_ADDR 312, BD_SIZE 314,
  • BD_BSIZE 316 and BD_ATTR 320 Each field is thirty two bits long.
  • BD_ADDR 312 includes a pointer that points to the current buffer entry. The pointer scans the buffer and is incremented on every DMA transaction.
  • BD_SIZE 314 indicates the size of the remaining data to be transferred in order to complete a DMA task or a DMA sub- task. This value is decremented by a DMA transaction size every time a DMA transaction is completed. Conveniently, a DMA task is completed when this field reaches zero.
  • BD_BSIZE 308 stores the base size (aggregate size of data to be transferred during the whole DMA task) of the buffer .
  • BD_ATTR 320 includes the following fields: (i) SST
  • CYC 322 that indicates whether the buffer is cyclic or incremental
  • CONT 323 that indicates whether to close the buffer when BD_SIZE reaches zero
  • NPRT 324 that indicates which I/O port to use during the next DMA task
  • N0_INC 325 that indicates whether to increment the buffers address (usually by altering the buffer offset) after a DMA task is completed
  • NBD 326 that selects the buffer that will be used for the next DMA task
  • PP 328 that sets the buffers priority that can be taken into account by MAC 98
  • TSZ 330 that indicates the size of a row of a dynamic memory unit
  • RFZ 331 that indicates whether to freeze a buffer once BD_SIZE reaches zero
  • MR 332 that indicates whether to mask requests from the DMA channel until the data sent by the
  • EDF 327 can indicate whether (a) the DMA channel and the arbiter can continue to work normally (in a continuous manner) , (b) the EDF counter should be loaded with the base counter value, or (c) the DMA task requests of that DMA channel can be masked until a predefined time period lapses from the start of the task (for example the EDF counter reaches zero) . Once the latter occurs the counter is loaded with the base counter value.
  • a DMA task of a four-dimensional buffer includes four DMA sub- tasks .
  • the multidimensional buffer descriptor 340 includes the fields of the single dimensional buffer descriptor as well as additional fields. It also includes more attribute fields then the single dimensional buffer descriptor .
  • each dimension can be monitored separately.
  • BD_SIZE a single value that indicates the remaining size of data to be transferred during a DMA task
  • C2DIM 362 the remaining repetitions of the second dimension
  • C3DIM 363 the remaining repetitions of the third dimension
  • each additional dimension has its own offset (instead of the single dimensional BD_ADDR 312 field) , and its repetition base count (BC2DIM 272, BC3DIM 273 and BC4DIM 274) that indicate the overall number of repetitions of each of the second, third and fourth dimensions.
  • the additional attribute fields in addition to fields 321-327 belong to attribute field 320' and include: LAST 341, BD 342, SSTD 343, FRZD 344, CONTD 345, and MRD 346.
  • LAST 341 indicates if the buffer is the last one in a chain of chained buffers (and if so the DMA channel is closed once the buffer is filled (write operation) or emptied (read operation) .
  • BD 342 indicates the number (such as four) of dimensions of the buffer.
  • SSTD 343 indicates whether a completion of the first, second, third or fourth DMA sub-tasks will set a completion status bit.
  • FRZD 344 indicates whether a completion of the first, second, third of fourth DMA sub-task will cause the DMA controller to freeze the DMA channel.
  • CONTD 345 defines inter-buffer jumping points by indicating when the DMA channel will switch to the next buffer descriptor- after a completion of the first, second, third or fourth DMA sub-task. CONTD 345 facilitates to switch buffers before the whole DM task is completed.
  • MRD 346 indicates when DMA channel requests are masked.
  • FIG. 6 illustrates DMA channel logic 440 and selected DMA channel logic 460, according to an embodiment of the invention.
  • DMA controller 100 can manage multiple DMA channels.
  • FIG. 6 illustrates DMA channel logic 440 and selected DMA channel logic 460, that manage a single DMA channel.
  • DMA channel logic 440 is located within channel logic and arbiter 110.
  • the channel logic and arbiter 110 includes such logic for each DMA channel.
  • Selected DMA channel logic 460 is located within DMA logic 120.
  • the DMA logic 120 includes a single DMA channel logic 460 that manages the selected DMA task requests. If, for example, the DMA controller 100 is adapted to manage more than one DMA task at substantially the same time it should include additional logics such as logic 460. For example, if DMA controller 100 is adapted to manage one DMA task per I/O port (172 and 174) then it should include two selected DMA channel logics .
  • DMA channel logic 440 includes a timing counter unit 442, and additional channel logic 448.
  • the timing counter unit 442 includes at least one timing counter, such as timing counter 444 that counts time that passed from various events, such as (i) a beginning of an execution of a DMA task, DMA sub-task or DMA transaction, (ii) a reception of a DMA task request, (iii) as election of a DMA task request, and the like.
  • Timing counter 444 can be sampled and reloaded by the additional channel logic 448.
  • the additional channel logic 444 can allow DMA task requests to be sent to the channel logic and arbiter 110 only if these DMA task requests are valid and/or can be serviced by the I/O port.
  • the additional channel logic 448 accesses various field in register file 200 and can conveniently access the buffer descriptors. For example, it accesses the DMA channel enable register 230, the DMA channel disable register 232, the DMA channel freeze register 234 and the like.
  • a DMA task request that is received ay a peripheral device or other memory mapped device and/or a request initiated by a FIFO out of FIFOs 150 can be masked by the additional channel logic 448 or can be provided to the arbiter 410.
  • the additional channel logic 448 can detect a possible timing violation (and send a possible timing violation signal) by checking whether a DMA task was completed before the counter reaches a predefined value that indicates that the DMA task execution sub-interval has passed.
  • the DMA task execution sub-interval can be included within the buffer file 200 or within a buffer descriptor.
  • the signal can be sent to various components of device 90, including core 92 or to another portion of DMA controller 100.
  • the additional channel logic 448 can receive an indication from the selected DMA channel logic 460 or from a buffer descriptor that the DMA task was completed.
  • Selected DMA channel logic 460 manages the selected DMA task or sub-task. It accesses the buffer descriptor of the selected DMA task and performs various operations such as address calculation, determining when a DMA task or DMA task has ended, deciding when to perform an inter- buffer jump, and the like.
  • Selected DMA channel logic 460 includes at least one progress counter 462.
  • the progress counter 462 is loaded with a base address once the DMA task begins and is decremented by the remaining size of data to be transferred during the DMA task or DMA sub-task by the DMA transaction size, when such a DMA transaction is completed. Once a DMA task or DMA sub-task ends the updated buffer descriptor is sent back to the PRAM 130 and to memory unit 94.
  • Selected DMA channel logic 460 also includes an address calculation unit 464 that receive various addresses and uses these address to access selected entries of a buffer (pointed by the buffer descriptor) , perform jump operations, and the like.
  • FIG. 7 is a flow chart of a method 800 for controlling multiple DMA tasks, according to an embodiment of the invention.
  • Method 800 starts by stage 810 of defining multiple buffer descriptors for each of a plurality of DMA channel; wherein at least two buffer descriptors include timing information that controls an execution of cyclic time based DMA tasks. Examples of various information included within a buffer descriptor are illustrated in FIG. 5.
  • the timing information defines a DMA task execution interval and a DMA task priority. These fields can be utilized by a method such as method 600.
  • at least one buffer descriptor includes a current iteration I/O port selection information and a next iteration I/O port selection information. If the DMA controller (such as DMA controller 100) includes multiple I/O ports then these fields define the I/O port that should be used during a current DMA task, DMA sub-task and/or DMA transaction and the I/O port that should be used during the next DMA task, DMA sub-task and/or DMA transaction.
  • at least one buffer descriptor includes arbitration type information. Thus, in view of this field the DMA controller can select an arbitration scheme, such as but not limited to the arbitration schemes of method 500.
  • Stage 810 is followed by stage 850 of receiving multiple DMA task requests.
  • Stage 850 is followed by stage 860 of selecting a DMA task request out of the multiple DMA task requests.
  • the selection can include any stage of method 500.
  • Stage 860 is followed by stage 870 of executing a DMA task or a DMA task iteration and updating the buffer descriptor associated with the selected DMA task request to reflect the execution. Stage 870 is followed by stage 860.
  • stage 870 is followed by stage 880 of generating an interrupt request once a possible timing violation is detected.
  • Stage 880 and a possible timing violation operation are followed by stage 860.
  • buffer descriptors can be updated during the execution of method 800, although this update stage is not illustrated in FIG. 11 for convenience of explanation.
  • At least one buffer descriptor is stored in a memory unit that is coupled to a DMA controller and the execution of a first iteration of a cyclic time based DMA task includes retrieving a buffer descriptor associated with the cyclic time based DMA task from the memory unit .
  • At least one cyclic time based DMA tasks includes multiple DMA sub tasks associated with multidimensional buffers.
  • the method 800 includes utilizing different I/O ports during different DMA task iterations.
  • FIG. 8 is a flow chart of a method 700 for accessing a dynamic memory unit, according to an embodiment of the invention.
  • Method 700 can start by initialization stage 710 during which row completion information is retrieved for multiple sources of DMA task requests.
  • a source can be a DMA channel, a communication channel, an entity that can request to execute a DMA task and the like.
  • Row completion information can assist in determining whether a completion of one or more DMA tasks (or a portion of a DMA task) will completely fill a row of a dynamic memory unit.
  • the row completion information may include the size of the row, the vacant row space, the size of the data transferred during an execution of one or more DMA tasks or the size of the data transferred during one or more DMA transaction.
  • DMA controller 100 can determine a vacant row portion by comparing between a current position of the read or write process (indicated by a pointer such as BD_ADD 312) and the row size (or width) that can be indicated by TSZ 330.
  • each channel can be associated with different buffer descriptors that include different values of BD_ADD 312 and TSZ 330.
  • Stage 710 is followed by stage 720 of receiving multiple DMA task requests that involve writing to a dynamic memory unit .
  • Stage 720 is followed by optional stage 730 of filtering DMA task requests that can read a complete row of a dynamic memory unit or are a part of a complete row reading group of DMA task requests.
  • stage 730 is followed by stage 740 of arbitrating between the filtered DMA task requests to select a winning DMA task.
  • Stage 740 is followed by stage 750 of performing at least one DMA transaction that belongs to the winning DMA task request.
  • stage 750 the row completion information is updated.
  • Stage 750 can include performing one or more DMA transactions and jumping to stage 740. It is noted that a sequence of DMA transactions that reads a complete row can guaranteed by either keeping the priorities of arbitrated DMA task request as is (thus the same DMA task request will win again) , by increasing the priority of the winning DMA task request, and the like.
  • FIG. 9 is a flow chart of a method 900 for accessing a dynamic memory unit, according to an embodiment of the invention .
  • Method 900 can start by initialization stage 910 during which row completion information is retrieved for multiple sources of DMA task requests.
  • a source can be a DMA channel, a communication channel, an entity that can request to execute a DMA task and the like.
  • Row completion information can assist in determining whether a completion of one or more DMA tasks (or a portion of a DMA task) will completely fill a row of a dynamic memory unit.
  • the row completion information may include the size of the row, the vacant row space, the size of the data transferred during an execution of one or more DMA tasks or the size of the data transferred during one or more DMA transaction.
  • DMA controller 100 can determine a vacant row portion by comparing between a current position of the read or write process (indicated by a pointer such as BD_ADD 312) and the row size (or width) that can be indicated by TSZ 330.
  • each channel can be associated with different buffer descriptors that include different values of BD_ADD 312 and TSZ 330.
  • Stage 920 is followed by optional stage 930 of filtering DMA task requests that can completely fill a row of a dynamic memory unit or are a part of a row filling group of DMA task requests. It is noted that the filtering can be bypassed or replaced by allowing DMA task requests to participate in the arbitration but assigning them a lower priority, and the like.
  • Stage 930 is followed by stage 940 of arbitrating between the filtered DMA task requests to select a winning DMA task.
  • Stage 940 is followed by stage 950 of performing at least one DMA transaction that belongs to the winning DMA task request.
  • stage 950 the row completion information is updated.
  • Stage 950 can include performing one or more DMA transactions and jumping to stage 940. It is noted that a sequence of DMA transactions that completely fill a row can guaranteed by either keeping the priorities of arbitrated DMA task request as is (thus the same DMA task request will win again) , by increasing the priority of the winning DMA task request, and the like.
  • a DMA controller can access both read and write DMA access in an interlaced manner.
  • FIG. 10 is a flow chart of a method 1000 for accessing a dynamic memory unit, according to an embodiment of the invention.
  • Method 1000 includes stage 1020 of receiving multiple requests to perform DMA transactions to the dynamic memory unit .
  • Stage 1020 is followed by stage 1040 of determining a size of a vacant row portion.
  • Stage 1040 is followed by stage 1060 of searching for a row filling group of DMA task requests within the received requests.
  • stage 1040 is followed by optional stage 1050 of partitioning the DMA task request to multiple DMA task requests.
  • Stage 1060 is followed by stage 1080 of executing, in a consecutive manner, multiple DMA transactions associated with the row filling group of DMA task requests .
  • Stage 1060 can be followed by optional stage 1070 of selecting between multiple row filling groups of DMA task requests associated with different rows of the dynamic memory unit .
  • stage 1060 of searching includes arbitrating between multiple DMA task requests and delaying an execution of DMA task requests that won the arbitration until they form a row filling group of DMA task requests.
  • stages of method 1000 can be applied for arbitrating between DMA tasks that read data from rows of a dynamic memory unit. It is noted that the stages of method 1000 can be applied for arbitrating between tasks that read data from rows of a dynamic memory unit and write data to rows of a dynamic memory unit .

Abstract

La présente invention concerne un procédé (1000) pour accéder à une unité mémoire dynamique, qui consiste à recevoir (1020) de multiples demandes visant à exécuter des actions d'accès direct à la mémoire (direct memory access / DMA) auprès de l'unité mémoire dynamique ; rechercher (1060) un groupe de remplissage de rangée des demandes de tâche DMA parmi les demandes reçues ; et exécuter (1080), de façon consécutive, les multiples actions DMA associées au groupe de remplissage de rangée de demandes de tâches DMA.
PCT/IB2006/050334 2006-01-31 2006-01-31 Dispositif et procédé pour accéder à des unités mémoire dynamiques WO2007088426A1 (fr)

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