WO2007082745A1

WO2007082745A1 - Selective etching for semiconductor devices

Info

Publication number: WO2007082745A1
Application number: PCT/EP2007/000413
Authority: WO
Inventors: Rémy Pascal Henri CHARAVEL; Jean-Pierre Emmanuel Octave Ghislain Raskin
Original assignee: Universite Catholique De Louvain
Priority date: 2006-01-18
Filing date: 2007-01-18
Publication date: 2007-07-26

Abstract

A manufacturing process involves ion implantation (120) of selected parts of a SiO2 layer, and vapour HF etching (140) to remove the selected ion implanted parts at a rate greater than the rate of removal of the other parts. By using ion implantation combined with a vapour etchant, the selectivity of the etching of the SiO2 can be increased to 200. Such selectivity can lead to more precise manufacturing of structures, or simpler or more cost effective manufacturing. The ion implantation can have a nuclear deposited energy larger than 2 x 1024 eV/cm3 to break sufficient SiO2 bonds. Enhancement of the etching selectivity can make implanted oxide a candidate for a sacrificial layer for MEMS devices or for buried mask definition, or for manufacturing mutually self aligned trenches for gates of double gate MOS transistors.

Description

SELECTIVE ETCHING FOR SEMICONDUCTOR DEVICES

Field of the invention: This invention relates to methods of manufacturing semiconductor devices, in particular, to methods of manufacturing a structure having an oxide layer or other layer that is made more reactive to an etchant than a semiconductor material such as silicon or to other parts of the oxide layer, by ion implantation of selected parts of the oxide layer (e.g. SiO₂ layer), and selective etching. The present invention also relates to devices obtainable by the above methods.

Description of the Related Art:

From mid 1980's to 1990's several research groups have published¹'²'³ experimental results on etch rate modification of silicon dioxide by ion implantation. The mechanisms of etch rate modification have been well understood. The collisions between implanted ions and the nuclei of the silicon dioxide target atoms from the silicon dioxide disorganize the structure of the oxide and break the Si-O bonds. It has been shown that any kind of ions could be implanted in order to modify the structure of the oxide. Once the structure has been modified it becomes more reactive to HF wet etching solutions. The literature reports selectivity of a factor of 5 between implanted and unimplanted oxide³. The etch rate modification depends on the mass of the implanted ions, the implantation dose and the energy. Although this effect is of interest from a scientific point of view, it has mainly been considered as a parasitic effect that makes the etch rate of SiO₂ difficult to control. Because of the low etching selectivity (around 5) between implanted and unimplanted silicon dioxide, the implantation of SiO₂ has not been considered for developing patterned sacrificial or etch stop layers. Silicon-on-Insulator (SOI) technology allows the fabrication of devices with reduced parasitic capacitances compared to bulk CMOS yielding higher switching speed . Another advantage of this technology is the resistance to radiation and high temperatures¹⁰. The device isolation is also easier to achieve. Thus, fully depleted SOI double gate MOS transistors are promising devices. As the active layer of double gate transistor is very thin, the inversion layer extends over the whole active silicon film, giving rise to volume conduction, which increases drain current and transconductance and decreases the floating body effect^{1 1}. The threshold voltage is better controlled and the short channel effects are reduced. The double gate architecture makes the subthreshold swing nearly ideal. As the advantages of these structures become predominant over single gate technology for very small dimensions (in the order of a few deca nanometers), it is necessary to find a fabrication method to self align the top and the bottom gates. Indeed, a misalignment of both gates would deteriorate the intrinsic performance of the double gate structure strongly and increase the parasitic capacitances, mainly the overlap capacitances. The FinFET structure overcomes the alignment problems by making a vertical double gate. However, the disadvantages of this structure are: (i) the width of the transistor is determined by the thickness of the silicon film and is fixed for all the transistors of the same chip; multi-gate fingers connected in parallel have to be considered for designing wider transistors, and (ii) the surface mobility of carriers along the vertical gates of FinFET is lower than the one for planar devices because of the surface defects introduced by dry etching of the Si fins. Planar double gate transistors overcome theses problems and allow the fabrication of transistors for any gate width over length ratio. The literature is rich in simulation results about the physical behaviour of double gate transistors¹² but few double gate transistors have been fabricated.

The inventors have previously proposed two methods for the fabrication of self aligned double gate transistors¹³. These involved defining the bottom gate by implanting boron or n-type doping in crystallized amorphous silicon layer buried within the BOX of an SOI wafer. A mask defining the top gate was deposited on the surface of the wafer. The implantation of doping in the buried layer reproduced the pattern present on the top surface of the wafer. After few steps of CMP and wafer bonding engineering the buried layer could be reached and was revealed in HNA (hydrofluoric acid, nitric acid, acetic acid) TMAH (tetra methyl ammonium hydroxide) depending on the need of a positive or negative revelation. The drawback of theses methods were the use of unconventional SOI wafers (needing a crystallized amorphous silicon layer within the BOX layer), and the need of CMP and wafer bonding, technological steps that are not easy to integrate in a process flow.

Summary of the Invention:

An object of the invention is to provide improved methods of manufacturing semiconductor devices, in particular, to improved methods of manufacturing a structure having an oxide layer or any other layer that is more reactive to an etchant than a semiconductor material such as silicon and/or than other parts of the oxide layer, by ion implantation of selected parts of the oxide layer (e.g. SiO₂ layer), and selective etching to provide devices obtainable by the above methods.

According to a first aspect, the invention provides a method of manufacturing a structure having an oxide layer such as an SiO₂ layer, having the steps of carrying out an ion implantation of selected parts of the oxide layer (e.g. SiO₂ layer), carrying out an etching by exposing the selected parts and other parts of the oxide layer (e.g. SiO₂ layer) to a vapour etchant to remove the selected ion implanted parts at a rate greater than the rate of removal of the other parts. In the case of the vapour etchant being VHF, great selectivity is thought (without being limited by theory) to be obtained because the bonds are broken by the implantation, and because HF etches SiO₂ only. Other vapour etchants are included within the scope of the invention. Etch rate of implanted Si or polysilicon or other materials can be improved by etching with TMAH or HNA. By using ion implantation combined with a vapour etchant, the selectivity of the etching of the oxide layer (e.g. SiO₂) can be increased compared to the known use of wet HF with ion implantation. This improved selectivity can reduce the amount of unwanted removal of the oxide layer (e.g. SiO₂), which can lead to more precise manufacturing of structures, or simpler or more cost effective manufacturing can be achieved. Areas to be removed can be defined by the implantation more easily or effectively than using etch resist coverings or other methods.

An additional feature of some embodiments is the etching step comprising a vapour HF etching step. This can provide the higher selectivity to avoid or reduce the problems of unwanted removal of the other parts of the oxide layer, e.g. SiO₂ layer, especially in view of the etch being isotropic. Another such additional feature is the ion implantation having a nuclear deposited energy larger than 2 x 10²⁴ eV/cm³. This can help enable the increase in selectivity by breaking sufficient SiO₂ bonds.

An additional feature is the etching step removing the selected ion implanted parts at a rate ten times greater than the rate of removal of the other parts. This is substantially greater selectivity than conventional etching without ion implantation.

An additional feature is the ion implantation being carried out in multiple different ways to implant at different depths. This can enable the rate of etching to be controlled at different depths, to vary the rate or maintain it constant over a range of depths. This helps enable more precise manufacturing of structures. Vapour HF etching has much higher etching rate of the ion implanted parts than non implanted parts, and a much higher difference in etching rates than is provided by wet HF etching. Thus etching selectivity is higher and there is less unwanted removal of non ion implanted parts.

Another such additional feature is the etching step comprising multiple cycles of etching and rinsing.

Another such additional feature is the structure being formed on a silicon-on-insulator substrate. This is a useful type of structure for many applications including MOS devices and MEMS devices.

Another such additional feature is the structure comprising a MEMS device and the method having a step of forming an actuator made of semiconductor material such as a silicon actuator part on the oxide layer (e.g. SiO₂ layer) and using the etching step to release at least part of the actuator. Another such additional feature is the structure comprising an MOS device and the method having a step of using the etching step to form a trench in the oxide layer, e.g. SiO₂ layer and at least partially filling the trench with another material. Such a trench is useful to improve integration to reduce the chip area taken up by a given element such as a gate of a transistor. Another such additional feature is the structure comprising an MOS device, and the method having the steps of forming a semiconductor region such as a silicon region having the oxide layer, e.g. SiO₂ on opposing sides of the semiconductor region, e.g. silicon region, and using the etching step to form mutually self aligned trenches on both sides of the semiconductor region, e.g. silicon region. This is useful for a number of types of structures for which mutual alignment helps to enable the device size to be reduced or manufacturing precision or cost effectiveness to be improved. One example is in manufacture of double gate MOS devices.

Another such additional feature is the oxide layer such as SiO₂ being arranged above and below the semiconductor region, e.g. silicon region, the ion implantation being arranged to extend below the semiconductor region, e.g. silicon region, to enable the mutually self aligned trenches to be etched above and below the semiconductor region, e.g. silicon region. This helps enable a planar double gate structure with gates above and below a semiconductor, e.g. silicon channel, or other structures to be achieved. Another such additional step involves filling the trenches with a material for a gate, forming an insulator around the gate, forming source and drain regions at opposing sides of the semiconductor region, e.g. silicon region, and forming contacts to the gate, source and drain regions. There are other structures that can be formed, and other ways of completing an MOS transistor device.

Another such additional feature is the structure having micro channels for micro- fluidics, and the etching step being arranged to create such micro channels. Any of the additional features can be combined together and combined with any of the aspects. Other advantages will be apparent to those skilled in the art, especially over other prior art. Numerous variations and modifications can be made without departing from the claims of the present invention. Therefore, it should be clearly understood that the form of the present invention is illustrative only and is not intended to limit the scope of the present invention.

Brief Description of the Drawings :

How the present invention may be put into effect will now be described by way of example with reference to the appended drawings, in which:

Figure 1 shows a graph of etch rate in A /min. and Argon concentration in atms/cm³ versus depth in A, Figure 2 shows a graph of etch rate in A /min. for as implanted and annealed oxide and nuclear deposited energy in eV/cm³ versus depth in A,

Figure 3 shows a graph of etch rate in function of the nuclear deposited energy for various types of implanted species,

Figure 4 shows a graph of etch rate of implanted oxide in vapour HF in function of the nuclear deposited energy,

Figures 5-a to 5-j show process steps of an alternative method for self-aligned DG MOS fabrication,

Figure 6 shows a schematic view of a structure for demonstration purposes,

Figure 7 shows results of VHF etching 30 min. at 38°C for an implanted zone, Figure 8 shows results of VHF etching 30 min. at 38°C for an unimplanted zone,

Figure 9 shows results of VHF etching 15 cycles of 2 min. etching and 3 min. 20 sec. N₂ rinsing at 38°C for an implanted zone,

Figure 10 shows results of VHF 15 cycles of 2 min. etching and 3 min. 20 sec. N₂ rinsing at 38°C for an unimplanted zone,

Figure 11 shows results of VHF 15 cycles of 2 min. etching and 3 min. 20 sec. N₂ rinsing at 38°C for unimplanted and implanted zones,

Figure 12 shows results of VHF 7 cycles of 4 min. etching and 5 min. N₂ rinsing at 38⁰C for an implanted zone,

Figure 13 shows results of VHF 7 cycles of 4 min. etching and 5 min. N₂ rinsing at

38⁰C for an unimplanted zone,

Figure 14 shows results of VHF etching 10 min. at 52⁰C for an implanted zone,

Figure 15 shows results of VHF etching 10 min. at 52°C for an unimplanted zone, Figure 16 shows results of VHF 3 cycles of 10 min. etching and 5 min. N₂ rinsing at

52°C for an implanted zone,

Figure 17 shows results of VHF 3 cycles of 10 min. etching and 5 min. N₂ rinsing at

52°C for an unimplanted zone,

Figure 18 shows typical under etch in the anchor area for a released interdigitated capacitor,

Figure 19 shows an implanted sample after VHF release,

Figure 20 shows an unimplanted sample after VHF release,

Figure 21 shows some of the principal steps according to an embodiment, and

Figure 22 shows steps in an embodiment involving forming suspended silicon wires for a gate all around device, or other device.

Detailed Description of Embodiments:

The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual reductions to practice of the invention. It is to be noticed that the term "comprising", used in the claims, should not be interpreted as being restricted to the means/steps listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B. The invention will now be described by a detailed description of several embodiments of the invention. It is clear that other embodiments of the invention can be configured according to the knowledge of persons skilled in the art without departing from the true spirit or technical teaching of the invention, the invention being limited only by the terms of the appended claims. Embodiments of the invention relate to process steps which may be usefully applied to the manufacturing of MEMS devices, of double gate MOS transistors and many other types of devices as well as to the devices themselves. The embodiments show process steps including implanting an oxide rather than a semiconductor, as is usually done. This oxide is therefore made very reactive to an etchant such as HF (hydrofluoric acid) in its vapour phase. It is therefore readily etched contrary to a non-implanted oxide. The implantation enables variation of the speed of etching of a same oxide and therefore on the selectivity of the etching between the implanted zones and the non-implanted zones. It is then possible to define by implantation, trenches buried (e.g. under a silicon film) in an oxide. This enables, for example, defining trenches by implantation above and below a thin Si film or other materials. Implantation through any suitable film is included within the scope of the present invention, the film preferably not being etched by HF. Alternative films include polysilicon films or films made of other semiconductor materials such as SiGe, Ge, SiC, etc. The above mentioned trenches will be auto-aligned because they are created simultaneously, with the same mask, and then, a standard MOS process can continue to make the complete MOS DG (double gate) transistor, or other device. This enables auto-aligned double gate transistors because of the creation of a mask buried in the oxide (BOX) of a SOI (silicon-on-insulator) layer. Other applications such as the relaxing of MEMS structures or the creation of sacrificial oxide layers are feasible as well. In the following the use of a silicon oxide layer is described but the present invention is not limited thereto.

The etching speed of the silicon oxide can be increased by a factor of at least 50 times or at least 100 times or at least 200 times. For example, the etch rate of unimplanted oxide is typically 10 Angstrom/min whereas the etch rate of implanted oxide can be 2000 Angstrom/min., e.g. 200 times or more, when the oxide has been treated beforehand by ionic implantation and the etching is performed by hydrofluoric acid (HF) in its vapour phase. This very high selectivity between implanted and non- implanted oxide facilitates the making of buried masks or can accelerate the relaxing speed of MEMS structures for example. Enhancement of the etching selectivity up to a value of more than 50, more than 100 or more than 200 by using a vapor etchant such as vapor HF instead of wet HF etching opens new possibilities in microelectronics and MEMS technology, making implanted oxide a better candidate for a sacrificial layer or for buried mask definition and conjointly unimplanted oxide a good etch stop layer. Manufacturing of auto-aligned double gate (DG) MOS transistors may prove a particularly commercially valuable application as DG transistors are currently seen as a very promising technology for improved scalability and performance as they develop over the next 5-10 years. Other structures may be formed exploiting the advantages of auto-aligned structures on various levels, i.e. not necessarily MOS DG transistors but for instance implementations of electrodes (MEMS) or micro-channels (micro-fluidics) auto-aligned on various levels defined by implantation and selective etching. For example the large etching selectivity between the implanted and the non-implanted oxide in gaseous HF can be used as well in order to better define the anchoring of MEMS as "cantilevers" or "clamped beams". Indeed, silicon oxide is nowadays used as a sacrificial layer for the releasing of microstructures in liquid HF (hydrofluoric acid). The oxide etching being isotropic, it is difficult to obtain with precision the non-etched zones, i.e. the anchoring. The silicon oxide can be created in many ways, e.g. 1200 nm wet thermal oxide grown at 975 °C, 1000 nm TEOS (tetraethoxysilane) deposited by a CVD process at 670 °C.

First application: Etch rate modification in ion damaged silicon dioxide

The increase in etch rate for implanted oxide has been investigated for both aqueous and for vapor forms of HF and for different implanted species like Boron, Phosphorous, Arsenic, Argon. The parameter directly linked to the etch rate modification is the nuclear deposited energy which depends on the incoming ion mass and energy, the target atoms and the implanted dose. For a nuclear deposited energy larger than say 4e24 eV/cm³ the etch rate increases drastically. It has been shown that in aqueous solution a selectivity of 4 between implanted and unimplanted oxide could be reached. The etching selectivity has been increased to a value of at least 50 times, at least 100 times or at least 200 times when etching in vapor HF. Water being a reaction product and a catalyst for oxide etching, the reaction kinetic increases much more in the implanted zone which are easily etched, than in the unimplanted zone which are etched more slowly. This new technique opens many process possibilities like buried mask creation or etch stop layer creation.

Experimental details: 3000 A thermal oxide were grown in wet ambient at 1000 °C on 3 inches p-type, <100> oriented silicon wafers. The oxide thickness was accurately measured by ellipsometry. A photolithography was done before the implantation defining implanted and unimplanted zones. Boron, Phosphorous, Argon and Arsenic were implanted at different energies and doses in the oxide layer through the photoresist mask. After implantation the resist was stripped by oxygen plasma and H₂O₂ZH₂SO₄ cleaning and the samples were diced in 1 cm² pieces. The wet HF etching was done in 3% HF solution diluted in DI water. The vapour HF etching was performed on a GEMETEC PAD-Fume, commercially available system for wafer cleaning that was adapted according to custom specifications to enable stiction-free surface micromachining. The gas flow (nitrogen bubbling through a 49% HF solution) was 1 1/min. and the temperature was 38°C. Etchings were performed during two or five minutes, depending on the etch rate of the implanted oxide. The remaining thicknesses of implanted and unimplanted oxide were measured after etching by ellipsometry.

Wet etching example for comparison with vapour etching

Previous studies have¹'²'³ shown that implanted oxide layer could be etched in buffered HF (BHF) or in diluted HF up till five times faster than unimplanted oxide. The enhancement of the etching rate is due to the highest reactivity of the Si-O bonds of oxide broken during implantation. A 3000 A thick oxide layer has been implanted with argon at energy of 160 keV and a dose of 2el4 atms/cm². The etch rate in HF 3% was measured in function of the depth. Figure 1 superposes the Argon concentration and the etching rate in function of depth. From the surface of the oxide layer to a depth of 2000 A the etch rate has a constant value of 300 A /min. From 2000 A to 2600 A, the etch rate drops abruptly to reach a value of 100 A/min. The argon concentration, plotted in logarithmic scale, is roughly IeI 7 atms./cm³ close to the surface, and reaches a maximum of IeI 9 atms./cm³ around a depth of 1900 A. From 2600 A the argon concentration is still rather high at a value of 2el8 atms./cm³. It is thus not possible to correlate the Argon concentration to the etch rate modification.

A. Hiraiwa et al. ² reported that the enhancement of the etch rate is due to the destruction of the Si-O bonds of the silicon dioxide. When an ion penetrates a material, it undergoes collisions with the atoms of the target until it loses its total amount of energy. In each collision the energy is transferred from the ion to the atoms. If the transferred energy is high enough, the Si-O bonds can be broken or reconstructed if they were already broken. The transferred energy is the parameter that we will use to characterize the implantation rather than the dose or the doping profile after implantation. As the mass of the electrons is 3 orders of magnitude smaller than mass of the nuclei, we consider that the implanted ion suffer collisions only with the nuclei of the silicon dioxide target. The energy transferred from the incoming ion to a nuclei of the target is called the nuclear energy loss. The nuclear deposited energy E_n is given by: E_n = V_n -D ₍₁₎

Where η_n is the nuclear energy loss and D the implanted dose. The loss of energy of the Ar ions into the oxide film was simulated with the freeware SRIM⁴.

Figure 2 plots the nuclear deposited energy and the etch rate for as implanted and annealed samples in function of the depth in the SiO₂ layer. The nuclear deposited energy has a constant value from the surface to a depth of 1600 A and then decreases logarithmically. The nuclear deposited energy curve and the etch rate curve of the as implanted sample perfectly superpose to each other. This result demonstrates that the destruction of the Si-O bonds, characterized by the nuclear deposited energy is the mechanisms responsible for the enhancement of the etching rate. In order to check the validity of this hypothesis, the Ar implanted sample was annealed at 1000 °C under a nitrogen flow of 1.5 l./min. during 40 minutes. The plot of the measured etch rate after annealing does not show any dependence in function of the depth and the etch rate value is 80 A/min., similar as the value obtained for unimplanted oxide. The annealing step of the implanted oxide samples reconstructs the Si-O bonds and the etching selectivity of 4 that was obtained between implanted and unimplanted oxide is lost.

As the etch rate of oxide is influenced by the amount of destructed Si-O bonds and not by the implanted ions, it was tried to implant other species than argon, like boron, phosphorous and arsenic. Figure 4 plots the etch rate of oxide in HF 3% in function of the nuclear deposited energy for different implanted species.

The graph confirms that the type of implanted species has no influence on the etch rate.

The only parameter to consider is the nuclear deposited energy. A nuclear deposited energy lower than Ie23 eV/cm³ does not change the etch rate of oxide in HF 3%, i.e. 80

A/min. Above 3e24 eV/cm³, the etch rate saturates at an average value of 320 A/min.

Garrido et at. have shown that not more than 15.5% of the Si-O bonds can be broken.

Indeed they demonstrate that above a certain concentration of nuclear deposited energy a steady state occurs between formation and breaking of Si-O bonds. The etch rate of implanted oxide can be enhanced by a factor 4 when etched in HF 3%. Whatever the type of implanted species, a maximum etch selectivity of 4 was reached in HF 3%.

However, for a given implantation energy, light species will penetrate and then dissipate their energy deeper into the target layer than heavier species, but with a lower average value. Thus, if the structure of the oxide has to be modified over a given thickness, the energy will have to be higher for heavier species than for lighter species but the dose to implant for reaching a given nuclear deposited energy concentration will be lower for heavier species than for lighter ones.

Vapor HF etching Etching of implanted oxide has also been done in vapor HF. Figure 5 plots the etch rate in function of the nuclear deposited energy for an oxide film implanted with phosphorous. 3000 A thick oxide film was implanted at two different energies and doses in order to get a constant nuclear deposited energy concentration over the whole film thickness. The increase in etch rate occurs for the same concentration of nuclear deposited energy as in the case of the wet etching, but the etching selectivity between implanted and unimplanted oxide which was around 4 in the case of wet etching is in the range of 200 for vapour HF etching. Without being limited by theory, the great difference in selectivity can be explained knowing the etching mechanism of SiO₂ in HF. The etching of silicon dioxide in vapour HF has been well described in previous publications⁶'⁷'⁸ Water plays a key role in the etching. Its presence is necessary to start the reaction. First of all, HF is decomposed into a H⁺ ion and a F^" ion due to the presence of water:

HF + H₂O → F^~ + H⁺ - H₂O „) The fluorine ion binds itself to HF: HF + F- → HF₂- p.

HF_2- is the ion responsible for the oxide etching: SiO₂ + 3HF₂- + H⁺ → SiF₆ ^" + 2H₂ O ₍₄₎

The reaction produces water and fluosilicic acid. The fluosilicic acid undergoes the following reaction:

2H⁺ + SiF₆ ^" → H₂ SiF_{6 (5)}

H₂ SiF₆ → 2HF + SiF_{4 (6)} The SiF₄ evaporates and HF is reused by the reaction.

Fluosilicic acid can also attack the oxide following the reaction:

55/F₆ ^" + 4H⁺ + SiO₂ → 3(SiF₆.SiF₄ )^" + 2H₂ O _(?)

O ^* C —

However ^{l 6} is easily recombined in presence of H⁺ ions into H^SYF_ό so that the last equation is of minor importance in the etching of silicon dioxide. As described above in vapour HF, the etching mechanism needs water to initiate the reaction. Condensation has to occur on the wafer surface for starting the reaction. Once the reaction has started, water is produced by the reaction and enhances the etch rate. The etch rate will strongly depend on the amount of water produced by the etching. This is a kind of avalanche effect. In the case of the wet etching, the quantity of water as reaction product is negligible in comparison to the water quantity in which HF is diluted and therefore does not influence the kinetic of the reaction. The etch rate mainly depends on the HF, HF_2- and broken bonds concentration, but not on the reaction byproducts. In the case of vapour etch, water is the limiting factor of the reaction kinetic. Some water comes from condensation but after a transition step the main origin of the water is from reaction by-products. The avalanche effect will thus be multiplied by the highest reactivity of the oxide due to the presence of broken bonds and the fact that more water is produced in the damaged zone than in the non-implanted oxide. Selectivity of 200 can thus be achieved.

Conclusions for the first application

The etch rate increase of implanted oxide has been verified in diluted HF for various implanted species. The parameter which control the etch rate is the nuclear deposited energy, E_n which depends on the atoms of the target, the mass and the dose of the implanted ions. For a nuclear deposited energy lower than Ie23 eV/cm³, the etch rate is not modified and for a nuclear deposited energy larger than 3e24 EV/cm³, the etch rate reaches its maximum value. Light or heavy ions can both be implanted. Heavy ions will have a shallow penetration while the light ions will penetrate deeper in the film. To reach the same level of nuclear deposited energy, higher dose has to be considered for light ions as their nuclear energy loss is lower than for heavy ions. In the case of implantation through a silicon film, silicon or argon can be implanted to avoid contamination. The use of vapour HF etching instead of diluted HF increases the selectivity from 4 to at least 50times, at least 100 times; or at least 200 times. The dissolution of silicon dioxide in HF is an autocatalytic reaction which only needs water to be initiated. In vapour HF etching, the water produced by the reaction will be preponderant compare to the total amount of water taking part to the reaction yielding to an avalanche effect and a drastically increases of the etch rate. This very high selectivity opens very promising applications such as buried mask patterning in oxide and definition of sacrificial layers.

Application 2: Buried mask revelation in silicon dioxide for double gate MOS fabrication, Fig 5

A new process for self-aligned double gate MOS fabrication is proposed. The milestone of this process is the revelation of a buried mask in the BOX of a SOI wafer and in a thermal oxide layer on top of active silicon film. The revelation of the buried mask makes use of the highly selective etching of implanted oxide in VHF. The etching mechanism of VHE etching of oxide is presented and the influence of the VHF etching parameters like temperature and etching time are discussed to prove the feasibility of this process step in order to integrate it in the whole process. The method proposed here helps avoid the two problems of previous self-alignment techniques discussed above, but keeps the self alignment by implantation of a buried mask. A selective etching of oxide has been developed which enables the bottom gate to be defined directly in the BOX. The process flow is presented hereafter. The oxide buried mask is based on the etching selectivity of implanted oxide. The process steps are described with reference to Figures 5-a to 5-j.

A conventional SOI wafer (Figure 5-a) is oxidized (Figure 5-b) and the gates are patterned by lithography. An implant is performed through the mask in the top oxide layer and in the BOX layer to define a sacrificial buried mask for the top and bottom gates (Figure 5-c). To insulate the devices from each other, the choice of a MESA process was made for this example, other conventional techniques are feasible. The active zones are defined by lithography and RIE of the top oxide layer and the SOI layer. The RIE stops on the BOX (Figure 5-d). The etching of the implanted oxide is done in vapor HF and yields two self-aligned cavities (Figure 5-e). This leaves a free standing silicon bar, which will be the future channel of the transistor. The gate oxide is then grown and the channel implant is performed before the polysilicon gate deposition (Figure 5-f). The filling of the bottom cavity has been proven to be successful¹⁴ for double gate transistors with a ratio W/L of 60 μm/3 μm. The gate is defined by RIE in an SF₆ based plasma (Figure 5-g). The top oxide layer is removed by RIE in a CF₄/H₂ in the source and drain area. To avoid misalignment problems, the source and drain area is defined 2 μm smaller in x and y direction than the active zone (Figure 5-h). Once the source and drain implantation has been performed, the passivation layer is deposited and the contact holes are opened by RIE (Figure 5-i). The metallization to create contacts for the various regions then ends the process (Figure 5-j). The critical step of this technique is the revelation of the buried mask in oxide layers surrounding the thin active Si layer. The next part below describes the etching mechanism of implanted oxide in more detail.

Etching selectivity of implanted oxide When an ion penetrates a material, it undergoes collisions with the nuclei of the target until it lots its total amount of energy. In each collision the energy is transferred from the ion to the nuclei. The energy transferred is called the nuclear deposited energy, E_n. This energy transfer can be sufficient to break the valence biding between the atoms of the target, or to reconstruct this binding if it was broken. When silicon dioxide is implanted the breaking of the Si-O bonds is balanced by the recombination when the proportion of destruction bonds reaches 15%' The destructed Si-O bonds present a highest reactivity to HF etching⁵'¹⁵ The etch rate increase of implanted oxide has been verified in diluted HF¹' ' for various implanted species. The nuclear deposited energy is strongly linked to the etch rate modification due to implantation. It is calculated by multiplying the nuclear energy loss η_n by the dose D. E_n = V_n-D η_n depends on the atoms of the target and on the mass of the implanted ions. η_n has been calculated using the freeware SRIM. As the etch rate measurement is averaged over the whole film thickness, the implantation has been performed at two different doses and energy to ensure a constant nuclear deposited energy over the whole film thickness. Phosphorous has been implanted at 60 keV for 16.5% of the total dose and at 190 keV for 83.5% of the total dose. A total dose of 2el3 atms./cm² yielding an average nuclear deposited energy of 5e22 eV/cm³. The total implantation range varies from 2el3 atms./cm² to 5el5 atms./cm², yielding an nuclear deposited energy range between 5e22 and 2e25 eV/cm³.

Figure 4 gives the etch rate in function of nuclear implanted energy for Boron and Phosphorous ions implanted in a 3000 A thick oxide layer. For a nuclear deposited energy lower than Ie23 eV/cm³ the etch rate is not modified but for a nuclear deposited energy larger than 1 e25 eV/cm³ the etch rate does not increase any more, the proportion of 15% of broken bonds being reached. Light or heavy ions can both be implanted. Heavy ions will have a shallow penetration in the film while the light ions will penetrate deeper in the film. To reach the same level of nuclear deposited energy, the dose for light ions has to be increased as their nuclear energy loss is lower than for heavy ions.

Demonstration of mutually self aligned cavities

Vapor HF etching being highly selective, it is a good candidate to reveal the buried mask defined by implantation in oxide. When the buried mask has to be revealed, cycling of VHF etching and nitrogen rinsing steps are preferably introduced in order to maintain a good etching selectivity. A demonstration of two self aligned cavities above and below the SOI film was made using selective etching of implanted oxide. Starting from a standard SOI wafer from the company SOITEC, on top of this 1960 A of oxide was grown in wet ambient at 1000 °C during 19 minutes. The final structure had the following thicknesses: BOX 4000 A / SOI 820 A / thermal oxide 1960 A. A dark field photolithography was performed to define the gates dimension (length and width). Implanting silicon would have the great advantage that the SOI film would not be contaminated, however for the demonstration phosphorous was used which has an atomic weight close to the one of silicon. The implantation dose and energy were calculated with the software SRIM⁴ in such a way that the nuclear deposited energy was higher than 4e24 eV/cm³ in the top oxide layer and in the 2000 A from the BOX close to the SOI. High energy implantation was done at 290 keV at a dose of IeI 5 atm/cm², the low energy implantation was done at a 150 keV at a dose of 2el4 atm/cm². After implantation the resist was stripped by oxygen plasma and H₂O₂/H₂SO₄ cleaning. A second photolithography was done to define the opening to access the implanted BOX after a RIE step. The top and buried oxide layers were etched in a CF₄/H₂ plasma, the SOI layer in a SF₆ plasma. The resist was strip by oxygen plasma and H₂O₂/H₂SO₄ cleaning after RIE. Figure 6 shows in schematic form a cross section of the demonstrator.

The vapour HF etching was performed on a GEMETEC PAD-Fume, commercially available system for wafer cleaning that was adapted according to custom specifications to enable stiction-free surface micromachining. The gas flow (nitrogen bubbling through a 49% HF solution) was set to 1 1/min. Etching were performed either in one time or in short steps between which N₂ rinsing was done. The temperature was varied from 38°C to 52°C. Figure 7 and 8 show SEM cross sections of the demonstrator after 30 min. VHF etching at 38°C for both implanted and unimplanted area. The top oxide is oxide is totally etched in the both cases. The underetch is 1.5 μm in the unimplanted zone and 4 μm in the implanted zone. The selectivity is very bad, as in case of wet etching. Although this result is poor, it brings important information. After a too long etching time, a large amount of water is produced and condenses over the whole wafer, and thus transforms the etching into wet etching.

To overcome this effect and keep the selectivity due to the etching in VHF, the etching was performed in short steps between which N₂ rinsing was done. The rinsing steps in between the etching steps allows the water produced during etching to evaporate and avoid any condensation on the oxide which has not been implanted. Figures 9 and 10 shows SEM cross section after 15 cycles of 2 min. etching and 3 min. 20 sec. N₂ rinsing.

The result is here very good. There is no underetch in the unimplanted area and the top oxide is also preserved. In the implanted area the underetch is 1 μm and the top oxide is totally removed. Figure 10 shows the respective size of the top and bottom cavities. The top cavity is roughly 700 run larger than the bottom cavity. A hypothesis is that the lateral scattering of the energy loss is high close to the surface but it was not possible to verify it by simulation. The etching was also tried with longer etching steps. Figure 12 and 13 shows SEM cros- section of the demonstrator which suffered 7 cycling of 4 minutes etching and 3 min. 30 sec. N₂ rinsing. Although the total etching time was almost the same as for the 2 min. cycles, the underetch is here 3.2 μm in the implanted zone instead of 1 μm previously.

The larger the etching time, the more water condensate appears on the oxide surface and thus enhances the etch rate, but in this case the top oxide is also slightly attacked, which is not a good result.

The etching time during each cycle is a notable parameter. 2 min. is a good value.

Etchings at 52°C were also performed, as at higher temperature less water condenses.

Figures 14 and 15 shows SEM cross section of the demonstrator etched during 10 minutes at 52°C. This time and temperature combination gives very good results. The underetch is 3.1 μm in the implanted zone and almost null in the unimplanted zone where the top oxide is also totally preserved.

An attempt was made to perform 3 cycles of 10 minutes etching with 5 minutes N₂ rinsing at 52°C. Figure 16 and 17 shows the SEM cross section. This combination of parameters does not give such good results. The top oxide in the unimplanted zone is totally removed. The rinsing time might be too short to evaporate all the water condensed on the surface.

Conclusions for the second application A new process for self-aligned double gate fabrication in SOI technology has been disclosed above. It is based on the revelation of a buried mask in a thermal oxide grown on top of a SOI wafer and in the BOX. The revelation of the buried mask makes use of the very high selectivity of VHF etching between implanted and unimplanted oxide. The VHF etching parameter like temperature and etching have been tuned to demonstrate the feasibility of the critical step which is the buried mask revelation. Temperature of 52°C allows etching time of 10 minutes and keeps the selectivity at a high value. Temperature of 38⁰C has to be performed during time of 2 minutes directly followed by a N₂ rinsing. Longer etching time at this temperature decreases the selectivity because too much water condensate on the wafer surface and change the behavior of the etching in a wet-like etching. Etching time of 10 min. at 52°C or cycling with etching steps of 2 min. and rinsing time of 3 min. at 38°C are a good set of parameters for VHF revelation of the buried mask. This process step can be readily integrated in the self-aligned double gate MOS process.

Application 3: MEMS underetch reduction by highly selective etching of oxide

Most of the SOI MEMS use the BOX layer as sacrificial layer to release beams and microstructures. This release is done in vapor HF based chemistry without implantation. Vapor HF has the advantage of avoiding stiction problems. The drawback of this technique is that the under etch in the anchor area is as large as the half of the largest dimension of the beam to release. A highly selective etching method of silicon dioxide has been developed to overcome this problem. Ion implantation in oxide increases by a factor of 200 the etch rate of oxide in vapor HF. By implanting the zone to release, the under etch can be avoided in the anchor area, which is not implanted. As the modification in etch rate arises from the destruction of the Si-O bonds during implantation, any species can be implanted, as for example phosphorous and boron but also argon or silicon, which do not contaminate the top film through which the implantation is done. Figures 18-20 describe the etching mechanism of implanted silicon dioxide in wet and vapor HF chemistry and gives examples of reduced under etch for particular etching conditions.

The improvement in etch rate was done by etching the implanted silicon in vapor HF. It was performed on a GEMETEC PAD-Fume. The gas flow (nitrogen bubbling through a 49% HF solution) was 1 1/min. and the temperature was 38°C. Fig. 3 shows the etch rate for phosphorous and boron implanted samples in function of the nuclear deposited energy.

The very high etching selectivity solves or reduces the problem of under etching when releasing a MEMS structure. Fig. 18 shows a typical under etch for a released array of beams. By performing before the release an implantation of sufficient dose and energy in the oxide to be released, one can practically suppress the under etch. A demonstrator was made of a SOI wafer from which the BOX was implanted through the silicon film with phosphorous at a dose of 3.2el5 atm./cm² and an energy of 150 keV, yielding a nuclear deposited energy of 4e24 eV/cm³. Openings were made by RIE in the silicon film to reach the BOX. Fig. 19 and 20 show respectively an implanted and unimplanted sample after 7 cycles of 4' VHF etching at 38°C and 3' N₂ rinsing. 4 μm were etched in the case of the implanted sample and nothing in the case of the unimplanted sample. It is a very good result to suppress the under etch which occurs when releasing MEMS structure. This technique has a variety of applications including creation of cavities in a buried film and is a good candidate to fabricate self aligned double gate MOS using a buried mask in the BOX of a SOI wafer. However this process does not support any thermal budget as an annealing will recombine the destructed Si-O bonds and thus will not affect the etch rate of HF any more.

Figure 21 shows an overview of some principal steps according to an embodiment for any of the applications. Step 100 shows forming an SiO₂ layer on a substrate. Step 110 represents optional other steps in the manufacturing process. Step 120 shows ion implantation into selected parts of the SiO₂. Step 130 shows optional other steps provided there is no thermal annealing. A selective etch to remove ion implanted parts of SiO₂ at greater rate than removal of non implanted parts is carried out at step 140. At step 150 optional other steps according to the application are carried out to complete the device.

Fig 22, application to suspended silicon wires

Figure 22 shows a further application. The use of the definition of a trench in the BOX of a SOI wafer by implantation and vapour HF etching developing can be used not only for the manufacture of a double-gate MOSFET transistor but also for a quadruple-gate (also called Gate-Ail-Around (GAA)). As illustrated in Figure 22 a technique for making suspended silicon wires (which can be thin enough to be called nanowires) can be applied with a defined buried trench perfectly aligned to the top implantation mask. The implanted buried oxide is removed selectively in vapour HF. Figure 22 shows steps in the fabrication of suspended Silicon nanowires in accordance with an embodiment of the present invention above a revealed trench in the BOX of a SOI wafer self-aligned to the polysilicon implantation mask.

A first step is to provide a silicon layer on an oxide layer on a substrate. The top silicon layer is etched to provide a pattern of wires to be suspended. A next step is removal of HSQ (hydrogen silsequioxane) Subsequently a chemical vapour deposition step is used to deposit an oxide layer covering the pattern such as a PECVD oxide layer. A thicker layer of polysilicon is deposited on top, followed by a second CVD oxide layer such as a PECVD oxide layer. After application of a resist layer, e.g. a PMMA spin coating, and developing of the resist, an etch step is carried out of the PECVD oxide layer to thereby etch the second oxide layer in the region of the pattern of wires. The resist layer, e.g. PMMA, is then removed, and a polysilicon etch step is carried out to etch the polysilicon above the pattern of wires. Then a further etch is carried out to remove the second oxide layer, and to remove the first oxide layer in the region of the pattern of wires. The buried oxide can then be implanted in the region of the pattern of wires, as has been described above. The dimensions of the nanowires can be characterized by: a height and a width of a few nm (e.g. 2-12nm) to a few tens of nm (e.g. 30-100nm), and a length of a few tens of nm (e.g. 10 to lOOnm) depending on the channel length of transistor to build. For GAA transistors, for example, that will be of interest for MOSFETs, these have a channel length well below 100 nm (i.e. 30 nm and below). In this embodiment polysilicon can be used for the implantation mask but the present invention is not limited thereto. The purpose of the implantation mask is to stop the implanted ions to protect the silicon area. Other materials could be used, such as silicon nitride, silicon dioxide, a metal layer, etc. Also the nanowires, can be made of silicon but they could be also made from other semiconductor materials such as SiGe, Ge, SiC, etc. For the gate stack, silicon dioxide may be used for the insulator and polysilicon for the gate material, but a high-k dielectric layer and a metallic gate can be included into the proposed GAA process.

The last part of fig 22 shows the result of a subsequent reveal step, to leave suspended silicon nanowires over a revealed narrow trench in BOX defined by implantation and vapour selective etching, e.g. HF vapour etching. When nanowires or a trench or cavity have to be revealed, cycling of VHF etching and nitorgen rinsing steps are preferably introduced in order to maintain a good etching selectivity.

After the revelation of the implanted oxide in etching vapour, e.g. HF, the gate dielectric layer can be grown (e.g. a thermal silicon dioxide) or conformly deposited (using an Atomic Layer Deposition machine for instance, for high-k materials) as well as the gate material (doped polysilicon or mid-gap metal gate) all around the suspended silicon nanowires. After the metal gate deposition, a Chemical Mechanical Polishing (CMP) step can be used for removing the metal layer outside the transistor channel, using the implantation mask as polishing stop layer. The implantation mask is then selectively removed, the source/drain regions implantation is performed and metallic interconnections are made to finalize the fabrication of GAA or quadruple gate self- aligned MOSFETs.

Silicidation (resistive or Schottky contacts) of the source and drain contacts could be also introduced.

Other remarks: Other embodiments can be envisaged, and other conditions or process steps can be used. For the VHF etching, other temperatures, pre-heat times, cycle times, flow rates, HF concentrations, etch times and rinse parameters can be used to suit the application as appropriate.

References

¹ C. Dominguez, B. Garrido, J. Montserrat, J. R. Morante and J. Samitier, Etching rate modification in silicon dioxide by ion implantation and rapid thermal annealing, Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms, Volumes 80-81, Part 2, pp. 1367-1370 (1993)

² A. Hiraiwa, H. Usui, K. Yagi, Novel characterization of implant damage in Siθ₂ by nuclear deposited energy, Applied Physical Letters, Volume 54, Part 12, (1989)

³ L. Liu, K.L. Pey, P. Foo, HF wet etching of oxide after ion implantation., Electron Devices Meeting, 29 June 1996, IEEE Hong Kong, pp. 17-20, (1996).

⁵ B. Garrido, J. Samitier, S. Bota, C. Dominguez, J. Montserrat, J.R. Morante, Structural damage and defects created in SiO ₂ films by Ar implantation, Journal of non crystalline Solids, No 187, pp. 101-105, (1995) ⁶ D. F. Weston, RJ. Mattox, HF vapour phase etching (HF/VPE): Production viability or semiconductor manufacturing and reaction model, Journal of vacuum science and technology, No 17, Volume 1, pp. 466-469, (1980)

⁷ P.J. Holmes, J. E. Snell, A vapour etching technique for the photolithography of silicon dioxide, Microelectronics and reliability, Volume 5, pp. 337-341 , (1966)

⁸ CR. Helms, B. E. Deal, Mechanism of the HF/H2O vapor phase etching ofSiθ2, Journal of vacuum science and technology A, No 10, Volume 4, (1992) ⁹ M. Yoshimi, Solid-State Electronics, Vol. 46, (2002), pp. 951-958

¹⁰ Y. Li et al, Solid-State Electronics, Vol. 47, (2003), pp. 1111-1115

¹¹ M. Cass et al, Solid-State Electronics, Vol. 48, (2004), pp. 1243-1247

¹² TJ. Walls et al., Solid-State Electronics, Vol. 48, (2004), pp. 857-865

¹³ R.Charavel, J. -P. Raskin, Self-alignment method by buried mask implantation for double gate and nano devices fabrication, SPIE, Vol. #5592, 2004.

¹⁴ Ref MING

¹⁵ P. Mazzoldi, A. Camera, F. Caccavale, and M. L. Favaro, N and Ar ion-implantation effects in Siθ₂ films on Si single-crystal substrates, Journal of applied physics, Volume 70, No 7, pp.3528-3536, (1991)

Claims

Claims:

1. A method of manufacturing a structure having an oxide layer, having the steps of carrying out an ion implantation (120) of selected parts of the oxide layer, carrying out an etching (140) by exposing the selected parts and other parts of the oxide layerto a vapour etchant to remove the selected ion implanted parts at a rate greater than the rate of removal of the other parts.

2. The method of claim 1 wherein the oxide layer is a silicon dioxide layer.

3. The method of claim 2, the etching step comprising a vapour HF etching step.

4. The method of any of claims 1 to 3, the ion implantation having a nuclear deposited energy larger than 2 x 10²⁴ eV/cm³.

5. The method of any preceding claim, the etching step removing the selected ion implanted parts at a rate at least ten times greater than the rate of removal of the other parts.

6. The method of any preceding claim, the ion implantation being carried out in multiple different ways to implant at different depths.

7. The method of any preceding claim, the etching step comprising multiple cycles of etching and rinsing.

8. The method of any preceding claim, the structure being formed on a silicon-on- insulator substrate.

9. The method of any preceding claim, the structure comprising a MEMS device and the method having a step of forming a semiconductor actuator on the oxide layer and using the etching step to release at least part of the actuator.

10. The method of any preceding claim, the structure comprising an MOS device and the method having a step of using the etching step to form a trench in the oxide layer and at least partially filling the trench with another material.

11. The method of any preceding claim, the structure comprising an MOS device, and the method having the steps of forming a semiconductor region having the oxide layer on opposing sides of the semiconductor region, and using the etching step to form mutually self aligned trenches in the oxide layer on both sides of the semiconductor region.

12. The method of claim 11, the oxide layer being arranged above and below the semiconductor region, the ion implantation being arranged to extend below the semiconductor region to enable the mutually self aligned trenches to be etched above and below the semiconductor region.

13. The method of claim 12, having the step of filling the trenches with a material for a gate, forming an insulator around the gate, forming source and drain regions at opposing sides of the silicon region, and forming contacts to the gate, source and drain regions.

14. The method of any of claims 1 to 8, the structure having micro channels for micro-fluidics, and the etching step being arranged to create such micro channels.

15. The method of any preceding claim, having the step of forming one or more semicoductor wires, and using the etching step to leave the wire or wires suspended.

16. The method of claim 15, having the steps of forming a gate material around the suspended semiconductor wire or wires, to form a self-aligned gate all around device.