WO2007082626A3 - Method and apparatus for error correction decoding - Google Patents
Method and apparatus for error correction decoding Download PDFInfo
- Publication number
- WO2007082626A3 WO2007082626A3 PCT/EP2006/070101 EP2006070101W WO2007082626A3 WO 2007082626 A3 WO2007082626 A3 WO 2007082626A3 EP 2006070101 W EP2006070101 W EP 2006070101W WO 2007082626 A3 WO2007082626 A3 WO 2007082626A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- accumulator
- computed
- node update
- information
- likelihood values
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
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- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Error Detection And Correction (AREA)
Abstract
Methods and apparatuses are disclosed for decoding LDPC coded data, employing in iteration likelihood values in a memory, check node update steps and symbol node update steps. For accelerating convergence, before performing the check node update, symbol node update steps are performed in which updated likelihood values are used in matrix rows above and likelihood values from a previous iteration are used in matrix rows below. For efficiently decoding structured LDPC coded data, an accumulator is employed for each symbol node, new extrinsic information is computed using the accumulator and the memory, intrinsic information is computed by subtracting old extrinsic information from the accumulator, and a-posteriori information is computed by adding the new extrinsic information to the accumulator. Cyclic shifting is performed at the accumulator.
Applications Claiming Priority (10)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP06100463 | 2006-01-17 | ||
EP06100463.6 | 2006-01-17 | ||
EP06100831 | 2006-01-25 | ||
EP06100854.6 | 2006-01-25 | ||
EP06100831.4 | 2006-01-25 | ||
EP06100854 | 2006-01-25 | ||
EP06100982 | 2006-01-27 | ||
EP06100982.5 | 2006-01-27 | ||
EP06125438 | 2006-12-05 | ||
EP06125438.9 | 2006-12-05 |
Publications (2)
Publication Number | Publication Date |
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WO2007082626A2 WO2007082626A2 (en) | 2007-07-26 |
WO2007082626A3 true WO2007082626A3 (en) | 2008-06-05 |
Family
ID=38287972
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2006/070101 WO2007082626A2 (en) | 2006-01-17 | 2006-12-21 | Method and apparatus for error correction decoding |
Country Status (1)
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WO (1) | WO2007082626A2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8645810B2 (en) | 2011-07-31 | 2014-02-04 | Sandisk Technologies Inc. | Fast detection of convergence or divergence in iterative decoding |
CN104092468B (en) * | 2014-07-07 | 2017-02-08 | 西安电子科技大学 | LDPC linear programming decoding method based on acceleration alternating direction multiplier method |
US10862512B2 (en) | 2018-09-20 | 2020-12-08 | Western Digital Technologies, Inc. | Data driven ICAD graph generation |
US10735031B2 (en) | 2018-09-20 | 2020-08-04 | Western Digital Technologies, Inc. | Content aware decoding method and system |
US11528038B2 (en) | 2020-11-06 | 2022-12-13 | Western Digital Technologies, Inc. | Content aware decoding using shared data statistics |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1610466A1 (en) * | 2004-06-22 | 2005-12-28 | Infineon Technologies AG | LDPC decoder for decoding a low-density parity check (LDPC) codewords |
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2006
- 2006-12-21 WO PCT/EP2006/070101 patent/WO2007082626A2/en active Application Filing
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1610466A1 (en) * | 2004-06-22 | 2005-12-28 | Infineon Technologies AG | LDPC decoder for decoding a low-density parity check (LDPC) codewords |
Non-Patent Citations (3)
Title |
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"DIGITAL VIDEO BROADCASTING (DVB); SECOND GENERATION FRAMING STRUCTURE, CHANNEL CODING AND MODULATION SYSTEMS FOR BROADCASTING, INTERACTIVE SERVICES, NEWS GATHERING AND OTHER BROADBAND SATELLITE APPLICATIONS", ETSI STANDARDS, EUROPEAN TELECOMMUNICATIONS STANDARDS INSTITUTE, SOPHIA-ANTIPO, FR, no. V111, June 2004 (2004-06-01), pages 1 - 74, XP002311764, ISSN: 0000-0001 * |
ANDREW J BLANKSBY ET AL: "A 690-mW 1-Gb/s 1024-b, Rate-1/2 Low-Density Parity-Check Code Decoder", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 37, no. 3, March 2002 (2002-03-01), XP011061705, ISSN: 0018-9200 * |
KIENLE F ET AL: "A Synthesizable IP Core for DVB-S2 LDPC Code Decoding", DESIGN, AUTOMATION AND TEST IN EUROPE, 2005. PROCEEDINGS MUNICH, GERMANY 07-11 MARCH 2005, PISCATAWAY, NJ, USA,IEEE, 7 March 2005 (2005-03-07), pages 100 - 105, XP010780248, ISBN: 0-7695-2288-2 * |
Also Published As
Publication number | Publication date |
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WO2007082626A2 (en) | 2007-07-26 |
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