WO2007080718A1 - Pont, processeur de donnees, systeme de traitement informatique et procede de gestion d'adresses globales - Google Patents

Pont, processeur de donnees, systeme de traitement informatique et procede de gestion d'adresses globales Download PDF

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Publication number
WO2007080718A1
WO2007080718A1 PCT/JP2006/323947 JP2006323947W WO2007080718A1 WO 2007080718 A1 WO2007080718 A1 WO 2007080718A1 JP 2006323947 W JP2006323947 W JP 2006323947W WO 2007080718 A1 WO2007080718 A1 WO 2007080718A1
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WO
WIPO (PCT)
Prior art keywords
address
access request
request packet
processor
identification number
Prior art date
Application number
PCT/JP2006/323947
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English (en)
Japanese (ja)
Inventor
Takeshi Yamazaki
Hideyuki Saito
Yuji Takahashi
Hideki Mitsubayashi
Original Assignee
Sony Corporation
Sony Computer Entertainment Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corporation, Sony Computer Entertainment Inc. filed Critical Sony Corporation
Publication of WO2007080718A1 publication Critical patent/WO2007080718A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L61/00—Network arrangements, protocols or services for addressing or naming
    • H04L61/09—Mapping addresses
    • H04L61/25—Mapping addresses of the same type
    • H04L61/2503—Translation of Internet protocol [IP] addresses
    • H04L61/2514—Translation of Internet protocol [IP] addresses between local and global IP addresses

Definitions

  • the present invention relates to an access technology between nodes on a computer network.
  • nodes that communicate with each other cannot see each other's resources such as memory and IO devices, and have no resource transparency.
  • processors in a computer network such as a multiprocessor system in which a plurality of processors are connected, there is no resource transparency between the processors, and therefore, a shared memory that can be accessed by each processor is provided. It is conceivable that data is transferred between processors via a PC. In this case, for example, when processor A wants to pass data to processor B, direct delivery is not possible. Processor A copies the data to shared memory and processor B reads the data from the shared memory and copies it. Processing is required, and overhead problems may occur as well.
  • the present invention has been made in view of the above circumstances, and an object thereof is to provide resource transparency between nodes on a computer network.
  • One embodiment of the present invention is a bridge.
  • This bridge relays the input / output node of a processor unit to the input / output node of a switching device to which a plurality of processor units are interconnected, and includes an upstream port, a conversion unit, and a downstream port. .
  • the upstream port is assumed to be one of the target nodes of the plurality of processor units from the processor unit on the premise of a global address space shared among the plurality of processor units to which the effective addresses of the processor units are mapped.
  • An access request packet specifying the effective address of is received.
  • the effective address is an address indicating a predetermined position in the effective address space.
  • the effective address space is a combination of a part of the memory space that is partially cut off from each of the storage means including the main memory and the like scattered in each processor unit.
  • One effective memory space corresponds to one processor unit. In other words, there are as many effective memory spaces as there are processor units, and each processor unit uses its own effective memory space as work memory. By optimizing the internal structure of the effective memory space, the corresponding processor unit can operate at maximum performance.
  • the conversion unit converts the effective address of the target node into a global address by adding the node identification number necessary for switching of the target node to the upstream port and the effective address of the target node.
  • the downstream port outputs a conversion unit and an access request packet in which a glow address is specified to the switching device.
  • the conversion unit accesses an access with a global address specified. You may want to store the identification number in the request packet.
  • the conversion unit receives the access request packet.
  • the upstream port may pass the application identification number acquired from the access request packet to the processor unit together with the effective address of the processor unit specified in the access request packet.
  • Another aspect of the present invention is an information processing apparatus.
  • a processor unit and an input / output bus of the processor unit are connected to each other by a plurality of processor units interconnected.
  • the bridge can be a bridge as described above.
  • the information processing system includes a plurality of processor units, a switching device that interconnects the plurality of processor units, and a bridge that relays the input / output bus of each processor unit to the input / output bus of the switching device.
  • This bridge can also be a bridge of the above-described embodiment.
  • the present invention can provide resource transparency between nodes on a computer network.
  • FIG. 1 is a diagram showing an information processing system used for explaining the outline of the present invention.
  • FIG. 2 is a diagram showing a configuration of nodes in the information processing system shown in FIG.
  • FIG. 3 is a diagram (part 1) illustrating the concept of a global address space.
  • FIG. 4 is a diagram showing a configuration of a bridge in the node shown in FIG.
  • FIG. 5 is a diagram showing a global address format corresponding to the global address space shown in FIG. 3.
  • FIG. 6 is a diagram (part 2) illustrating the concept of the global address space.
  • FIG. 7 is a diagram showing an example of a global address format corresponding to the global address space shown in FIG.
  • FIG. 8 is a diagram showing a configuration of an information processing system according to an embodiment of the present invention.
  • FIG. 9 is a diagram showing a configuration example of a node in the information processing system shown in FIG.
  • FIG. 10 is a diagram showing a configuration of a bridge in the node shown in FIG.
  • FIG. 11 is a diagram illustrating an example of a conversion table used when converting an effective address to a physical address and a conversion result.
  • This information processing system has a plurality of nodes 40 as an example here, and these nodes are connected by a switching device (hereinafter simply referred to as a switch) 50.
  • a switching device hereinafter simply referred to as a switch 50.
  • FIG. 2 shows the configuration of the node 40.
  • the node 40 includes a processor unit 30 and a bridge 20 that relays an input / output bus (not shown) of the processor unit 30 to an input / output bus (not shown) of the switch 50.
  • the processor unit 30 may be a single processor or may be composed of a plurality of processors.
  • FIG. 3 illustrates the concept of the global address space.
  • the effective address power of each processor unit 30 is mapped so as to be associated with the node to which this processor unit 30 belongs.
  • This global address space is shared among the processor units 30, and the address in the space is hereinafter referred to as a global address.
  • the processor unit 30 of the source node When accessing the target node, the processor unit 30 of the source node issues an access request packet specifying the effective address of the target node and outputs it to the bridge 20.
  • This access request packet is issued by, for example, DMA (direct 'memory' access). B) using architecture.
  • FIG. 4 shows the configuration of the bridge 20.
  • the bridge 20 includes an upstream port 22 that transmits / receives data to / from the processor unit 30 via the input / output bus of the processor unit 30, and a downstream port 26 that transmits data to / from the switch 50 via the input / output bus of the conversion unit 24 and switch 50. Is provided.
  • the upstream port 22 receives the access request packet issued by the processor unit 30, and the conversion unit 24 uses the effective address of the target node as a node identification number (hereinafter referred to as a node) of the target node for switching. By adding ID), the effective address of the target node is converted to a global address. Then, the downstream port 26 outputs an access request packet specifying this global address to the switch 50.
  • a node identification number hereinafter referred to as a node
  • the node ID can indicate the physical location of the node 40 in the network. For example, the number of the connection port to which the node is connected in the switch 50 can be used.
  • FIG. 5 shows a format of a global address. As shown in the figure, the global address consists of the node ID and effective address.
  • the downstream port 26 of the bridge 20 outputs an access request packet specifying such a global address to the switch 50, and the switch 50 reads the node ID included in the global address of the received access request packet. Then, the access request packet is transferred to the node 40 connected to the connection port indicated by the node ID.
  • the bridge 20 of the node 40 serving as the target node receives the access request packet through the downstream port 26.
  • the upstream port 22 outputs the effective address designated by the access request packet to the processor unit 30.
  • the conversion unit 24 may read out the effective address of the global address and pass it to the upstream port 22, and when the switch 50 transfers the access packet, only the effective address included in the global address is transmitted. It may be outputted to the bridge 20 so that the intervention of the conversion unit 24 is not required.
  • the access request packet may be directly passed to the processor unit 30 and the processor unit 30 may read the effective address.
  • the processor unit 30 converts the effective address into a physical address.
  • an area is allocated for each active application in a node that executes an application, specifically, a memory in a processor unit included in the node.
  • the technique proposed by the present inventor makes it easy to access an area allocated for this application between the same applications operating on different nodes in a distributed application system.
  • an application identification number (hereinafter referred to as application ID or APID) is introduced, and the global address space shown in FIG. 3 is logically divided using this application ID.
  • the application ID is assigned to each active application and uniquely identifies the application in the entire system. That is, the same application running on different nodes will have the same application ID.
  • FIG. 6 shows the concept of the global address space in this case.
  • the effective address on the right is the effective address space corresponding to each node and the application running on that node.
  • the central address space is a set of effective address spaces corresponding to the same application scattered in the information processing system.
  • the address space on the left is a set of address spaces corresponding to each application in the information processing system.
  • the processor unit 30 of the source node When accessing the target node, the processor unit 30 of the source node issues an access request packet specifying the effective address of the target node and outputs it to the bridge 20.
  • the conversion unit 24 of the bridge 20 adds the APID and the target node to the effective address of the target node.
  • the effective address of the target node is converted to a global address, this global address is specified via the downstream port, and the node of the source node that is the request source of the access
  • the access request packet with the ID added is output to switch 50.
  • FIG. 7 shows an example of a global address format. As shown in the figure, this global address is composed of an application ID (APID), a node ID, and an effective address.
  • API application ID
  • node ID node ID
  • effective address an effective address
  • the format of the global address is not limited to the example shown in FIG.
  • the A PID is included in the access request packet and can be read by the bridge 20 of the target node.
  • the format shown in Fig. 5 is used as the format of the global address, and the APID is stored in the access request packet.
  • the bridge 20 of the node 40 serving as the target node Upon receiving the access request packet, the bridge 20 of the node 40 serving as the target node reads the APID from the access request packet, and, along with this APID, the effective address specified by the access request packet as the node Pass to 40.
  • the processor unit 30 converts the effective address into a physical address of an area provided for the application corresponding to the access request source node ID or APID.
  • the processor unit may use an address conversion table for conversion when converting an effective address into a physical address.
  • a permission identification number indicating access permission Z prohibition to the physical address space that is the access request destination is added to this address conversion table.
  • the permission identification number is, for example, the node ID of the access request source node that permits access for each physical address space, or the access request source application.
  • APID which is the identification information of the client.
  • the processor unit converts the effective address to the physical address by referring to this conversion table, it corresponds to the effective address in the conversion request table and the access request node ID or APID to which the bridge power is also passed. Access to this effective address can be determined based on whether or not it matches the authorization identification number assigned to it.
  • each effective memory space is optimized so that the application operates across the nodes and the processor unit or the application operates at the maximum performance in each node.
  • the mutual access between the nodes in the effective memory space can be facilitated, and the area power allocated to a given application can be prevented from being accessed.
  • the configuration of the bridge can be simplified. Furthermore, the conversion table can be adjusted independently of the bridge on the processor unit side. Furthermore, even if nodes of different types of IO devices and memory sizes are mixed, access between nodes can be made possible by the bridge with the same configuration.
  • FIG. 8 shows a configuration of an information processing system according to an embodiment related to the present invention.
  • This information processing system includes a plurality of nodes 100 and a switch 80 that connects these nodes to form a network.
  • the node 100 is connected to the switch 80 by a connection bus (not shown), and this connection bus is, for example, a PCI Express (registered trademark) bus.
  • PCI Express registered trademark
  • FIG. 9 shows a configuration example of the node 100 in the information processing system shown in FIG.
  • the node 100 includes a bridge 110, a multi-core processor 120, and a main memory 180.
  • the multi-core processor 120 is formed in one chip, and includes a main processing unit PPE (Power Processing Element) 140, a plurality of, in the illustrated example, eight sub-processing units SPE (Synergistic Processing Element) 130, IO Interface (hereinafter referred to as IOIF) 160 and memory controller 170, which are connected by ring bus 150 Is done.
  • PPE Power Processing Element
  • SPE Synnergistic Processing Element
  • IOIF IO Interface
  • the main memory 180 is a shared memory of the processing units of the multi-core processor 120, and is connected to the memory controller 170.
  • the memory controller 170 mediates access to the main memory 180 by the PPE 140 and each SPE 130.
  • the main memory 180 is a multi-core processor 1
  • the force provided outside the 20 may be provided so as to be included in the multi-core processor 120.
  • the IOIF 160 is connected to the bridge 110 via an IOIF bus (not shown), and allows access between the nodes 100 in cooperation with the bridge 110.
  • the IOIF 160 includes an IO controller 1 64.
  • the SPE 130 includes a core 132, a low-power memory 134, and a memory flow controller (hereinafter referred to as MFC) 136.
  • the MFC 136 includes a DMAC (Direct Memory Access Controller) 138.
  • DMAC Direct Memory Access Controller
  • the local memory 134 is not a conventional hardware cache memory.
  • the PPE 140 includes a core 142, an L1 cache 144, an L2 cache 145, and an MFC 146.
  • the MFC 146 includes a DMAC 148.
  • the operating system (hereinafter also referred to as OS) of the multi-core processor 120 operates in the PPE 140, and a program operating in each SPE 130 is determined based on the basic processing of the OS.
  • the program that operates on the SPE 130 may be a program that forms part of the OS functions (for example, a device driver or a part of a system program).
  • the instruction set architectures of PPE140 and SPE130 have different instruction sets.
  • the OS may operate on each SPE 130. That is, an OS using a part of the core 132 and the local memory 134 included in each SPE 130 operates.
  • the OS of each SPE130 works together to form one OS as a whole.
  • the OS running on each SPE130 can communicate data with other SPE130s from itself by executing instructions from PPE140 when executing any application. It is possible to check and acquire the tasks that are included in the application and wait for execution by performing communication or accessing the main memory 180, and execute them if they can be executed.
  • the OS runs on a PPE140 and the OS decides a program that runs on each SPE130, the force that may have caused any SPE130 to not run is due to the OS running on each SPE130. All SPE130s can continue to run for application execution.
  • the information processing system shown in FIG. 8 is a distributed application system in which the same application can operate on a plurality of multi-core processors 120. In this system, the global address space shown in Fig. 6 is used.
  • FIG. 10 shows the configuration of the bridge 110.
  • the bridge 110 includes a first input / output unit 112, a bridge controller 114, and a second input / output unit 118.
  • the bridge controller 114 includes a register group 116.
  • the first input / output unit 112 and the second input / output unit 118 are the same as the upstream port 22 and the downstream port 26 of the bridge 20 shown in FIG. Omitted.
  • the bridge controller 114 converts the effective address designated by the access request packet issued by the multi-core processor 120 into a global address. Also, when the node to which it belongs is accessed as the target node, the global address strength APID included in the access request packet received by the second input / output unit 118 is read, and the access request packet is specified along with this APID. The effective address is passed to the multi-core processor 120.
  • the bridge controller 114 there is an IO address space for converting the effective address in each node 100 and the global address in the entire information processing system.
  • the IO address space is divided into one or more segments, and each segment is further divided into one or more pages.
  • the bridge controller 114 includes a register for performing conversion for each page, and a set of these registers is a register group 116.
  • the conversion register provided in the bridge controller 114 includes the node ID of the access request source node that is permitted to access the page or the APID that is identification information of the access request source application, and the main mapped in association with the page.
  • a physical address or the like is included for each page.
  • the multi-core processor 120 included in the node 100 accesses another node as a target node. In accessing, the multi-core processor 120 issues an access request packet to the bridge 110.
  • This access request packet includes the effective address (in this embodiment, an offset in the IO address space of the target node) of the access request destination application in the target node.
  • This access request packet is issued by the DMAC power of any processing unit included in the multi-core processor 120.
  • the bridge controller 114 of the bridge 110 converts the effective address into a global address.
  • the format shown in Fig. 7 is used for the global address.
  • the global address obtained by the bridge controller 114 is composed of the APID of the application requesting access, the node ID of the target node, and the effective address power at the target node.
  • the node ID of the source node that is the access request source is added to the access request packet.
  • Bridge 110 reads the node ID included in the access request packet specifying this global address, and forwards the access request packet to the target node indicated by this node ID.
  • the bridge controller 114 reads out the APID included in the access request packet. Then, the effective address included in the access request packet is converted into an IO address.
  • the bridge 110 transmits the IO address thus obtained to the IOIF 160 of the multi-core processor 120 together with the APID.
  • the IO controller 164 of the IOIF 160 converts the IO address into a physical address in the main memory 180.
  • Figure 11 shows an example of the conversion table used for this conversion and the result of the conversion.
  • the main memory 180 is divided into segments, and each segment is also divided into pages of a predetermined page size.
  • page size is ⁇
  • the conversion table maps the physical address (space) for each page included in the segment, and indicates access permission Z prohibition by the permission identification number IOID.
  • IOID indicates the node ID of the access request source node that is permitted to access the corresponding physical address (space), or APID that is the identification information of the access request source application.
  • the switch 80 may be configured to use a switch that interconnects buses of standards other than the force PCI that interconnected PCI buses.
  • the present invention can be applied to the field of computer network systems.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

La présente invention vise à garantir la transparence des ressources entre les nœuds d'un réseau informatique. Dans un système de traitement informatique composé d'une pluralité de processeurs connectés entre eux par un dispositif de commutation, un espace d'adresses globales comprenant une carte des adresses réelles des processeurs et partagé entre les processeurs est créé. Un pont destiné à assurer le relais entre le bus d'entrée/sortie de chaque processeur et le bus d'entrée/sortie du dispositif de commutation reçoit du processeur un paquet de demande d'accès comprenant l'adresse réelle d'un nœud cible, il convertit l'adresse réelle du nœud cible en une adresse globale en ajoutant à l'adresse réelle le numéro d'identification du nœud cible nécessaire pour la commutation, puis il envoie au dispositif de commutation le paquet de demande d'accès comportant l'adresse globale.
PCT/JP2006/323947 2006-01-16 2006-11-30 Pont, processeur de donnees, systeme de traitement informatique et procede de gestion d'adresses globales WO2007080718A1 (fr)

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JP2006-008004 2006-01-16
JP2006008004A JP2009110032A (ja) 2006-01-16 2006-01-16 ブリッジ、情報処理装置、情報処理システムおよびグローバルアドレス管理方法

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Cited By (2)

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JP2010152892A (ja) * 2008-12-10 2010-07-08 Nvidia Corp ハードウェアデバイスをヘテロジニアス処理ユニット間でバインドし移行するためのチップセットサポート
JP2010170237A (ja) * 2009-01-21 2010-08-05 Sony Corp アクセスキー生成装置および情報処理装置

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JP2014004694A (ja) * 2012-06-21 2014-01-16 Seiko Epson Corp 液体吐出装置
JP7181447B2 (ja) 2018-03-30 2022-12-01 株式会社ソシオネクスト 情報処理システム、情報処理方法及び半導体装置
JP6635209B2 (ja) * 2018-04-18 2020-01-22 富士通クライアントコンピューティング株式会社 情報処理システム
WO2019203331A1 (fr) * 2018-04-18 2019-10-24 富士通クライアントコンピューティング株式会社 Dispositif répéteur et système de traitement d'informations
JP6922879B2 (ja) * 2018-11-30 2021-08-18 日本電気株式会社 通信装置、情報処理システム、および通信方法
GB2586957A (en) * 2019-04-18 2021-03-17 Fujitsu Client Computing Ltd Repeating device and information processing system

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JPH0830567A (ja) * 1994-07-14 1996-02-02 Hitachi Ltd 並列計算機のプロセッサ間相互アクセス方法
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JPH05181751A (ja) * 1991-12-26 1993-07-23 Fujitsu Ltd 分散アドレス変換方式
JPH0830567A (ja) * 1994-07-14 1996-02-02 Hitachi Ltd 並列計算機のプロセッサ間相互アクセス方法
JPH08272754A (ja) * 1995-03-30 1996-10-18 Nec Corp マルチプロセッサシステム
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JP2010152892A (ja) * 2008-12-10 2010-07-08 Nvidia Corp ハードウェアデバイスをヘテロジニアス処理ユニット間でバインドし移行するためのチップセットサポート
JP2010170237A (ja) * 2009-01-21 2010-08-05 Sony Corp アクセスキー生成装置および情報処理装置

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