WO2007077801A1

WO2007077801A1 - Memory system for reducing current consumption and method thereof

Info

Publication number: WO2007077801A1
Application number: PCT/JP2006/325820
Authority: WO
Inventors: Toshio Sunaga
Original assignee: International Business Machines Corporation
Priority date: 2005-12-28
Filing date: 2006-12-25
Publication date: 2007-07-12
Also published as: JP5208519B2; JPWO2007077801A1; KR101027178B1; US7859935B2; CN101331552B; KR20080080562A; EP1968071A1; CN101331552A; EP1968071A4; EP1968071B1; US20090231941A1

Abstract

[PROBLEMS] To provide a memory system capable of reducing a large current consumption during an active state and a stand-by state by increasing the efficiency of a voltage generation circuit in a DRAM or the like having a charge pump circuit or the like and a method for reducing the current. [MEANS FOR SOLVING PROBLEMS] A memory system includes a high voltage supply boost circuit for supplying pre-charged electric charge to an access control circuit in response to an access start request for a memory cell array and driving the access control circuit from a low voltage for the memory access to a high voltage. Moreover, the memory system further includes a low voltage supply boost circuit for absorbing an excessive electric charge generated when the access control circuit is switched from the high voltage to the low voltage in response to the access end request to the memory cell array.

Description

Specification

Memory system for current consumption reduction key and method thereof

Technical field

[0001] The present invention relates generally to memory 'systems. More specifically, the present invention relates to a circuit for efficiently generating high and low levels of voltage in order to reduce current consumption during operation in a memory system and a voltage generation method therefor.

Background art

In a conventional memory such as a DRAM (Dynamic Random Access Memory) using a normal n-channel metal oxide semiconductor (FET) FET (Field Effect Transistor) as a memory cell cell transistor, The power consumption of the word line circuit that drives each word line connected to the gate of the memory 'cell of cell' transistor has been a problem.

That is, when a high level value is written to the memory cell of such a memory, a high level voltage is applied to the bit line (data line) connected to the source of the memory cell. Therefore, the high level voltage (high voltage, Vpp) of the word line connected to the gate of the memory cell is at least higher than the high level voltage of the bit line by the threshold voltage (Vt) of the cell transistor. There must be. Further, 'in the state that holds the data in the cell, the cell' and the voltage of the word line to a low level memory drain of the transistor - the leakage current between the source f (Femto, femto: 1x10- ¹⁵⁾ A (ampere) In order to keep it below the order of V t, V t must be quite high. In addition, when the bit line is at high level, the source follower operation (grounded drain) is performed with the base biased by the voltage of Vt, so the full high level of this bit line is actually increased at high speed. Therefore, the word line voltage (cell voltage of the cell transistor) sufficient to write to the memory cell is considerably higher than 3.0V. Due to the necessity of lowering the word line voltage due to the recent miniaturization of DRAM technology, the high level voltage (Vpp) of the word line has increased from 2.6V to 2.8V. Don't be. However, if Vt is lowered, the leakage current of the memory cell will increase. To prevent this, the low level voltage (low voltage, Vnn) of the word line is 0. A negative voltage of 2V to 0.5V is used. These word line high level voltage of 2.6V to 2.8V and negative line voltage of 0.2V to 10.5V are respectively charged by the charge pump circuits (referred to as Vpp pump and Vnn pump, respectively) inside the DRAM chip. Generated from internal voltage of DRAM. In this way, the negative voltage is used for the low level voltage of the word line, and the high level voltage has decreased from 2.6V to 2.8V. The internal voltage that generates it has also decreased to about 1.6V. The ratio remains large, and the current consumption is large due to the conversion loss caused by the inefficiency of the charge pump circuit described below.

[0004] According to S 丄 Cho et al., “IEEE Journal of Solid State Circuits J, pp.1726— 1729, vol.38, no. L 0, Oct. 2003, the efficiency of charge pump circuits is generally poor. In particular, the efficiency of the Vpp pump for producing high voltage is only about 40%, and Y. Nakagome et al., ΓΙΕΕΕ Journal of Solid State Circuits J, pp.465—472, vol.26, no.4, Apr. According to 1991, the charge 'pump circuit's inefficiency is due to the large current flowing in the control and drive circuits because it uses a single type of transistor to prevent reverse biasing of the junction. In other words, all Vpp pumps consist of n-channel MOS FETs, and a higher voltage must be applied to the gate to control a high voltage, and a capacitor pump is required to create this voltage, for example, power is supplied as Vpp. To obtain twice the voltage, up to three times the power It must made control circuit, and this is a cause of increasing the current consumption.

[0005] Since a current of a value obtained by multiplying the current actually used in the memory circuit (word line circuit) by the reciprocal of the efficiency value expressed in terms of a percentage flows, for example, at an efficiency of 0%, 2.5 times the current used in the actual word line circuit is consumed in the memory chip. In addition to the increasing number of word lines that need to be activated at the same time as DRAM memory capacity has increased in recent years, SDRAM (Synchronous Dynamic Random Access Memory) is generally used during refresh. Since all banks are refreshed at the same time, it is necessary to activate word lines that are several times the number of banks (usually 4 banks) compared to normal access. In 512Mbit SDRAM, this alone may be about 20mA. A major obstacle to reducing the normal access current and refresh current It is becoming harmful.

[0006] On the other hand, as a method not using the charge pump circuit that generates Vpp that is higher than the internal voltage as described above, there has been a conventional method using a boost circuit. The boost circuit is a circuit that boosts the voltage with a capacitor and a switch using n-channel MOS FET. When DRAM was made only with n-type MOS instead of CMOS (Complementary Metal Oxide Semiconductor) It is a well-known configuration that has been used since (until the mid-1980s before roughly 1Mbit DRAM).

[0007] Japanese Patent Application Laid-Open No. 6-139776 discloses an idea relating to the high speed operation of the boost circuit. That is, the power boost circuit that has various parasitic addition capacities around the mouth address 'Row Address Decoder' must boost the nodes that connect these capacities. It takes time to boost, and high-speed operation cannot be performed. In order to solve this, the voltage level rise for these nodes is raised from the power source to a predetermined voltage level through a switch by a separate route without relying on the boost circuit, and then the predetermined voltage level force is also increased. By increasing the voltage up to the word line voltage level using the boost circuit, the total time for boosting the voltage level for the node is shortened.

[0008] However, this method does not provide a solution to the reduction in current consumption, which can only solve the speed-up in the step-up of the voltage level. In addition, as described above, a configuration in which a voltage higher than the power supply voltage is always generated in a DC manner using a charge pump circuit and supplied to the word line is generally used. Thus, no method has been devised to achieve high speed when supplying a high voltage and low current consumption during supply.

Patent Document 1: S 丄 Cho et al., IEEE Journal of Solid State Circuits, pp.1726— 1729, vo 1.38, no.10, Oct. 2003.

Non-Patent Document 2: Y. Nakagome et al., EEE Journal of Solid State Circuits, pp.465-472, vol.26, no.4, Apr. 1991.

Patent Document 1: Japanese Patent Laid-Open No. 6-139776

Disclosure of the invention Problems to be solved by the invention

Accordingly, the present invention provides a memory such as a DRAM having a voltage generation circuit including a charge pump circuit for generating high-level and low-level voltages to be supplied to a word line that drives the gate of the memory cell. By increasing the efficiency of the voltage generation circuit, the large current consumption during both active and standby caused by the inherent inefficiency of the voltage generation circuit can be reduced. In addition, the main object of the present invention is to provide a memory system that can also achieve high-speed voltage supply and a method for reducing the current.

[0010] This object is achieved by a combination of features described in the independent claims. In addition, the dependent claims define further advantageous embodiments and specific examples of the present invention.

Means for solving the problem

In order to solve the above-described problem, in the first embodiment of the present invention, a memory 'cell' array and an access start request or an end request for the memory 'cell' array are received and the memory 'cell' array An access control circuit that controls access to the access control circuit, and a charge that is charged in advance in response to the access start request is supplied to the access control circuit to change the access control circuit from a low voltage for memory access to a high voltage. A memory'system is provided that includes a high voltage supply boost circuit for driving. Also provided is a memory system further comprising a low voltage supply boost circuit for absorbing excessive charges when the access control circuit is switched from the high voltage to the low voltage in response to the access end request.

[0012] In the second embodiment of the present invention, an access control circuit that receives an access start request or an end request for a memory 'cell' array in a memory 'system and controls access to the memory' cell array is provided. On the other hand, a method of supplying a voltage by a voltage supply boost circuit for driving by a high voltage and a low voltage for memory access, and charging the voltage supply boost circuit in response to the access start request A first charging step; a first discharging step of discharging the charged electric charge after completion of the charging and supplying the electric charge to the access control circuit; and a residual electric charge after the discharging. And a first initialization step for initializing for recharging while remaining in the voltage supply boost circuit. A second charging step for charging the voltage supply boost circuit in response to the access end request; and a second charging step for discharging the charged charge after the charging is completed. There is provided a method further comprising: a discharge step; and a second initial phase step for initializing for recharging while the residual charge after the discharge is held in the voltage supply boost circuit.

[0013] Further, in the third aspect of the present invention, there is provided an apparatus for supplying a voltage to a target system that requires driving of an internal circuit by at least binary voltages of a high voltage and a low voltage. In response to a request to start driving with the high voltage to the target system, a charge charged in advance is supplied to the target system to drive the internal circuit in the target system to the low voltage force to the high voltage. And a high voltage supply boost circuit of the target system, and absorbs an excessive charge when the internal circuit of the target system is switched from the high voltage to the low voltage in response to a request for termination of driving by the high voltage to the target system. Low voltage supply boost circuit for and

And a voltage supply method having steps corresponding thereto.

[0014] It should be noted that the summary of the invention described above is not a list of all the features necessary for the present invention, and that the present invention can also be applied to combinations that are part of the features of the plurality of inventions. Needless to say.

The invention's effect

[0015] According to the present invention, it is possible to reduce current consumption during active and standby of a memory system such as DRAM.

BEST MODE FOR CARRYING OUT THE INVENTION

[0016] The best mode for carrying out the present invention (hereinafter referred to as an embodiment) will be described in detail below with reference to the accompanying drawings. However, these embodiments limit the invention according to the scope of the claims. In addition, not all combinations of features described in the embodiments are necessarily essential for the solution of the invention.

[0017] As a premise for explaining the embodiment of the present invention, the configuration and operation of a memory such as DRAM in the prior art will be described in detail first. Figure 1 shows the structure of a conventional DRAM chip The figure is shown. There is a row address decoder (RDEC) 100 in the center, and a memory cell array (Memory Cell Array) 104, 106 on both sides across this. Memory 'cell' arrays 104 and 106 are memory 'cells 108 to 111 etc., which are storage units of the relevant DRAM, arranged vertically and horizontally, and for memory' cells 108 and 110 etc. arranged vertically. The same single bit line (also called data line) 120 is connected to the FET source 112, 114, etc. constituting each memory 'cell, and for the memory cells 108, 109, etc. arranged in the horizontal direction. The same word line 124 is connected to the FET gates 116, 117, etc. that make up each memory cell, and this bit line and word line must be driven to a high or low level at an appropriate timing. Thus, a high or low value can be stored in any memory cell in the memory cell array 104, 106, or a value stored in the arbitrary memory cell can be read. The “address” decoder 100 is a block that decodes the “address” decoder (not shown) input thereto and supplies a word line to the memory “cell” arrays 104 and 106.

In the address decoder 100, the word line circuit 102, which is a circuit block for generating the word lines 124 to 126 and driving them high or low, is provided for each memory cell. Exists. FIG. 2 shows a detailed circuit example of the word line circuit 102. In this example, the word line circuit 102 in the “address” decoder 100 that inputs a 10-bit “address” address and generates a total of 1024 word lines is shown. That is, 3 bits of the 10-bit mouth address are decoded to generate 8 source drive signals (SDV) 200 and 8 side line reset signals (WLr) 204. 'Decode the remaining 7 bits of the address to generate 128 decoder output signals (RDout) 202. One of the eight source drive signals (SDV) 200 and one of the eight word line reset signals (WLr) 204, corresponding to the one source drive signal 1024 word lines corresponding to 1024 (= 8x128) different combinations when selecting and inputting each of the pair that has power and 128 decoder outputs (RDout) 202 Driver circuits 220 and the like exist, and 1024 word lines (WL) 230 and the like are driven by them. That is, one source 'drive signal 206 is input to all 128 word line driver circuits to which each of 128 decoder output signals 202 is input, and one decoder output signal 206 is also input. The number 208 is input to all eight word line driver circuits to which each of the eight source drive signals 200 is input.

[0019] Looking at one word line driver circuit 220, if one source drive signal 206 is selected by decoding 3 bits of a 10-bit address, this signal will be The high side power supply voltage (Vpp) of 230 causes the high level (Vpp), and the word line reset signal 210 becomes low level (Vnn) due to the low side power supply voltage (Vnn) of the driver 234. At this time, if the decoder output signal 208 is also selected by decoding the remaining 7 bits, this signal becomes low level (Vnn) by the low side power supply voltage (Vnn) of the driver 232. Therefore, the source of the p-channel MOS FET 222 in the word line driver circuit 220 to which the source drive signal 206 is connected is high level (Vpp) and its gate is low level (Vnn). Turns on, and the drain voltage level of p-channel MOS FET 222 also goes high (Vpp). At the same time, since the word line reset signal 210 for the word line driver circuit 220 is low level (Vnn), the n-channel MOS FET 224 is turned off, and the word line 230 is driven to high level (Vpp) and connected to the word line 230. Turn on the gates of multiple cells' transistors. On the other hand, when the source drive signal 206 is not selected as a result of decoding the bit address, the word line reset signal 210 is set to the high level (Vdd) by the high side power supply voltage (Vdd) of the driver 234, and the n channel Since the MOS FET 224 is turned on, the word line 230 is driven to a low level (Vnn), and the gate of the cell transistor connected to the word line 230 remains off.

[0020] In this circuit, the power supply voltage (Vpp) for the drivers 230, 232 and the low-side power supply voltage (Vnn) for the drivers 230, 232, 234 are respectively supplied from the Vpp pump 130 and the Vnn pump 132 of FIG. The Vpp pump 130 and Vnn pump 132 are located on the outer periphery of the memory cell array 104, 106 and are connected to the Vpp and Vnn supply lines in the address decoder 100 through the metal wiring 140, 142. Each connected

Here, the current consumption in the word line circuit 102 will be examined. In the word line circuit 102, the high-side power supply voltage is Vpp and the low-side power supply voltage is Vnn. Therefore, the current (Iw) consumed in the memory cell access is Vpp pump as shown in Figure 1. 130 to Vnn pump Flows to 132. Since the Vpp pump 130 and the Vnn pump 132 also usually generate the internal power (Vdd) force of the memory chip, this current Iw will eventually be the current of the internal power supply (Vdd). If the efficiency expressed as a percentage of the Vpp pump 130 and Vnn pump 132 is Evp and Ενη, respectively, the reciprocal of them is multiplied by Iw, and the sum is obtained.

Iw (l / Evp + 1 / Evn) [Formula 1]

Current flows to the Vdd power supply ground, which is the total current consumed by the word line circuit 102 of the memory chip. Since both Evp and Ενη are usually 0.5 or less, their reciprocal is 2 or more, and this current consumption is actually several times the current Iw required for the word line circuit 102.

[0022] Generally, the Vpp pump 130 and the Vnn pump 132 are placed at the periphery of the memory chip, but the word line circuit 102 that is actually operated with these powers supplied is the central address of the memory chip. The resistance of the wiring is quite high. Figure 1 shows this wiring resistance. To ensure sufficient word line high and low levels in actual operation, the pump uses a higher voltage in consideration of the decrease in wiring resistance. This must cause extra current consumption.

In order to reduce the large current consumption in the word line circuit 102 of the prior art, the present invention first focuses on the operation mode of the circuit supplied by the Vpp pump 130 and the Vnn pump 132. In general, Vpp pump 130 and Vnn pump 132 are only for word line circuits, and are not used at all in other circuits. The purpose of both pumps is to raise the voltage level of the word line associated with the memory cell to Vpp when accessing the memory cell, and then back to V nn. This is because of the two actions of keeping Vnn. In the prior art, the pump controls the voltage with a feedback circuit in the same way as a regulator. Therefore, when Vpp is accessed and current is consumed in Vpp, the voltage level decreases, and when the voltage drops below the preset level, the pump control circuit starts to supply charges with the capacitor, and the current is repeated several times. It tries to return the voltage level that has been consumed down to the original level. When the access is completed, the current is no longer used, so the voltage level rises. When this level also exceeds the preset level, the control circuit stops the charge supply by the capacitor. Capacitor pumping The work is a relatively slow cycle time of once every 25-30 ns. In this way, the Vpp level is controlled to the desired DC level with a ripple going back and forth between two preset levels. This is a typical negative feedback control if it is corrected for the resulting result.

However, in the actual word line circuit 102, for external access and refresh, a request (command) for starting access is issued and the word line is driven (ie, the access is actually started). At least 10 ns is delayed until the time when a large amount of current is required to supply Vpp can be foreseen. The Vim supply requires a large current when the access is completed and the voltage level of the word line returns to Vnn, which is also a very predictable timing. Therefore, with regard to the supply of Vpp and Vim, as in the prior art, the method of dealing with the result that occurred, i.e., when the voltage level dropped because of the flow of current V, the V The timing of the current flow is divided rather than taking the action of stopping the pump in response to another result that the voltage level rises because the voltage is returned and the current stops flowing. By supplying the necessary current at that time, if the voltage level drops in the first place, no results will occur! / If the voltage level increases afterwards, there will be no other results.

In the embodiment of the present invention, a circuit configuration based on the above-described principle is proposed. That is, according to the embodiment of the present invention, it is necessary to hold the voltage level of the word line 230 at Vnn when there is no access to the memory cell, so that the Vpp pump 130 and The Vnn pump 132 itself can be used as is, and the pump control circuit can be operated by adding a circuit to efficiently supply the required amount of current locally at the required timing. Since the level fluctuation is not sensed, and as a result, the efficiency is low and the pump is hardly operated, the operating current of the word line circuit 102 when accessed is greatly reduced.

[0026] The above-described circuit for supplying the necessary current at the necessary timing when access is generated generates a high voltage (ie, Vpp) or a negative voltage (ie, Vnn) from the internal voltage of the memory chip. In this case, the current must be supplied, and a boost method using a capacitor is used. [0027] First, the principle of this local 'boost circuit will be described. First, the principle of charge transfer when a high level voltage is supplied to the word line will be described. Figure 3 shows the principle of charge transfer by a local boost circuit. This circuit also consists of a boost capacitor 302 (capacitance: Cb) and the switching switches SW1 and SW2 that connect both electrodes to various voltage levels. The high-side power supply voltage electrode of the word line circuit 102 that uses the voltage generated here is ERws308, and the parasitic capacitance 310 (capacitance: Cw) related to the current flowing through the word line circuit 102 is ERws308. Exists. As the parasitic capacitance 310, in addition to the capacitance of the previously connected word line, various wiring capacitances, node junction capacitances, and the like are conceivable. ERsup312 is an electrode for charging the boost capacitor 302 (supply voltage level: Vsup), and is usually the internal voltage (Vdd) of the chip. ERpul 314 is an electrode (supply voltage level: Vpul) for lifting the low potential side electrode of the boost capacitor 302. First, as shown in FIG. 3 (a), SW1 is connected to the electrode ERsup side and SW2 is connected to the ground side to charge the boost capacitor 302. The voltage level at the electrode ERws308 of the word line circuit 102 is low and is set to 0 V for simplicity. Accordingly, the boost'capacitor 302 stores Cb'Vsup charge and the parasitic capacitance 310 has no charge.

[0028] Next, as shown in FIG. 3 (b), by setting SW1 to the electrode ERws308 side and SW2 to the electrode ERpul side, the charge stored in the boost capacitor 302 is charged to the parasitic capacitance 310. · Boost transferred by sharing and the common node of capacitor 302 and parasitic capacitance 310. If the voltage level at ERws308 is Vx, the original charge Cb'Vsup is stored in boost 'capacitor 302 Cb' It is divided into the charge of (Vx – Vpul) and the charge of Cw'Vx stored in the parasitic capacitance 310. This Vx is generated at the electrode ERws 308, and this actually becomes Vpp which is the high level voltage of the word line in the word line circuit 102. If Cb / Cw = K,

Vx = K · (Vsup + Vpul) / (K + 1) ..... [Equation 2]

It becomes. Since the charge Qtr transferred to the parasitic capacitance 310 is Cw'Vx,

Qtr = CwK- (Vsup + Vpul) / (K + l) ..... [Equation 3]

It becomes.

[0029] Then, as shown in Fig. 3 (c), SW1 is opened to reset this circuit. By bringing W2 to ground, the boost'capacitor 302 is ready for charging on the next access. At this time, since the voltage level of the low potential side electrode of the boost'capacitor 302 is lowered from Vp ul to 0 V, if the voltage level of the high potential side electrode is Vr,

Vr = (Vx Vpul) = (K · Vsup Vpul) / (K + 1) ..... [Equation 4]

It becomes. The next charge to the boost capacitor 302 is performed by connecting SW1 to the electrode ERsup312 again, so the charge Qin charged from the electrode ERsup312 is

Qin = Cb-(Vsup-Vr) = Cb-(Vsup + Vpul) / (K + 1) ..... [Equation 5]

It becomes. The first charge shown in Fig. 3 (a) is the force from the state where no voltage is applied to both ends of the boost 'capacitor 302. From the second time onward, the charge starts from the state where the voltage level of Vr remains. In practice, this is the charge required every time. Here, since K = CbZCw, Qin and Qtr are equal. In other words, the charge Qin charged every time becomes the charge Qtr transferred to the parasitic capacitor 310.

Next, consider the charge transfer efficiency in this local boost circuit. The charge transferred is Qtr, and the charge required for boost operation by boost 'capacitor 302 is the charge charge Qin to boost' capacitor 302 (which is equal to Qtr), and the rest is the circuit Some are due to operation, the main being the charge that raises the voltage level of the low side electrode of boost'capacitor 302 to Vpul. In other words, it is the charging current for the capacitor between the low potential side electrode of boost'capacitor 302 and the ground, and this capacitance is smaller than Cb but proportional to Cb. The charge is Rc'Cb'Vpul. This is because the current consumed by the local 'boost circuit is dominated by the current used to raise the voltage level of the low side electrode of the boost' capacitor 302 to Vpul, except for the charging current to the boost 'capacitor 302. Qeff is the rough transfer efficiency of the local boost circuit.

Qef = Qtr / (Qin + Rc-Cb-Vpul) ..... [Formula 6]

It becomes. Organizing this equation using Qin = Qtr

Qef = 1 / (1 + Rc- (K + 1) · Vpul / (Vsup + Vpul)) ..... [Equation 7]

It becomes.

[0031] Next, an optimum circuit system is obtained from these equations. First, Vsup and Vef both Vsup , The power to understand that the higher the Vpul, the better the Vsup will pass a large current through the boost'capacitor 302 so it is better to simply use the internal voltage of the chip (eg 1.65V) Table 1 shows how the value of K (= Cb / Cw) is different for different values of Vpul, for example, when a boost voltage Vx of 2.8V is obtained from an internal voltage of Vsup = 1.65V.

Vx = K · (Vsup + Vpul) / (K + 1) = 2.8 ..... [Equation 8]

It is calculated from [Equation 7], and what value Qel¾ is obtained from the value of K and Vpul. Here, Rc is assumed to be 0.3 in [Equation 7]. In other words, it is assumed that the capacitance between the low potential side electrode of the boost capacitor 302 and the ground is 30% of Cb.

[table 1]

Table 1 shows that the higher V pul, which is the voltage level that lifts the low-potential side electrode of the boost capacitor 302, the lower the K and the better the charge transfer efficiency. That is, at first glance, increasing Vpul increases the charge that raises the voltage level of the low potential side electrode of boost'capacitor 302. Qel¾S may be worsened, but in reality, the effect of decreasing becomes larger. Cb can be reduced, and Qef improves with higher Vpul. Therefore, it can be seen that Vpul should be as high as possible in order to operate the local boost circuit efficiently and with low current. If Vpul is set to 2.8V, the same as Vpp, K is 1.7 That is, Cb is a force that can be increased by about 70% of Cw. If the internal voltage of the Vpul Kamori chip is about 1.6V, Cb needs to be 5.6 times Cw. In other words, considering that Qtr is always a constant value Cw'Vx = 2.8 'Cw, Vpul is high to transfer this same charge, and the unwinding force is small! /, Cb is good Show me that! /

[0033] A configuration according to an embodiment of the present invention will be described below based on the above analysis results. FIG. 4 shows a configuration of a memory system 410 including a feeder circuit 420 with a local boost circuit 400 and a Vpp pump 404 and a Vnn pump 406 according to an embodiment of the present invention. is there. Word line driver circuit in word line circuit 420 422 p-channel source drive signal (SDV) that supplies voltage to the source of MOS FET 424. Driver that drives 426 High-side supply voltage supply line (electrode) to 428 ERws430 (voltage level: Vws), where the local boost circuit 400 is connected via SW1. The voltage level Vws of the electrode E Rws430 is low when the word line 432 is off, and the total electrostatic capacity including the capacitance of each word line in the word line circuit 420 from the electrode ERws430 to the ground is included. The capacitance (corresponding to the “parasitic capacitance” in the above description) is Cw. The power supply voltage supplied by Vpp is the same as that of the prior art in FIG. 2, that is, the low address • The decoder output signal RDout434 of the decoder that drives the decoder 436 is supplied from the Vpp pump 404. In addition, the drain side 428, 436, and 438 inlet side supply voltage is Vnn supplied from the Vnn pump 406.

[0034] The high-side power supply voltage of the driver 436 is Vpp supplied from the Vpp pump 404. The reason is that the high-side power supply line of the driver 436 receives a large number of decoder output signals (128 lines in this embodiment). In actual operation, only one of the outputs (for example, RDout434) changes from high to low at the same time, and this output is also connected to a small number (in the case of this embodiment). It only drives the gates of FETs (eg, p-channel MOS FET424) in the 8) word line driver circuit, and even if the high-side power supply voltage Vpp of driver 436 is supplied from Vpp pump 404, Vpp pump 404 This is because almost no current flows.

[0035] On the other hand, the source 'drive signal (SDV) is used to drive the word line that follows it to low and high, and the word line is a very large number of memories in the memory' cell 'array 452. Because it is connected to the gate of the 'cell of cell' transistor, it consumes a large amount of current.

The high-side power supply voltage of the dryno 28 that drives the source drive signal is supplied from the local boost circuit 400 that optimizes the efficiency from the inefficient Vpp pump 404. In addition, as described above, the voltage level supplied to the electrode for raising the voltage level of the low potential side electrode of the boost 'cyanter 442 (capacitance: Cb) for the optimization of the local' boost circuit 400 (Fig. In this embodiment, Vpp is set to Vpp because the higher Vpul) in 3 is better.

[0036] As described above, in the embodiment according to the present invention, Vpp itself is generated and supplied by the Vpp pump 404 as in the prior art. This efficiency is bad, and the pump does not flow current as much as possible. Most current supply is handled by the local boost circuit 400.

[0037] It should be noted that to raise the low-side electrode of the boost capacitor 442 to Vpp, it is normal to use the current from the Vpp pump 404. As a means to further reduce the current from the Vpp pump 404, the first step from OV The n-channel MOS FET source's follower (drain ground type) circuit can be used to raise the voltage level and then switch to Vpp from the Vpp pump 404 when the voltage level rises. The reason for this is that the capacitor between the low-potential side electrode of the boost 'capacitor 442 and the ground is usually the capacitance in the diffusion layer where the source and drain are shorted in the n-channel MOS FET and under the inverted N-type channel. This is because the capacitance is originally small and becomes smaller as the voltage is higher because the capacitance is parallel to the capacitance in the depletion layer that is reverse-biased with the P-type substrate.

[0038] In addition, SW1 in Fig. 4 normally uses a source-follower (drain-grounded) circuit consisting only of n-channel MOS FETs. In the case of n-channel MOS FETs, the gate voltage must be very high. Since it does not operate as a sufficient switch, it is actually necessary to apply 3 times the voltage of Vdd to the gate. According to the embodiment of the present invention, a p-channel MOS FET in which the N-type substrate is always held by the voltage from the Vpp pump 404 can be adopted instead of the switch using only the n-channel MOS FET. Low charge due to charge transfer and high reliability at the gate because high voltage is not required at the gate. is there.

[0039] As shown in FIG. 4, the local boost circuit 400 is activated for each activated memory 'cell array 450, 452, and decodes the address given to the memory' chip. Thus, since the force that requires current in advance, that is, which local boost circuit should be activated, is divided, it is possible to prepare for performing the above-described boost operation for the local boost circuit. Also, the local 'boost circuit 400 is used to supply most of the current locally at the required location in the required amount, so the word line circuits that actually operate from the Vpp pump 4004 and Vnn pump 406 respectively. Wiring resistance up to 420 is not a problem at all.

[0040] In an actual design, based on the total capacitance Cw including the estimated capacitance of each word line in the word line circuit 420 so as to obtain the necessary Vpp as the high level voltage of the word line. The power to determine the value of Cb of the booster capacitor 442 as described above Since some current is used from Vpp as described above, by optimizing the value of Cb etc. to compensate for it, control of Vpp pump 404 The voltage level that the circuit senses can be reduced, and the Vpp pump is hardly operated. As a result, the current consumption in the word line circuit 420 can be greatly reduced. In the example of word line circuit 420 in Figure 4 with 1024 word line power, one source 'drive signal 426 is connected to 128 word line driver circuits, so one word per source' drive signal. The capacity of the line circuit 420 is about 2 pF for 128 words per line, so if Vpul is set to Vpp of 2.8 V, Cb will be 1.7 times Cw according to Table 1, leaving a margin. Even if it is doubled, Cb is only 4pF, and the necessary voltage and current can be supplied with low current and small area.

Next, detailed operation steps based on the configuration according to the embodiment of the present invention will be described below. First, the operation when the word line voltage level is set to Vpp will be described. FIGS. 5 (a) to 5 (c) show the operation steps of the Vpp mouth / single boost circuit 502 for the word line circuit 500 based on the embodiment of the present invention, and FIG. ~ (C) is a timing chart showing the transition of the voltage level of the word line 510 in association with each of FIGS. 5 (a) to (c). [0042] There has been a request to initiate access to the memory 'system (actually the memory' cell 'array in that memory' system), eg, the low address of a row address decoder (not shown) In response to the start of decoding, as shown in Fig. 5 (a), SW3 is opened and SW1 is placed on the electrode ERsup522 side at a predetermined timing (time when it hits TO in Fig. 6 (a)). By setting SW2 to the ground side, the Vpp boost capacitor 5 24 (capacitance: Cb) is charged. This is to prepare for starting boost by the Vpp boost capacitor 524 as the word line (WL) 510 is selected by the row 'address' decoder. Since the voltage level of the electrode ERws512 is Vnn, the word line 510 is at a low level (Vnn), and RDout 514 is directly biased with Vpp generated by the Vpp pump. There is a decoupling capacitor 520 (capacitance: Cdp) between the connection between the Vpp pump 506 and the local 'boost circuit 502' for Vpp and the ground, and has a very large capacitance on the order of nF. .

[0043] After the Vpp boost 'capacitor 524 has been charged, the decoding of the mouth'address'decoder's mouth'address is determined based on the access start request, and the word line circuit 500 belongs to In response to the fact that a memory cell array has been specified and actual access to a specific memory cell has begun, at a given timing (the time when it hits T1 in Fig. 6 (b)), Fig. 5 (b) As shown in Fig. 3, SW1 is set to the electrode ERws512 side, and then SW2 is set to the output side of the Vpp pump 506 to set the voltage level to Vpp. As a result, the electric charge is discharged from the boost'capacitor 524 and supplied to the electrode ERws512, and the voltage level of the electrode ERws512 is the total capacitance Cw and Cb including the capacitance of each word line in the word line circuit 500. If the word line 510 is selected by the mouth 'address' decoder, the word line 510 is boosted to the same level as the above voltage level. It is possible to read data from the memory cell connected to the word line 510.

[0044] After the discharge from the Vpp boost 'capacitor 524, at a predetermined timing (the time when it hits T2 in Fig. 6 (b)) while the access to the memory' cell continues, SW3 is closed and the Vpp pump 506 Connect to the output side. This is because the charge lost from the Vpp pump 506 is compensated for by the Vpp local boost circuit 502 with a slightly higher voltage! In addition, when the word line 510 needs to be kept at a high level for a long time such as in the page mode, the voltage level is prevented from being lowered due to a current leak. Leakage is generally low, and even if this is present, decoupling of a large capacitance Cdp is supplied from the capacitor 520, so that the Vpp value immediately drops and the pump-up operation starts. There is no.

[0045] After that, at a predetermined timing (time corresponding to T3 in Fig. 6 (c)) before the access end request to the memory 'system, SW3 is opened as shown in Fig. 5 (c). After that, SW1 is opened, SW2 is grounded, and the voltage level of the low-potential side of the Vpp booster capacitor 524 is grounded, so that the Vpp boost capacitor 524 is charged again. The voltage level at both electrodes of Vpp boost capacitor 524 is initialized (reset). Since the electrode ERws512 is connected to nowhere and the word line 510 remains in the high level state, the electrode ERws512 remains charged to Vpp. Note that the Vnn local 'boost circuit 504 does not operate at the timing shown in Figs. 6 (a) to (c)!

Regarding detailed operation steps based on the configuration according to the embodiment of the present invention, the operation for returning the voltage level of the word line to Vnn will be described next. FIGS. 7 (a) to (c) show the operation of the Vnn local boost circuit 504 for the word line circuit 500 according to the embodiment of the present invention, and FIGS. 8 (a) to (c). Fig. 7 is a timing chart showing the transition of the voltage level of the word line 510, corresponding to each of Figs. 7 (a) to 7 (c).

[0047] In response to a request for termination of access to the memory system, that is, in response to completion of decoding of a row address by a row address decoder, for example, a predetermined timing (FIG. 8 (a) At time T4), as shown in Fig. 7 (a), SW4 is on the electrode ERws512 side and SW5 is on the ground side. As a result, the electric charge charged to the total capacitance Cw including the capacitance of each word line in the word line circuit 500 is charged to the Vnn boost'capacitor 53 0 (capacitance: Cn). Di force coupling 'capacitor 532 (capacitance: Cdn) exists between the ground and the output of Vnn pump 508, and has a large capacity of the order of nF. Voltage from electrode ERws512 to electrode ERws512 with Vnn boost 'capacitor 530 charge caused by charging between Cw and Cn' The bell starts to drop from Vpp, and at the same time, the voltage level of the word line 510 starts to drop as shown in the timing chart of FIG. 8 (a) according to the non-selection of the word line 510 based on the access end request.

[0048] After the charging of the Vnn boost'capacitor 530 is completed, the voltage level of the non-selected word line becomes the low level and before the actual access is finished (FIG. 8 (b) 7), set SW4 to the ground side and SW5 to the output side of the Vnn pump 508 so that the voltage level of the low potential side electrode of the Vnn boost 'capacitor 530 is Vnn as shown in Fig. 7 (b). To. As a result, the electric charge stored in the Vnn boost 'capacitor 530 is supplied to the Vnn pump 508. This is because the word line 510 is deselected (ie, already deselected at T4), RDout514 and WLr518 go high, and the voltage level of the word line 510 is lowered to Vnn. The power required for this pull-down operation is supplied by the boost from the Vnn boost'capacitor 530, and the charge originally charged in the Vnn boost capacitor 530 is reused of the charge stored in the electrode ERws512. Therefore, the operation is more efficient than the charging current of the power supply.

[0049] After that, in response to the fact that the voltage level of the non-selected word line becomes low level (Vnn) and the actual access is completed, a predetermined timing (time corresponding to T6 in FIG. 8 (c)) Then, as shown in Fig. 7 (c), SW4 is open, SW5 is grounded, and the boosting capacitor for Vnn is set to ground by setting the voltage level of the low potential side electrode of capacitor 530 to ground. Initializes (resets) the voltage level at both electrodes of the Vnn boost capacitor 530 to recharge the 530.

[0050] When all the operation steps are completed as described above, the next access start request to the memory 'system, for example, decoding start by inputting the mouth' address 'mouth to the decoder' address, Repeat the state from Fig. 5 (a) again. In this way, the Vnn local boost circuit 504 side reuses the charge generated on the Vpp local boost circuit 502 side and supplies the charge from there at the required timing, so that high efficiency can be obtained. Also, when driving to Vpp and Vnn! /, The Vpp pump 506 and Vnn pump 508 almost do not work, and the local 'boost circuit for Vpp' 502 and local 'boost for Vnn' respectively. Since most of the current is supplied from the circuit 504, a significant reduction in current consumption in the word line circuit 500 can be achieved.

[0051] While the present invention has been described using the embodiment, it goes without saying that the technical scope of the present invention is not limited to the scope described in the embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiment. Further, it is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

Brief Description of Drawings

[0052] [FIG. 1] A configuration diagram of a DRAM chip in the prior art.

FIG. 2 shows a detailed circuit example of a word line circuit.

[Figure 3] Shows the principle of charge transfer by a local 'boost circuit.

FIG. 4 shows a configuration of a memory system including a word line circuit to which a local boost circuit is added and a Vpp pump and a Vnn pump according to an embodiment of the present invention.

FIG. 5 shows operation steps of the Vpp local boost circuit for the word line circuit according to the embodiment of the present invention.

[FIG. 6] The transition of the voltage level of the word line is shown in the timing chart corresponding to FIG.

FIG. 7 shows the operation steps of the local boost circuit for Vnn with respect to the word line circuit according to the embodiment of the present invention.

[FIG. 8] The transition of the voltage level of the word line is shown in the timing chart corresponding to FIG.

Claims

The scope of the claims

[1] Memory 'cell' array,

An access control circuit that receives either an access start request or an access end request for the memory cell array and controls access to the memory cell array;

A charge precharged in response to the access start request is supplied to the access control circuit, and the access control circuit is driven from a low voltage for memory access to a high voltage for memory access. Voltage supply boost circuit and

With a 'memory' system.

[2] The low voltage supply boost circuit according to claim 1, further comprising: a low voltage supply boost circuit for absorbing excess charge when the access control circuit is switched from the high voltage to the low voltage in response to the access termination request. The memory 'system described.

[3] The high voltage supply boost circuit includes:

A high voltage boost capacitor for discharging a charge pre-charged from a first reference voltage supply source in response to the access start request to the high voltage supply source in the access control circuit;

One electrode of the high voltage boost capacitor is connected to the supply source of the first reference voltage during the charging, and the one electrode is connected to the supply source of the high voltage in the access control circuit during the discharging. At other times, a first semiconductor switch that opens the one electrode,

The other electrode of the high-voltage boost capacitor is connected to the ground during the charging, the other electrode is connected to the second reference voltage supply source during the discharging, and the other electrode is connected to the ground during the other times. The memory system according to claim 2, further comprising a second semiconductor switch to be connected.

[4] It further comprises a high voltage generation circuit that generates and supplies the high voltage from the power supply voltage,

The high voltage supply boost circuit comprises:

The one electrode of the high-voltage boost capacitor is connected to a high-voltage supply source of the high-voltage generation circuit, and charges are compensated from the one electrode to the high-voltage generation circuit. Third semiconductor switch for

The memory 'system of claim 3, further comprising:

[5] It further comprises a low voltage generation circuit for generating and supplying the low voltage from the power supply voltage,

The low voltage supply boost circuit comprises:

A low voltage boost capacitor for discharging the charge previously charged from the supply source of the high voltage in the access control circuit through the low voltage supply source of the low voltage generation circuit in response to the access end request When,

One electrode of the low-voltage boost capacitor is connected to the supply source of the high voltage in the access control circuit during the charging, the one electrode is connected to the ground during the discharging, and the other electrode is connected during the other times. A fourth semiconductor switch that opens the electrode of

The other electrode of the low-voltage boost capacitor is connected to the ground during the charge, the other electrode is connected to the low-voltage supply source of the low-voltage generation circuit during the discharge, and the other electrode is used at other times. A fifth semiconductor switch that connects

The memory 'system of claim 4, comprising:

[6] The memory 'cell' array is a DRAM memory / senior array composed of n-channel MOS FETs.

The access control circuit is a word line circuit that drives a plurality of word lines connected to the gates of the memory cells constituting the memory cell array.

6. The memory system according to claim 5.

[7] The first reference voltage includes a power supply voltage;

The second reference voltage includes the high voltage;

The second reference voltage is supplied from the high voltage supply source of the high voltage generation circuit.

6. The memory system according to claim 5.

8. The memory system according to claim 5, wherein each of the high voltage generation circuit and the low voltage generation circuit also serves as a charge pump circuit.

[9] In the memory system, the memory access to the access control circuit that controls access to the memory 'cell' array upon receiving either an access start request or an access end request for the memory 'cell' array. A method of supplying a voltage by a voltage supply boost circuit for driving with a high voltage for memory and a low voltage for memory access,

A first charging step of charging the voltage supply boost circuit in response to the access start request;

A first discharging step of discharging the charged electric charge and supplying it to the access control circuit after the charging is completed;

A first initial phase step for initializing for recharging while retaining the residual charge after the discharge in the voltage supply boost circuit;

Having a method.

[10] a second charging step of charging the voltage supply boost circuit from the access control circuit in response to the access end request;

A second discharge step for discharging the charged electric charge after the charging is completed; and a second initial stage for initializing for recharging with the residual electric charge after the discharge being held in the voltage supply boost circuit. Step and

10. The method of claim 9, further comprising:

[11] The voltage supply boost circuit includes a high voltage boost capacitor,

The first charging step includes

Responsive to the access initiation request, connecting one electrode of the high voltage boost capacitor to a source of a first reference voltage;

Connecting the other electrode of the high voltage boost capacitor to ground, and the first discharging step comprises:

After the charging is completed, in response to an access start based on the access start request, connecting the one electrode to the high voltage source in the access control circuit;

After the connection, connecting the other electrode to a source of a second reference voltage; And the first initial step comprises

Opening the one electrode at a predetermined timing after the discharge and before the access termination request;

Connecting the other electrode to ground;

Have

The residual charge after the discharge is held in the high voltage boost capacitor, and the voltage level of the other electrode is grounded to be initialized for recharging.

The method of claim 10.

[12] The memory system further includes a high voltage generation circuit that generates and supplies the high voltage from a power supply voltage,

At a predetermined timing after the first discharge step and before the first initial step, the one electrode of the high voltage boost capacitor is connected to a high voltage supply source of the high voltage generation circuit. Filling the high voltage generation circuit with charge from the one electrode;

After the compensating step, at a predetermined timing before the first initial phase step, releasing the connection of the one electrode to the high voltage supply source of the high voltage generation circuit;

The method of claim 11, further comprising:

[13] The voltage supply boost circuit further includes a low voltage boost capacitor,

The memory system further includes a low voltage generation circuit that generates and supplies the low voltage from a power supply voltage,

The second charging step includes

Responsive to the access termination request, connecting one electrode of the low voltage boost capacitor to the source of the high voltage in the access control circuit; and connecting the other electrode of the low voltage boost capacitor to ground And the second discharging step comprises:

After the completion of the charging, a predetermined time before the end of access based on the access end request Connecting the one electrode to the ground and connecting the other electrode to a low voltage supply source of the low voltage generation circuit at the timing of the second initial stage. Steps

Responsive to the end of access, opening one of the electrodes, connecting the other electrode to ground, and

Have

The residual charge after the discharge is held in the low voltage boost capacitor, and the voltage level of the other electrode is grounded to be initialized for recharging.

The method according to claim 12.

[14] A device for supplying a voltage to a target system that requires driving of an internal circuit by at least binary voltages of a high voltage and a low voltage,

In order to supply the target system with a charge that has been precharged in response to a request to start driving with the high voltage to the target system, and drive the internal circuit in the target system from the low voltage to the high voltage. A high voltage supply boost circuit, and an excessive charge when the internal circuit of the target system is switched from the high voltage to the low voltage in response to a request to finish driving the high voltage to the target system. Low voltage supply boost circuit and

A device comprising:

[15] A method of supplying a voltage by a voltage supply boost device to a target system that requires driving of an internal circuit by at least two voltages of a high voltage and a low voltage, the high voltage for the target system A first charging step for charging the voltage supply boost device in response to a request to start driving by voltage;

A first discharging step of discharging the charged charge and supplying it to the target system after the charging is completed;

In response to the high voltage drive termination request to the target system, the pair The second charging step of charging the voltage supply boost circuit with a charge, the second discharging step of discharging the charged charge after the completion of the charging, and the residual charge after the discharging as the voltage A second initial step that initializes for recharging while held in the supply boost circuit;

Having a method.