WO2007066456A1

WO2007066456A1 - Interface circuit

Info

Publication number: WO2007066456A1
Application number: PCT/JP2006/321674
Authority: WO
Inventors: Daijyu Murakami
Original assignee: Matsushita Electric Industrial Co., Ltd.
Priority date: 2005-12-05
Filing date: 2006-10-30
Publication date: 2007-06-14

Abstract

An error detecting circuit (180) detects parity errors occurred in analog circuits during the receipt of SYNC and outputs signals sequentially to a circuit-characteristic setting section of a digital circuit (400) as to whether the detecting circuit (180) detects them or not. When the number of detected parity errors is over a predetermined value, electrical characteristics of a terminating resistance (110), a charge pump group (152), a low-pass filter (153) and a voltage-controlled oscillator (154) are changed by a circuit-character setting section and changes of the number of detected parity errors are measured by the error detecting circuit (180). Thus, characteristics of these circuits are set to electrical characteristics for the least number of the parity errors.

Description

Specification

interface circuit

Technical field

[0001] The present invention relates to an interface circuit that is incorporated into a computer, computer peripheral equipment, etc. and performs serial communication.

Background technology

[0002] To connect a personal computer (PC) and PC peripherals such as a CD (Compact Disk) drive, DVD (Digital Versatile Disk) drive, printer, etc., both the PC and the PC peripherals must be connected. It must be equipped with an interface for transmitting and receiving signals according to standards.

[0003] Standards for such interfaces include ATAZATAPI (AT Attachment).

Parallel communication methods, such as SerialATA and USB (Universal Serial Bus), use a combination of signal lines with multiple data buses and multiple control lines to communicate. There is a serial communication method that uses only several pairs of differential signal lines to communicate. Serial communication methods are currently being used for reasons such as achieving high-speed communication and ensuring communication stability, as well as making it easier to connect PCs and PC peripherals for user convenience. PCs and PC peripherals that have been adopted have become mainstream.

[0004] Recent serial communication systems have communication speeds of gigabits per second. Therefore, in order to ensure stable communications, interface circuits installed in PCs and PC peripherals must be designed and manufactured with greater margins than in the past. For example, in standards such as USB and SerialATA, there is a function to detect errors on the interface bus by incorporating mechanisms such as CRC (Cyclic Redundancy Check) calculation into the protocol, but if an interface circuit with a small margin is used for communication, , a CRC error can quickly lead to a serious communication error.

[0005] For example, when playing back video images on a PC peripheral device that plays DVD videos, C

If an RC error occurs, there is a possibility that the video may drop frames and cannot be played normally. Additionally, if the PC peripheral device is a recordable storage device, if a CRC error occurs while the PC is writing data to the storage device, the data will not be written correctly and the recording will fail. There is a possibility that it will happen. For example, if the recording medium is a DV DR (Digital Versatile Disc—Recordable) that can only be written to once, a single CRC error may damage the medium.

[0006] Furthermore, in ICs (Integrated Circuits) equipped with circuits capable of gigabit per second communication, communication errors may occur due to the influence of manufacturing conditions, operating temperature, power supply voltage during use, etc. Therefore, it is necessary to ship only high-precision products even if the yield is reduced, resulting in high-cost ICs.

[0007] Furthermore, in order to manufacture such high-precision products, it is necessary, for example, to increase the size of the transistors that make up the analog circuit or to increase the number of parts, which also increases costs. It is tied to and ends up.

[0008] The above problem can be solved by changing the communication speed or the current value driving the signal line in the parallel communication interface circuit depending on the occurrence of the CRC error. There is a method that avoids subsequent CRC errors (for example, see Patent Document 1).

[0009] According to this interface circuit, after a CRC error is detected, the characteristics of the circuit are adjusted to the optimum communication state, and stable communication becomes possible.

Patent document 1: Japanese Patent Application Laid-open No. 11 249821

Disclosure of invention

The problem that the invention seeks to solve

[0010] However, as in the above interface circuit, if the communication speed is reduced to a level that allows safe communication in order to avoid CRC errors, it cannot be applied to devices that require high-speed communication.

[0011] Furthermore, it is originally preferable to be able to adjust the communication speed and electrical characteristics before a communication error actually occurs.

[0012] Furthermore, ICs equipped with circuits capable of gigabit per second communication require highly accurate and high quality shipping inspection to ensure stable operation. For this purpose, we introduced a high-precision IC tester. It is necessary to do so, which increases costs.

[0013] The present invention has been made with attention to the above-mentioned problem, and an object of the present invention is to provide an interface circuit that can perform stable communication while suppressing an increase in cost.

Means to solve problems

[0014] In order to solve the above problems, one aspect of the present invention includes:

An interface circuit that performs communication using a communication method in which a predetermined pattern of signals is transmitted prior to data transmission,

an analog circuit into which the received signal is input;

an error detection circuit that detects an error that occurs when the signal of the predetermined pattern passes through the analog circuit;

a circuit characteristic setting unit that changes characteristics of the analog circuit so that errors detected by the error detection circuit are reduced;

It is characterized by having the following.

[0015] As a result, the electrical characteristics of the analog circuit are optimally adjusted before data is received, so that the frequency of occurrence of error errors thereafter can be reduced.

[0016] Further, one aspect of the present invention is

The above interface circuit,

The circuit characteristic setting section is characterized in that it is configured to change the characteristics of the analog circuit when the number of errors detected by the error detection circuit exceeds a predetermined number.

[0017] This makes it possible to prevent characteristic adjustment from being performed, for example, when a parity error occurs due to sudden noise. In addition, it is possible to avoid placing an unnecessary load on the system such as the circuit characteristic setting section.

[0018] Further, one aspect of the present invention is

The above interface circuit,

The error detection circuit is characterized in that it is configured to detect error errors.

[0019] Further, one aspect of the present invention is The above interface circuit,

The communication method is a bit stuff method,

The error detection circuit is characterized in that it is configured to detect a bit stuff error.

[0020]Thus, internal errors occurring in the analog circuit are detected.

[0021] Further, one aspect of the present invention is

The above interface circuit,

The predetermined pattern signal is a signal that is transmitted even after communication is established, and the error detection circuit is configured to detect errors even after communication is established.

[0022]Thereby, the electrical characteristics of the analog circuit are adjusted even after communication is established, so that the circuit characteristics can be set in accordance with environmental changes that occur during operation, such as temperature changes.

[0023] Further, one aspect of the present invention is

The above interface circuit,

The analog circuit includes a PLL circuit that receives a received signal as input, and the circuit characteristic setting section is configured to change the characteristics of the PLL circuit.

[0024] Further, one aspect of the present invention is

The above interface circuit,

The PLL circuit includes a charge pump, a low-nos filter, and a voltage-controlled oscillator, and

The characteristic of the PLL circuit that is changed by the circuit characteristic setting section is at least one of the amount of current of the charge pump, the cutoff frequency of the low-pass filter, and the oscillation frequency of the voltage-controlled oscillator. It is characterized by

[0025] Further, one aspect of the present invention is

The above interface circuit,

The analog circuit includes a receiver circuit that amplifies a received signal, and the circuit characteristic setting section is configured to change an amplification factor of the receiver circuit. It is characterized by the presence of

[0026] Further, one aspect of the present invention is

The above interface circuit,

The analog circuit includes a terminating resistance element whose resistance value can be varied in a path through which the received signal is input,

The circuit characteristic setting section is characterized in that it is configured to change the resistance value of the terminating resistor element.

[0027] These adjust the electrical characteristics (output current amount and voltage value) of the analog circuit.

[0028] Further, one aspect of the present invention is

The above interface circuit,

The predetermined pattern signal is a signal for synchronization adjustment.

[0029]Thereby, the electrical characteristics of the analog circuit are adjusted while receiving the synchronization signal.

[0030] Further, one aspect of the present invention is

The above interface circuit,

Furthermore, it is equipped with a pattern generation circuit that generates test signal patterns.

The analog circuit is characterized in that it is configured to be able to switch and input a test signal pattern generated by the pattern generation circuit instead of the received signal.

[0031] Further, one aspect of the present invention is

The above interface circuit,

The test signal pattern is at least one of the following: a signal pattern with an upper limit frequency determined by a communication system standard, a random signal pattern, and a pattern the same as a signal for synchronization adjustment. shall be.

[0032] Since a test signal pattern is generated by these, the electrical characteristics of the analog circuit can be set using the interface circuit alone.

Effect of the invention

[0033] According to the present invention, the electrical characteristics of the analog circuit can be adjusted before a communication error actually occurs, so that stable communication can be performed while suppressing an increase in cost. Brief description of the drawing

[FIG. 1] FIG. 1 is a block diagram showing the configuration of an interface circuit according to an embodiment of the present invention.

[Figure 2] Figure 2 is a block diagram showing the configuration of the charge pump.

[Figure 3] Figure 3 is a diagram showing the signals exchanged between the sending side and the receiving side in SerialATA standard communication.

Explanation of symbols

100 interface circuit

110 Terminal resistor

120 receiver circuit

130 Emphasis circuit

140 Power supply

150 PLL circuit for reception

151 Phase Detector

152 Charge pump

152a current source

152b switch

152c switch

152d current source

153 Low pass filter

154 Voltage Controlled Oscillator

160 Deserializer

170 8bZl0b conversion circuit

180 Error detection circuit

190 8b,10b conversion circuit

200 Serializer

210 PLL circuit for transmission

220 driver circuit 230 Terminal resistor

240 Pattern generation circuit

250 switch

300 host device

400 digital circuits

BEST MODE FOR CARRYING OUT THE INVENTION

[0036] Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an interface circuit 100 according to an embodiment of the present invention.

[0037] Interface circuit 100 is connected to host device 300 via an interface cable to perform communication. In this embodiment, it is assumed that the host device 300 is a personal computer (hereinafter referred to as a PC) and uses SerialATA as a communication interface.

[0038] Furthermore, the interface circuit 100 is further connected to a digital circuit 400, and is incorporated together with the digital circuit 400 into, for example, a PC peripheral device such as a DVD drive or a PC. The digital circuit 400 is a circuit that processes signals received in this PC peripheral device or PC, and, as will be described in detail later, is a circuit that controls electrical characteristic settings of the analog circuit in the interface circuit 100. It includes a characteristic setting section (not shown).

[0039] (Configuration of interface circuit 100)

As shown in Figure 1, the interface circuit 100 includes a termination resistor 110, a receiver circuit 120, an emphasis circuit 130, a power supply 140, a reception PLL circuit 150 (PLL is an abbreviation for Phase Locked Loop), a deserializer 160, and an 8bZl0b conversion circuit. Equipped with a circuit 170, an error detection circuit 180, an 8bZl0b conversion circuit 190, a serializer 200, a transmission PLL circuit 210 (abbreviated as T xPLL in the figure), a driver circuit 220, a terminating resistor 230, a pattern generation circuit 240, and a switch 250. It is made up of.

[0040] The terminating resistor 110 is connected to the signal receiving path, and its resistance value can be varied under the control of the circuit characteristic setting section of the digital circuit 400. For SerialAT A, this resistance value is specified as 100 Ω ± 15% for differential signal input according to the standard. By adjusting the terminating resistor 110 according to the standard, it is possible to Impedance matching can be performed. Further, the amplitude of the input signal to the receiver circuit 120 can also be changed depending on the rise or fall of the resistance value.

[0041] Receiver circuit 120 is configured to amplify a signal received from host device 300 (hereinafter referred to as a received signal) to a predetermined amplitude.

[0042] The emphasis circuit 130 is configured to change the amplitude of the signal output from the receiver circuit 120 in accordance with the control of the circuit characteristic setting section of the digital circuit 400.

[0043] Power supply 140 is adapted to supply voltage to emphasis circuit 130.

[0044] The receiving PLL circuit 150 includes a phase detector 151 (abbreviated as PD in the figure), a charge pump group 152 (abbreviated as CP in the figure), a low-pass filter 153 (abbreviated as LP in the figure), and a voltage A controlled oscillator 154 (abbreviated as VCO in the figure) is provided to synchronize the received signal with the clock signal inside the interface circuit 100.

[0045] Phase detector 151 detects the phase difference between the received signal and the output signal of voltage controlled oscillator 154.

[0046] As shown in FIG. 2, the charge pump group 152 includes multiple stages of charge pumps configured in parallel with a current source 152a, a switch 152b, a switch 152c, and a current source 152d. The output is connected to a low pass filter 153.

[0047] Each charge pump can adjust the amount of current flowing through the charge pump group 152 and the current balance by turning off the switch 152b and the switch 152c according to the phase difference detected by the phase detector 151. . Further, the switch 152a and the switch 152b of each charge pump can also control ONZOFF in accordance with the control of the circuit characteristic setting section of the digital circuit 400 regardless of the phase difference. That is, the amount of current output by charge pump group 152 can be swept by the circuit characteristic setting section of digital circuit 400.

[0048] The low-pass filter 153 is a filter composed of a resistive element and a capacitive element, and the cutoff frequency can be varied by varying at least one of the resistance value of the resistive element and the capacitance of the capacitive element. ing. The resistance value and capacitance described above are controlled by a circuit characteristic setting section of the digital circuit 400.

[0049] Voltage controlled oscillator 154 outputs a clock signal with a frequency according to the input control voltage. It's supposed to be powerful. This voltage controlled oscillator 154 receives the output signal of the low-pass filter 153 as the aforementioned control voltage, and this control voltage can be shifted by the control of the circuit characteristic setting section of the digital circuit 400. .

[0050] The above-mentioned terminating resistor 110, receiver circuit 120, and receiving PLL circuit 150 are analog circuits, and in these analog circuits, the quality of the signal transmitted by the host device 300, noise entering from the cable etc., or the surroundings temperature etc. can cause errors in the signal.

[0051] The deserializer 160 receives the clock signal (serial signal) output by the receiving PLL circuit 150.

) to a 10-bit parallel signal. Note that in this embodiment, 2 bits of the 10 bits are parity data.

[0052] The 8b/10b conversion circuit 170 is designed to remove the 2-bit data included in the 10-bit parallel signal power and convert it into an 8-bit signal, which is output to the digital circuit 400. . A parity error occurs when a signal error occurs in an analog circuit. In other words, this parity error is an internal error that cannot be detected directly on the Serial ATA interface bus.

[0053] The error detection circuit 180 detects 8b according to the control of the circuit characteristic setting section of the digital circuit 400.

The parity error generated in the ZlOb conversion circuit 170 is detected and the presence/absence of detection is sequentially output to the digital sensor circuit 400.

[0054] The 8bZl0b conversion circuit 190 adds 2 bits of parity data to the 8-bit parallel signal output by the digital circuit 400 for transmission to the host device 300, and converts it into a 10-bit Noral signal. and output it.

[0055] Serializer 200 converts the 10-bit parallel signal output from 8bZl0b conversion circuit 190 into

, it is designed to convert to a 10-bit serial signal.

[0056] The transmission PLL circuit 210 is configured to output a 10-bit serial signal in synchronization with a clock signal of a predetermined frequency.

[0057] The driver circuit 220 transmits the serial signal output from the transmission PLL circuit 210 to the host device 30.

Now it starts sending to 0.

[0058] The terminating resistor 230 is connected to the signal transmission path, and the resistance value can be varied!/ヽru [0059] The pattern generation circuit 240 is configured to generate a predetermined test signal pattern and output it to the 8bZl0b conversion circuit 190. The test signal patterns to be generated include Notierra 1, which is most likely to occur!/ signal patterns, and signal patterns used in SerialATA communication from the time communication is established to the end (for example, the SYNC signal, which will be detailed later). ) or a random signal pattern can be applied.

[0060] Specific signal patterns that are likely to cause parity errors include, for example, signal patterns with the upper limit frequency specified in the standard, and cases where the usage environment is unstable in advance, such as usage environments at high temperatures. An example of this is a signal with a frequency assumed to be .

[0061] Switch 250 is a switch provided between the output of driver circuit 220 and the input of receiver circuit 120. Thereby, the output from the driver circuit 220 can also be transmitted to the receiver circuit 120.

[0062] The circuit characteristic setting section of the digital circuit 400 includes a register that holds the number of parity errors detected by the error detection circuit 180, and includes a register that holds the number of parity errors detected by the error detection circuit 180, and a register that holds the number of parity errors detected by the error detection circuit 180. The error detection circuit 180 is configured to detect a parity error while receiving a parity signal (such as a signal to be transmitted). Specifically, in this embodiment, a communication error is detected during reception of SYNC and primitive patterns (described in detail later) in SerialA TA standard communication.

[0063] Then, when the number of detected parity errors exceeds a predetermined number, the circuit characteristic setting section of the digital circuit 400 controls the electrical power of the termination resistor 110, the charge pump group 152, the low-pass filter 153, and the voltage-controlled oscillator 154. The circuit characteristics are changed to measure changes in the number of parity errors detected by the error detection circuit 180, and the characteristics of these circuits are set to the electrical characteristics that minimize the number of parity errors. Changing the characteristics when the number of parity errors exceeds a predetermined number in this way means that, for example, if you adjust the characteristics when a parity error occurs due to sudden noise, the margin for subsequent operations will be reduced. This is because there is a possibility that This is also to prevent the load on the digital circuit 400 from becoming unnecessarily large.

[0064] (Operation of interface circuit 100) When data sent by the host device 300 is received by the interface circuit 100 in SerialATA standard communication, the steps shown in Figure 3 are used to transmit signals in order to establish a communication method between the sending side and the receiving side. An exchange takes place.

[0065] Among the signals shown in Figure 3, COMRESET, COMINIT, and COMWAKE are called OOB (Out of Band) in Seria 1ATA standard communication, and each signal has a signal pattern called a primitive (burst signal) and a no signal. Consists of intervals (spaces)!,ru. Additionally, OOB is followed by the primitive patterns ALIGN and SYNC. OOB, ALIGN, and SYNC are interactions without CRC operations. Additionally, ALI GN and SYNC are signals used to synchronize communications.

[0066] First, the host device 300 transmits a COMRESET burst signal to the device (Step S 101).

[0067] The digital circuit 400 that received it communicates with the COMI via the interface circuit 100.

A burst signal called NIT is transmitted to the host device 300 (step S102).

[0068] After receiving COMINIT, host device 300 transmits a burst signal called COMWAKE to the device (step S103).

[0069] The digital circuit 400 that received COMWAKE from the host device 300 is the host device 30

0 via the interface circuit 100 (step S104).

[0070] Upon receiving COMWAKE, the host device 300 transmits the highest speed clock signal of SerialATA called D10.2 (Step S105).

[0071] In response, the digital circuit 400 transmits ALIGN, and the host similarly transmits ALIGN.

[0072] After that, the digital circuit 400 whose signals have been synchronized by ALIGN transmits a primitive pattern called SYNC to the host (step S 106).

[0073] When the host device 300 receives the SYNC from the digital circuit 400 and sends the same SYNC to the digital circuit 400, the establishment of mutual communication is completed.

[0074] The host device 300 and the digital circuit 400 send SYNC to each other until the digital circuit 400 sends the status to the host device 300. That is, the digital circuit 400 is the stator It is possible to continue receiving the SYNC sent by the host device 300 for a certain period of time until the host device 300 sends the SYNC.

[0075] Therefore, the circuit characteristic setting section of digital circuit 400 causes error detection circuit 180 to detect a parity error while receiving SYNC. Then, for example, by increasing or decreasing the resistance value of the termination resistor 110 or by sweeping the amount of current of the charge pump group 152, these circuits are set to have electrical characteristics that minimize the number of parity errors. .

[0076] As a result, the electrical characteristics of the analog circuit are optimally adjusted before data is received, and the frequency of subsequent note errors can be reduced.

[0077] Note that in SerialATA standard communication, SYNC is inserted at predetermined intervals even after the communication method is established, so the above circuit characteristics setting may be performed every time SYNC is received. This allows circuit characteristics to be set by following environmental changes that occur during operation, such as temperature changes.

[0078] Furthermore, the circuit characteristics of the interface circuit 100 can be set, for example, during inspection before product shipment, before starting communication, or even when the interface circuit 100 and the host device 300 are not connected. To do this, first, the pattern generation circuit 240 generates a test signal pattern. Then, switch 250 is switched so that driver circuit 220 and receiver circuit 120 are connected.

[0079] Thereby, the circuit characteristics can be set for the interface circuit 100 alone. In other words, circuit characteristics can be adjusted during pre-shipment inspections without the need for a high-precision IC tester. In addition, there is no need to reduce yield to ship only high-precision products or to increase the size of transistors that make up analog circuits. Therefore, according to this embodiment, stable communication can be performed while suppressing an increase in cost.

[0080] Note that note errors may be detected using any signal that allows circuit characteristics to be set prior to data transmission. Therefore, instead of SYNC as described above, you can also use, for example, ALIGN as described above.

[0081] In addition, in cases where there is no particular limit to the time for detecting an error or changing the circuit settings, the pattern generation circuit generates all patterns that may exist from the start to the end of communication. It may also be sent by This allows for higher quality communication Can be set to circuit characteristics.

[0082] Furthermore, the above embodiment may be applied to a USB interface. In this case, bit stuff errors can be detected instead of error errors.

[0083] Furthermore, the SerialATA and USB interfaces described above as communication methods are examples, and any communication method in which a predetermined pattern of signals is transmitted prior to data can be applied.

Industrial applicability

[0084] Since the interface circuit according to the present invention can adjust the electrical characteristics of the analog circuit before a communication error actually occurs, it has the effect of stably communicating while suppressing an increase in cost. However, it is useful as an interface circuit for serial communication built into computers and computer peripherals.

Claims

The scope of the claims

[1] An interface circuit that performs communication using a communication method in which a predetermined pattern of signals is transmitted prior to data transmission,

an analog circuit into which the received signal is input;

An interface circuit characterized by comprising:

[2] The interface circuit according to claim 1,

The interface circuit is characterized in that the circuit characteristic setting section is configured to change the characteristics of the analog circuit when the number of errors detected by the error detection circuit exceeds a predetermined number.

[3] The interface circuit of claim 1,

The interface circuit is characterized in that the error detection circuit is configured to detect error errors.

[4] The interface circuit according to claim 1,

The communication method is a bit stuff method,

An interface circuit, wherein the error detection circuit is configured to detect a bit stuff error.

[5] The interface circuit of claim 1,

The interface is characterized in that the signal of the predetermined pattern is a signal that is transmitted even after communication is established, and the error detection circuit is configured to detect an error even after communication is established. circuit.

[6] The interface circuit of claim 1,

The interface circuit is characterized in that the analog circuit includes a PLL circuit that inputs a received signal, and the circuit characteristic setting section is configured to change the characteristics of the PLL circuit. .

[7] The interface circuit according to claim 6,

The characteristic of the PLL circuit that is changed by the circuit characteristic setting section is at least one of the amount of current of the charge pump, the cutoff frequency of the low-pass filter, and the oscillation frequency of the voltage-controlled oscillator. An interface circuit featuring:

[8] The interface circuit of claim 1,

The analog circuit includes a receiver circuit that amplifies a received signal, and the circuit characteristic setting section is configured to change an amplification factor of the receiver circuit.

An interface circuit characterized by V.

[9] The interface circuit according to claim 1,

The circuit characteristic setting section is configured to change the resistance value of the terminating resistance element.

An interface circuit characterized by V.

[10] The interface circuit of claim 1,

An interface circuit characterized in that the signal of the predetermined pattern is a signal for synchronization adjustment.

[11] The interface circuit of claim 1,

The interface circuit is characterized in that the analog circuit is configured to be able to switch and input a test signal pattern generated by the pattern generation circuit instead of the received signal.

[12] The interface circuit according to claim 11,

The test signal pattern is at least one of the following: a signal pattern with an upper limit frequency determined by a communication system standard, a random signal pattern, and a pattern the same as a signal for synchronization adjustment. interface circuit.