WO2007066133A1

WO2007066133A1 - Memory cell

Info

Publication number: WO2007066133A1
Application number: PCT/GB2006/004601
Authority: WO
Inventors: Marlon Facey
Original assignee: Cavendish Kinetics Limited
Priority date: 2005-12-08
Filing date: 2006-12-08
Publication date: 2007-06-14
Also published as: GB0525025D0

Abstract

A memory cell (1) comprising a cantilever (2) moveable between a first position in which this is in contact with a contact pad (3) and a second position and which is out of contact with the contact pad, - an electromagnetic driving means (4, 5) for controllably driving the cantilever between its two positions; and a transistor (12) having its drain connected to the cantilever.

Description

MEMORYCELL

The present invention relates to a memory -cell -employing a micro-electro mechanical cantilever. The present invention also relates to a memory device comprising plural such cells-connected in an array.

Multiple time programmable (MTP) memorycells formed from cantilevers are being developed. Such devices have advantages when compared to traditional semiconductor-based memory cells in that they can operate as non-volatile memories without the need for a supporting power supply and in that they can be read without the need for large amounts of power.

However, such devices also have disadvantages in that control of their programming can -be complicated. Such control can be-complicated because of the inevitable time delay during programming whilst the cantilever moves from one state to another, such delay leading to the possibility of large currents passing through the cantilever and effectively wielding it in its contacted state such that further movement and programming is not possible and the cell is -essentially destroyed.

The present invention -seeks to provide an arrangement which prevents such "welding" and which assures reliable operation. In addition, it seeks to provide a*cell which enables fast switching of the cantilever by ensuring that a full rail of voltage can be applied across the elements used to move the -cantilever.

According to the«present invention there is provided a memory cell-comprising: a cantilever moveable between a first position in which this is in contact with a contact pad and a second position and which is out of contact with the contact pad; a electromagnetic driving means for controllably driving the cantilever between its two positions; and

a transistor having its drain connected to the cantilever.

The transistor may be of the NMOS type. The cell is arranged such that, in use, a current can be passed through the NMOS transistor and Io the-cantilever to determine the position of the cantilever.

The present invention also provides a memory array comprising an array of cells of the above type. By employment of a NMOS transistor attached to the cantilever it is possible to provide a memory .cell which has four terminals, two associated with driving the cantilever and two associated with reading it, by employment of the NMOS transistor the cell is capable of being read with very low voltage inputs and hence low current flows to prevent inadvertent welding of the -cantilever to the contact and hence destruction of the cells. It also enables a construction in which no resistive components are provided across the drive components, meaning that a full voltage can be applied to the cantilever to ensure rapid and reliable switching.

When the memory cell is joined to others in an array it also enableS'Simple and effective control of the array to enable the erasing of all -cells and the -selective programming and reading of each individual cell without affecting the storage -state of other cells in the array. The use of the transistor connected to thecantilever combined with the operation control such that the signals are applied to their respective lines limits the amount of current that flows when the cantilever is reador programmed. Furthermore, with the transistor on the cantilever, the charge islimited to the cantilever which has a small capacitance. With prior art arrangements there is a risk that the-charge on a whole line may be shorted through the cantilever contact

One example of the present invention will now be described with reference to the accompanying drawings, in which:

Figure 1 is a schematic diagram showing a cantilever memory cell;

Figure 2 is a 'state diagram showing the logic state for the terminals of the cell of Figure 1 during both erase and program operations; and

Figure 3 is a schematic diagram showing a memory array comprising four cells in accordance with the present invention.

Referring to Figure 1 , a memory cell 1 comprises a conductive-cantilever 2 which is moveable between a first position (as shown) out of contact with an electrical contact 3 and a second position {not shown) in contact with that contact 3. The cantilever 2 is driven between the two states by application of appropriate electrical potentials on a pull up electrode 4 and pull down electrode 5.

To prevent the cantilever from attaching tho the pull up«e|ectrode 4 an oxide layer 6 is formed between the pull up electrode 4 and the cantilever 2. The cantilever 2 may be biassed towards its non-contacting position, or may -be held there by application of appropriate electrical potentials to the pull up electrode 4 and pull down electrode 5. It may be retained in its contacting position again through application of appropriate potentials or through mechanical stiction to the-contact 3.

The memory cell operates as a memory by detection of the position of the cantilever 2 by attempting to pass a current from a cantilever terminal 10-to a contact terminal 11. If a current passes through it is determined that the cantilever is in its contacted position. The position of the cantilevercan therefore be used to represent a logical "1" or logical "0" in order to store data.

As mentioned above, such devices can have problems itexcessive current passes through the cantilever 2 when in its incontact position. ^Excessive current can effectively melt either the contact 3 or cantilever 2 such that they weld together to prevent further movement of the cantilever 2.

Figure 2 shows the logical commands for driving the memory cell 1 between "an erased state and a programmed state. "PU" represents pull upelectrode 4, "PD" represents pull down electrode 5, "CAN" represents cantilever-terminal 10 and "CON" represents contact terminal 11. The symbol "S" represents when two of tire terminals are of the same logical value "X" indicates that the logical value of the relevant terminal is not important. S and OP_PU represents two of the terminals being of the same value but of opposite value to the pull up terminal 4, and S and OP_PD represents when two terminals of the cell 1 are of the=same and opposite values to the pull down terminal 5. As mentioned above, during programming the potential at terminals 10 and 11 should be the same to prevent any possibility of welding.

Figure 3 shows an array of cells according to the present invention, Each cell has all of the components of the cell of figure 1 , but has attached to the cantilever terminal 10 the drain or source of an NMOS transistor 12. The cells 1 of the memory device are arranged as an array in rows and columns, and whilst in the example shown there are four memory cells, it will be appreciated that the memory device may have a far greater number. In the example shown in figure 3 thecells are arranged such that the pull up terminals 4 ofeachcell 1 in a row are connected to a common driving rail€R. Likewise, each pull down terminal 5 of-each-eell 1 of a row are connected to a common rail PD. In addition, the^ate of«each NMOS transistor 12 associated with -each cell 1 of each row is connected via a common rail WL.

The input of each NMOS transistor 12 in each column is connected via a common rail PBL and the contact terminal row 11 of each memorycell 1 in each column is connected via common rail VG. The provision of an NMOS transistor 12 associated with each cell ensures that an appropriate level of control can -be provided to the potential across the terminals 10, 11 of each cell 1 so that inadvertent welding of the cantilever of each cell cannot occur -either during an erase or programming operation. The provision of the NMOS transistor 12 also provides appropriate isolation to cells which are not being read to ensure that reading of other cells does not cause any damage and also to-ensure inadvertent programming of cells when others in the array are being .erased, programmed or read. How this is achieved will be understood in more detail by consideration of the erasing, programming and reading procedures set out below.

Firstly, referring to an erasing procedure, it will be appreciated that there are times when it is necessary to erase the-content of individual memory cells, or, indeed, the whole memory device. For example, directly after manufacture of a device the state of individual cells 1 will not be known and it is preferable to set all to a common state prior to data programming. With the device shown in figure 3 this is possible as follows:

ER[0/1]=1->0

PD[0/1]=0->0

WL[0/1]=1->0

PBL[0/1]=0->0

VG[0/1]=0>0

The symbol-> denotes a transition from one logic level to another.

The ER signal is connected to PU and is logic 1. From the state diagram of figure 2, it will be appreciated that PD and CAN need to be the opposite value i.e. logic 0. The CAN net is connected to the NMOS transistors. Hence the NMOS must discharge the CAN nets to logic 0. This is accomplished by the control signal values of WL=1, and PBL=O. VG is given as donyt care because it has little effect on the pull up or down of the cantilever, hence it is logic 0.

This leads to the cantilever being pulled up to the ER (PU -electrode) net.

Due to the encapsulation oxide 6 the -cantilever does not make a conductive path, but sticks to the oxide cap 6 or simply dangles freely.

Thus all cells are erased and all CAN nets are logic ϋ, whilst the -controlling signals transit to logic 0. This leaves the cell electro-statically neutral, and no resultant force is on the cantilever.

When programming an individual -cell it is essential that no other^«cells change their state: cells already programmed remain programmed and -erased cells remain Erased. Thus to program a cell the state diagram says that the VU and the CAN net must be the same value, but be opposite to the PD net. This will lead to cells that are in the ERASED state being programmed, tout in the case when a cell is already in the PROGRAMMED state programming axell in the same row should not erase it.

Hence in the general case, the row that the cell to be programmed is in -must first be read to identify the state of that cell and the cells that are not to be programmed

If we assume we are going to programme cell 00 which is in the -ERASE state, we need to find what control signal should be applied assuming -cell 01 could in general be in the ERASE or PROGRAMME state. Cells 10 and 11 are in another row and their WL, ER and PD lines are at logic 0 hence their state cannot be altered if PBL or VG changes.

ER[0]=0->0

PD[O]=I ->0

WL[O]=I ->0

PBL[0]=0->0

VG[0]=0->0

With reference to the state diagram of figure 2 cell OO will be programmed and its cantilever will be pulled down to make contact with the CON net. This is due to the selection of row 0 by ER[O)=U, PD[O]=I and WL[O]=I . From the-state diagram itcan be seen that all cells in this row will be programmed if their CAN nets are at the same logic level as ER[O] (which is PU). Those that have their CAN nets at the -same 'logic level as PD will not be programmed, This is why the row to be programmed musttirst be read so that the cell's state is found and so allow the correct CAN logic level to be applied. For cells in row 0 that are not to be programmed and are in the ERASE state PBL must be 1 , if the cell is in the PROGRAMMED state PSL should be 0. The -CAN nets will then follow the PBL net since the NMOS in rowO is on (WL[O]=I).

To prevent welding of cell 00 net VG[O] is equal to the PBL[O] net. As a-safety precaution all VG nets are driven to follow their associated PBL nets during

Programming.

Any reading procedure must also follow the requirement that no othertϊell should have their state altered and also the added criteria that the reading of a cell should not destroy the cell's own state.

As mentioned above, due to the nature of the cantilever, it may be damaged if excessive current flows through it, or a high voltage is applied. The cantilever in contact with the CON net in the MTP cell may experience welding if currents are too high (either DC or fast discharging -of charge through it) hence a low voltage, pulsed current mode reading method can be implemented.

Since reading is via current mode detection, then the state of a cell {cell 00) is given if there is or is not a current flow, depending upon whether the cell has or has not been programmed.

Finally; the VG net is grounded during the cell read. Thus to read a -given cell, in this case cell 00, the following control signals will be applied.

ER[O] = 0 - >0

PD[O]= 0->0

WL[O] = 1->0

PBL[O) = low analogue voltage - > 0

VG[0]=0->0

The PLB[O] signal is no lonqer a digital signal but an analog one. This constraint will typically be that PBL[O] will only be at a value such that only a voltage of between 0.1 and 0.3V should be across the -cantilever. The current will be dictated by the -cantilever ys resistance, the NMOS drain source resistance and the PEL voltage.

Another merit of the above array structure is that during Programming or Erase the PU and PD electrodes 4,5 have the full rail voltage applied to them, i.e. there are no threshold voltage drops because of any NMOS access transistor or after components connected to them. Also that the VG and PBL lines follow-each other during programming to prevent welding.

Of course, for reading an assessment will be needed of how much current can be conducted through the cantilever and the contact CON to prevent welding and

constraints to any current mode sense amplifier and the IvIMOS transistor made accordingly depending upon the physical characteristics of the cantilever.

Claims

1. A memory cell comprising:

a cantilever moveable between a first position in which this is in contact with a contact pad and a second position and which is out of contact with the -contact pad;

a electromagnetic driving means for controllably driving the cantilever between its two positions; and

a transistor having its drain connected to the cantilever.

2. A memory cell according to claim 1 , wherein the transistor is an NMOS transistor

3. A memory array comprising plural cells according to claim 1 or claim 2.

4. A memory array according -to claim 3, wherein the cells are arranged in a series of rows and columns and arranged such that -each respective part of the electro-magnetic driving means of each -cell in a row is connected to a«common rail, the gate of each transistor of«ach«cell in a given row is connected to a common rail;

each source or each drain of each transistor of«each<cell in a given column is connected to a common rail; and

a cantilever contact is provided for -each cell and each cantilever contact for each cell in a given column is -connected to a common rail.

5. A memory array according to claim 4, further comprising-control means for applying drive signals to the rails at predetermined timings such that the -current through the cantilever is minimised.