CN117636959A

CN117636959A - Driving circuit, memory device and operation method thereof

Info

Publication number: CN117636959A
Application number: CN202311595907.2A
Authority: CN
Inventors: 潘立阳; 梁英真; 高滨
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2023-11-27
Filing date: 2023-11-27
Publication date: 2024-03-01

Abstract

A driving circuit, a memory device and an operating method thereof are provided. The driving circuit comprises a first control circuit, a current limiting circuit and a second control circuit which are coupled, wherein when the working mode of the driving circuit is a self-stopping mode, the first control circuit is configured to be started according to a first control signal so as to transmit the current limiting voltage on a current limiting operation signal line to the current limiting circuit; the current limiting circuit is configured to be turned on according to a current limiting voltage to apply a first operation signal to a load signal line connected to an output terminal of the driving circuit; the second control circuit is configured to be turned on according to the second control signal to transmit the second operation signal to the current limiting circuit, and to control the current limiting circuit to stop applying the first operation signal to the load signal line according to the second operation signal and the feedback signal from the load signal line. The drive circuit can realize the function of automatic stop drive, can reduce the voltage drop on a bus, and can avoid continuous application of operation voltage on a load, thereby obviously reducing power consumption.

Description

Driving circuit, memory device and operation method thereof

Technical Field

Embodiments of the present disclosure relate to a driving circuit, a memory device and an operating method thereof.

Background

The resistive random access memory (Resistive Random Access Memory, RRAM) is a nonvolatile memory device which can adjust the conductivity state by applying external excitation, can record and store data information based on resistance change, and has the characteristics of high speed, low power consumption, small size and the like. Resistive random access memories have a good application prospect in the fields of artificial intelligence, neural networks, memories and the like, and have been increasingly focused by academia and industry.

Disclosure of Invention

At least one embodiment of the present disclosure provides a driving circuit including: the first control circuit is configured to be started according to a first control signal so as to transmit the current-limiting voltage on the current-limiting operation signal line to the current-limiting circuit when the working mode of the driving circuit is a self-stopping mode; the current limiting circuit is configured to be turned on according to the current limiting voltage so as to apply a first operation signal to a load signal line connected with an output end of the driving circuit; the second control circuit is configured to be turned on according to a second control signal to transmit a second operation signal to the current limiting circuit, and to control the current limiting circuit to stop applying the first operation signal to the load signal line according to the second operation signal and a feedback signal from the load signal line.

For example, in the driving circuit provided in at least one embodiment of the present disclosure, the operation mode of the driving circuit further includes an off mode and a current limiting mode, in the off mode, the first control circuit is configured to be turned on according to the first control signal, and transmit an off voltage on the current limiting operation signal line to the current limiting circuit to turn off the current limiting circuit; in the current limiting mode, the first control circuit is configured to be turned on according to the first control signal to transmit the current limiting voltage on the current limiting operation signal line to the current limiting circuit, the current limiting circuit is configured to limit the current on the load signal line to be not higher than a preset current according to the current limiting voltage, and the second control circuit is configured to be turned off according to the second control signal.

For example, in the driving circuit provided in at least one embodiment of the present disclosure, the current limiting circuit receives the first operation signal through a first operation signal line, the second control circuit receives the second operation signal through a second operation signal line, or the current limiting circuit and the second control circuit receive the first operation signal and the second operation signal through the same operation signal line, wherein voltages of the first operation signal and the second operation signal are the same.

For example, in the driving circuit provided in at least one embodiment of the present disclosure, the second control circuit includes a feedback switching circuit configured to be turned on or off according to the second control signal to turn on or off the second control circuit, and a sampling circuit configured to control the current limiting circuit to stop applying the first operation signal to the load signal line according to the feedback signal and the second operation signal when turned on.

For example, in the driving circuit provided in at least one embodiment of the present disclosure, the first control circuit includes a first switch component, the current limiting circuit includes a second transistor, the feedback switch circuit includes a third transistor, the sampling circuit includes a fourth transistor, and a first end of the first switch component is connected to a first voltage source through a current limiting operation signal line; the control electrode of the second transistor is connected with the second end of the first switch component, the first electrode of the second transistor is connected with a second voltage source to receive the first operation signal, and the second electrode of the second transistor is connected with the load signal line; the control electrode of the third transistor is connected with a third voltage source to receive the second control signal, the first electrode of the third transistor is connected with a fourth voltage source to receive the second operation signal, and the second electrode of the third transistor is connected with the first electrode of the fourth transistor; the control electrode of the fourth transistor is connected with the load signal line, the first electrode of the fourth transistor is connected with the second electrode of the third transistor to receive the second operation signal, and the second electrode of the fourth transistor is connected with the control electrode of the second transistor.

For example, in the driving circuit provided in at least one embodiment of the present disclosure, the first control circuit includes a first switch component, the current limiting circuit includes a second transistor, the feedback switch circuit includes a third transistor, the sampling circuit includes a fourth transistor, and a first end of the first switch component is connected to a first voltage source through a current limiting operation signal line; the control electrode of the second transistor is connected with the second end of the first switch component, the first electrode of the second transistor is connected with a second voltage source to receive the first operation signal, and the second electrode of the second transistor is connected with the load signal line; the control electrode of the third transistor is connected with a third voltage source to receive the second control signal, the first electrode of the third transistor is connected with the second electrode of the fourth transistor, and the second electrode of the third transistor is connected with the control electrode of the second transistor; the control electrode of the fourth transistor is connected with the load signal line, and the first electrode of the fourth transistor is connected with a fourth voltage source to receive the second operation signal.

For example, in the driving circuit provided in at least one embodiment of the present disclosure, the first switch component includes a first N-type transistor and a first P-type transistor, and the driving strengths of the first N-type transistor and/or the first P-type transistor and the fourth transistor jointly determine a threshold voltage for turning off the driving circuit; alternatively, the first switch component only comprises a first N-type transistor, and the driving strengths of the first N-type transistor and the fourth transistor jointly determine the threshold voltage for turning off the driving circuit; alternatively, the first switch component only comprises a first P-type transistor, and the driving strength of the first P-type transistor and the driving strength of the fourth transistor jointly determine the threshold voltage for turning off the driving circuit.

At least one embodiment of the present disclosure also provides a memory device including: one or more memory arrays, each of the memory arrays comprising one or more columns of memory cells and one or more bit lines respectively connected to the one or more columns of memory cells; the driving module comprises one or more driving circuits, each driving circuit comprises a first control circuit, a current limiting circuit and a second control circuit which are coupled, and when the working mode of the driving circuit is a self-stopping mode, the first control circuit is configured to be started according to a first control signal so as to transmit a current limiting voltage on a current limiting operation signal line to the current limiting circuit; the current limiting circuit is configured to be turned on according to the current limiting voltage to apply a first operation signal to a bit line connected to an output terminal of the driving circuit; the second control circuit is configured to be turned on according to a second control signal to transmit a second operation signal to the current limiting circuit, and to control the current limiting circuit to stop applying the first operation signal to the bit line according to the second operation signal and a feedback signal from the bit line.

For example, in the memory device provided in at least one embodiment of the present disclosure, the operation mode of the driving circuit further includes an off mode and a current limiting mode, in which the first control circuit is configured to be turned on according to the first control signal, and to transmit an off voltage on the current limiting operation signal line to the current limiting circuit to turn off the current limiting circuit; in the current limiting mode, the first control circuit is configured to be turned on according to the first control signal to transmit the current limiting voltage on the current limiting operation signal line to the current limiting circuit, the current limiting circuit is configured to limit the current on the bit line to be not higher than a preset current according to the current limiting voltage, and the second control circuit is configured to be turned off according to the second control signal.

For example, in the memory device provided in at least one embodiment of the present disclosure, the current limiting circuit receives the first operation signal through a first operation signal line, the second control circuit receives the second operation signal through a second operation signal line, or the current limiting circuit and the second control circuit receive the first operation signal and the second operation signal through the same operation signal line, wherein voltages of the first operation signal and the second operation signal are the same.

For example, in a memory device provided in at least one embodiment of the present disclosure, the second control circuit includes a feedback switch circuit configured to be turned on or off according to the second control signal to turn on or off the second control circuit, and a sampling circuit configured to control the current limiting circuit to stop applying the first operation signal to the bit line according to the feedback signal and the second operation signal when turned on.

For example, in the memory device provided in at least one embodiment of the present disclosure, the first control circuit includes a first switch component, the current limiting circuit includes a second transistor, the feedback switch circuit includes a third transistor, the sampling circuit includes a fourth transistor, and a first end of the first switch component is connected to a first voltage source through a current limiting operation signal line; the control electrode of the second transistor is connected with the second end of the first switch component, the first electrode of the second transistor is connected with a second voltage source to receive the first operation signal, and the second electrode of the second transistor is connected with the bit line; the control electrode of the third transistor is connected with a third voltage source to receive the second control signal, the first electrode of the third transistor is connected with a fourth voltage source to receive the second operation signal, and the second electrode of the third transistor is connected with the first electrode of the fourth transistor; the control electrode of the fourth transistor is connected with the bit line, the first electrode of the fourth transistor is connected with the second electrode of the third transistor to receive the second operation signal, and the second electrode of the fourth transistor is connected with the control electrode of the second transistor.

For example, in the memory device provided in at least one embodiment of the present disclosure, the first control circuit includes a first switch component, the current limiting circuit includes a second transistor, the feedback switch circuit includes a third transistor, the sampling circuit includes a fourth transistor, and a first end of the first switch component is connected to a first voltage source through a current limiting operation signal line; the control electrode of the second transistor is connected with the second end of the first switch component, the first electrode of the second transistor is connected with a second voltage source to receive the first operation signal, and the second electrode of the second transistor is connected with the bit line; the control electrode of the third transistor is connected with a third voltage source to receive the second control signal, the first electrode of the third transistor is connected with the second electrode of the fourth transistor, and the second electrode of the third transistor is connected with the control electrode of the second transistor; the control electrode of the fourth transistor is connected with the bit line, and the first electrode of the fourth transistor is connected with a fourth voltage source to receive the second operation signal.

For example, in a memory device provided in at least one embodiment of the present disclosure, the first switch component includes a first N-type transistor and a first P-type transistor, and drive strengths of the first N-type transistor and the fourth transistor jointly determine a threshold voltage for turning off the driving circuit; alternatively, the first switch component only comprises a first N-type transistor, and the driving strengths of the first N-type transistor and/or the first P-type transistor and the fourth transistor jointly determine the threshold voltage for turning off the driving circuit; alternatively, the first switch component only comprises a first P-type transistor, and the driving strength of the first P-type transistor and the driving strength of the fourth transistor jointly determine the threshold voltage for turning off the driving circuit.

For example, in the memory device provided in at least one embodiment of the present disclosure, the output terminals of the one or more driving circuits are respectively connected to the one or more bit lines; or the output ends of the one or more driving circuits are connected with one or more selected bit lines through a column selection switch circuit; or the output ends of the one or more driving circuits are respectively connected with one or more bit lines of a selected memory array in the one or more memory arrays through an array selection switch circuit; alternatively, the output ends of the one or more driving circuits are respectively connected with one or more bit lines in the selected memory array through the array selection switch circuit and the column selection switch circuit.

At least one embodiment of the present disclosure also provides a method of operating a memory device, the method of operating comprising: in a self-stopping mode, turning on the one or more first control circuits in the driving module according to the first control signal to transmit a current limiting voltage on the current limiting operation signal line to the current limiting circuit of each driving circuit; turning on the current limiting circuit of each of the driving circuits according to the current limiting voltage, thereby applying the first operation signal to the memory cell connected to the bit line; turning on the second control circuit of each driving circuit according to the second control signal to transmit the second operation signal to the current limiting circuit of each driving circuit; and controlling the current limiting circuit to stop applying the first operation signal to the bit line according to the second operation signal and the feedback signal on the bit line through the second control circuit of each driving circuit.

For example, the operation method provided in at least one embodiment of the present disclosure further includes: in a turn-off mode, turning on the first control circuit according to the first control signal, and transmitting a turn-off voltage on the current-limiting operation signal line to the current-limiting circuit to turn off the current-limiting circuit; or in the current limiting mode, the first control circuit is started according to the first control signal so as to transmit the current limiting voltage on the current limiting operation signal line to the current limiting circuit, the current on the bit line is limited to be not higher than a preset current through the current limiting circuit according to the current limiting voltage, and the second control circuit is turned off according to the second control signal.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

FIG. 1 is a schematic diagram of an exemplary resistive memory device according to at least one embodiment of the present disclosure;

FIG. 2 is a schematic diagram of an exemplary memory cell according to at least one embodiment of the present disclosure;

FIG. 3A is a schematic block diagram of a driving circuit provided in at least one embodiment of the present disclosure;

fig. 3B-3D are schematic structural diagrams of an exemplary driving circuit according to at least one embodiment of the present disclosure;

FIG. 4 is a timing diagram of a driving circuit according to at least one embodiment of the present disclosure in different operation modes;

FIGS. 5A-5C are schematic structural diagrams of an exemplary memory device provided in accordance with at least one embodiment of the present disclosure; and

fig. 6A-6C are schematic structural diagrams of an exemplary memory device provided in at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

The present disclosure is illustrated by the following several specific examples. Detailed descriptions of known functions and known parts (elements) may be omitted for the sake of clarity and conciseness in the following description of the embodiments of the present disclosure. When any part (element) of an embodiment of the present disclosure appears in more than one drawing, the part (element) is denoted by the same or similar reference numeral in each drawing.

The resistive random access memory device is considered as a novel non-volatile memory with potential due to high reading and writing speed, simple structure and good compatibility with CMOS technology, and has been widely used in the fields of information storage, logic operation, neural network calculation and the like.

Fig. 1 shows a schematic structure of an exemplary resistive memory device. As shown in fig. 1, the resistive memory device R1 includes a resistive layer 111 and upper and lower electrodes 113 and 114 on both sides, and may further include a functional layer 112 in at least one example. The functional layer 112 is an optional layer, and can be added or not according to the optimization direction of the performance of the resistive memory device R1, and is designed accordingly. The resistive layer 111 may be, for example, a single layer including a single type of binary metal oxide (e.g., niO, alOx, etc.), graphene oxide, a multiple perovskite oxide (e.g., STO, SZO, PCMO, etc.), or may be a multilayer, such as any optional stack of the above materials, for example, a stack of TixN and AlOx.

The resistive memory device may store data based on a resistive switching characteristic. The resistance switching characteristics of the resistive memory device are related to the conductive filaments, and the conductive filaments inside the resistive memory device can be restored or broken by applying a Set (Set) voltage or a Reset (Reset) voltage between the upper and lower electrodes of the resistive memory device. When the conductive filaments are connected, the resistive memory device exhibits a low resistance state (Low Resistance State, LRS), which may be used, for example, to store data 0; when the conductive filaments break, the resistive memory device exhibits a high resistance state (High Resistance State, HRS), which may be used, for example, to store data 1.

For example, after forming a conductive filament inside the resistive memory device R1, the resistive memory device R1 has an operation threshold voltage. When the magnitude of the input voltage applied between the upper electrode 113 and the lower electrode 114 of the resistive memory device R1 is smaller than the operation threshold voltage of the resistive memory device R1, the resistance value (or the conductance value) of the resistive memory device R1 is not changed. In this case, the current stored value of the resistive memory device may be read by applying a read voltage to the resistive memory device. The current storage value of the resistive memory device may be, for example, a resistance value of the resistive memory device. The read voltage is less than an operating threshold voltage of the resistive switching memory device.

When the magnitude of the input voltage applied between the upper electrode 113 and the lower electrode 114 of the resistive memory device R1 is greater than the operation threshold voltage of the resistive memory device R1, the resistance value (or the conductance value) of the resistive memory device R1 may be changed according to the set voltage or the reset voltage applied between the upper electrode 113 and the lower electrode 114 of the resistive memory device R1. For example, the set voltage is a positive voltage pulse, and the reset voltage is a negative voltage pulse. In the embodiments of the present disclosure, applying the set voltage to the resistive memory device is referred to as a set operation, applying the reset voltage to the resistive memory device is referred to as a reset operation, and one set operation or reset operation may be used as one write operation.

The structure of the memory cell and the write operation are described in detail below with reference to fig. 2.

Fig. 2 shows a schematic diagram of an exemplary memory cell. The memory cell includes a transistor M1 and a resistive memory device R1. For example, when the transistor M1 is an N-type transistor, the gate thereof is connected to the word line WL, for example, the transistor M1 is turned on when the word line WL inputs a high level; the first pole of the transistor M1 may be a source and configured to be connected to the source line SL, e.g., the transistor M1 may receive a reset voltage through the source line SL; the second pole of the transistor M1 may be a drain and configured to be connected to the second pole (e.g., a negative pole) of the resistive memory device R1, the first pole (e.g., a positive pole) of the resistive memory device R1 is connected to the bit line BL, and the resistive memory device R1 may receive a set voltage through the bit line BL, for example. For example, when the transistor M1 adopts a P-type transistor, the gate thereof is connected to the word line WL, for example, the transistor M1 is turned on when the word line WL inputs a low level; the first pole of the transistor M1 may be a source and configured to be connected to the source line SL, e.g., the transistor M1 may receive a reset voltage through the source line SL; the second pole of the transistor M1 may be a drain and configured to be connected to the second pole (e.g., a negative pole) of the resistive memory device R1, the first pole (e.g., a positive pole) of the resistive memory device R1 is connected to the bit line BL, and the resistive memory device R1 may receive a set voltage through the bit line BL, for example. It should be noted that the structure of the memory cell may also be implemented as other structures, for example, a structure in which the second pole of the resistive memory device R1 is connected to the source line SL, which is not limited by the embodiment of the present disclosure.

Taking an N-type transistor as an example for M1, the word line WL is used to apply a corresponding voltage to the gate of the transistor M1, thereby controlling the transistor M1 to be turned on or off. In the case of performing a write operation to the resistive memory device R1, for example, a set operation or a reset operation, the transistor M1 needs to be turned on first, that is, an on voltage needs to be applied to the gate of the transistor M1 through the word line WL. After the transistor M1 is turned on, for example, a voltage may be applied to the resistive memory device R1 at the source line SL and the bit line BL to change the resistive state of the resistive memory device R1. For example, a set voltage may be applied through the bit line BL to make the resistive memory device R1 in a low resistance state; for another example, a reset voltage may be applied through the source line SL to make the resistive memory device R1 in a high resistance state. For example, the high resistance state has a resistance value that is one hundred times or more, for example, one thousand times or more, than the low resistance state.

Embodiments of the present disclosure are not limited to the type, structure, etc. of the memory cell, and the structure of the memory cell may be 1T1R (including one transistor and one resistive memory device), 2T2R (including two transistors and two resistive memory devices), or other possible structures. It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors (e.g., MOS field effect transistors) or other switching devices with the same characteristics. The source and drain of the transistor used herein may be symmetrical in structure, so that the source and drain may be indistinguishable in structure. Embodiments of the present disclosure are not limited in the type of transistor employed.

Since there is no conductive filament inside the resistive memory device when the fabrication of the resistive memory device is completed, the resistive memory device needs to undergo an additional initialization (Forming) process to obtain the resistive switching characteristics, compared to other types of memories. The initialization process is to apply a relatively high voltage pulse across the two poles of the resistive memory device, thereby inducing the formation of conductive filaments within the resistive memory device. After forming the conductive filament inside the resistive memory device, the resistive memory device may become low resistance at a set voltage or high resistance at a reset voltage.

Since the initialization operation and the set operation are both operations to change the resistance value of the resistance-change memory device from a high resistance value to a low resistance value, the initialization operation and the set operation are collectively referred to as "low resistance operation" in the embodiments of the present disclosure.

The low resistance operation requires applying a relatively high voltage pulse to the resistive memory devices, and the pulse time required for each resistive memory device to complete the low resistance operation is not necessarily the same because the resistive memory devices themselves are relatively different. If the pulse voltage is applied to each of the resistive memory devices for the same time, a failure of lowering the resistance of a part of the resistive memory devices may be caused, thereby affecting the performance of the memory cell. Therefore, after the low resistance operation is performed on the resistive memory device, it is also generally necessary to perform a plurality of verify operations on the resistive memory device to check whether the resistive memory device has been successfully lowered in resistance.

The verifying operation refers to acquiring a resistance value of the resistive memory device after the initialization or set voltage is applied through a read operation, and checking whether the resistance value of the resistive memory device reaches a target resistance value. For example, after an initializing voltage pulse of a preset time and a preset amplitude is applied to a resistive memory device, a read voltage is required to be applied to read the current resistance value of the resistive memory device, if the current resistance value of the resistive memory device does not reach a target resistance value, which indicates that the resistive memory device has not completed a low resistance operation, the amplitude of the initializing voltage pulse is required to be changed, or the pulse time applied to the resistive memory device is required to be changed, and then the low resistance operation and the verification operation are performed again on the resistive memory device until it is determined that the resistive memory device is successfully lowered. After the resistance of one resistance change memory device is reduced, repeating the operation for the next resistance change memory device, and finally, successfully reducing the resistance of all the resistance change memory devices. However, multiple checks make the time for the low resistance process long, greatly increasing the time costs of production and testing.

An effective solution to the above problem is parallel low resistance. Parallel resistance reduction refers to applying the same voltage pulse to a plurality of resistance change memory devices in a row at the same time, the time of the voltage pulse being set long enough for any one of the resistance change memory devices to complete the resistance reduction. That is, the parallel low resistance reduces the total time for the low resistance operation of the plurality of resistance change memory devices as a whole by extending the time for a single low resistance operation. However, the parallel low-resistance operation cannot give consideration to the difference of the resistive memory devices, and the high current caused by the parallel low-resistance operation also provides new challenges for circuit design.

On the one hand, excessive current on the wiring leads to serious voltage Drop (IR Drop) problems, thereby limiting the number of resistive memory devices that can be subjected to parallel low resistance. Here, the voltage drop refers to that when a large current flows through a long wire due to the resistance of the wire, a voltage difference v=i×r exists between the proximal end and the distal end of the wire. The voltage drop problem can result in the voltage obtained by the resistive random access memory device at the far end of the wiring being far less than the preset low resistance voltage. For example, since word lines in memristor arrays tend to be long (in the order of millimeters), if the current for each column is reduced to tens of microamps, then when a thousand columns are simultaneously reduced, the current on the trace can reach tens of milliamperes, which can result in a very large voltage drop. The presence of the voltage drop causes the operating voltage of the resistive memory device at the far end of the trace to drop, which may result in the resistive memory device at the far end of the trace not being successfully low-resistance, and thus the number of columns operating in parallel in the memristor array is limited.

On the other hand, parallel low resistance may also degrade the performance of the resistive memory device. In parallel low resistance, in order to ensure that all resistance change memory devices can be successfully lowered in low resistance, the pulse time of the low resistance voltage needs to be set long to ensure a sufficient margin. However, during the period in which the low resistance voltage pulse continues, current may flow through the resistive memory device, and even if there is a current limiting protection measure, applying a high voltage to the resistive memory device for a long period of time may result in poor uniformity or excessively low resistance of the resistive memory device, so that the performance of the resistive memory device that is concurrently low-resistance tends to be inferior to that of the resistive memory device that is low-resistance one by one. In addition, the large current on the wiring for a long time also increases power consumption.

At least one embodiment of the present disclosure provides a driving circuit, a memory device and an operating method thereof. The driving circuit comprises a first control circuit, a current limiting circuit and a second control circuit which are coupled, wherein when the working mode of the driving circuit is a self-stopping mode, the first control circuit is configured to be started according to a first control signal so as to transmit the current limiting voltage on a current limiting operation signal line to the current limiting circuit; the current limiting circuit is configured to be turned on according to a current limiting voltage to apply a first operation signal to a load signal line connected to an output terminal of the driving circuit; the second control circuit is configured to be turned on according to the second control signal to transmit the second operation signal to the current limiting circuit, and to control the current limiting circuit to stop applying the first operation signal to the load signal line according to the second operation signal and the feedback signal from the load signal line.

The driving circuit provided by the embodiment of the disclosure can automatically close the current limiting circuit according to the feedback signal of the output end, and realize the function of automatic stop driving, so that the voltage of the output end can be effectively controlled, the resistance value of the load on the load signal line is controlled, the continuous application of the operation voltage on the load can be avoided, and the power consumption is obviously reduced.

Embodiments of the present disclosure will be described in detail below with reference to the attached drawings, but the present disclosure is not limited to these specific embodiments.

Fig. 3A is a schematic block diagram of a driving circuit provided in at least one embodiment of the present disclosure. As shown in fig. 3A, the driving circuit 31 provided in at least one embodiment of the present disclosure includes a first control circuit, a current limiting circuit, and a second control circuit coupled.

For example, the first control circuit receives a first control signal and a current limit operation signal. The first control signal is a signal for controlling the on state of the first control circuit, for example, when the first control signal is at a low level, the first control circuit is turned on; when the first control signal is at a high level, the first control circuit is turned off. For example, the first control signal may also be used to determine a threshold voltage at which the drive circuit self-stops.

For example, the first control circuit is coupled to the current limiting circuit, and after the first control circuit is turned on, the current limiting operation signal can be applied to the current limiting circuit, and the current limiting circuit is turned on and starts working under the control of the current limiting operation signal, so that the first operation signal is transmitted to the load signal line, and the first operation signal is a driving voltage signal required to be applied to the load. For example, the current limiting circuit is turned on when the current limiting operation signal transmitted on the current limiting operation signal line is a current limiting voltage, and is turned off when the current limiting operation signal transmitted on the current limiting operation signal line is a turn-off voltage. For example, the load signal line is connected to the output terminal of the driving circuit 31 and also connected to the second control circuit of the driving circuit 31, thereby transmitting the feedback signal to the second control circuit.

For example, the second control circuit receives a second control signal and a second operation signal. The second control signal is a signal for controlling whether the second control circuit is turned on, for example, when the second control signal is at a low level, the second control circuit is turned on; when the second control signal is at a high level, the second control circuit is turned off.

For example, after the second control circuit is turned on, a feedback signal from the load signal line may be received, and the second operation signal may be applied to the current limiting circuit under the control of the feedback signal, thereby controlling the on state of the current limiting circuit. For example, the second control circuit turns off the current limiting circuit when the feedback signal reaches the threshold voltage. After the current limiting circuit is turned off, the first operation signal is stopped being applied to the load signal line, thereby realizing the function of self-stopping driving. This mode of operation may be referred to as a self-stopping mode of the drive circuit 31.

For example, the operation modes of the driving circuit 31 further include an off mode and a current limiting mode. At least one embodiment of the present disclosure may control the operating states of the first control circuit and the second control circuit according to the first control signal and the second control signal, respectively, so as to switch between different operating modes. For example, when voltage driving of the load is not required, the driving circuit 31 may be caused to enter an off mode; for example, when it is only necessary to control the current on the load signal line, the drive circuit 31 may be caused to enter a current limiting mode; for example, when it is necessary to automatically end driving of the load, the driving circuit 31 may be put into the self-stop mode; for example, the driving circuit 31 may be brought into the current limiting mode first and then into the self-stop mode under the control of the second control signal at a predefined time or for a desired time. For example, the first control circuit and the second control circuit may be turned on simultaneously, so that the driving circuit 31 is first put into the current limiting mode, and then can be automatically put into the automatic stop mode after the driving is finished. Therefore, the driving circuit provided by at least one embodiment of the present disclosure can realize the switching between different working modes at least through the first control signal and the second control signal, so as to fully satisfy various requirements of practical applications, and the circuit has a simple structure and is flexible and convenient to operate.

For example, in the off mode, the off voltage is transmitted to the current limiting operation signal line, so that the off voltage is transmitted to the current limiting circuit through the first control circuit (on state), and the current limiting circuit is turned off, at this time, the first operation signal cannot be applied to the load. For example, in the off mode, the second control circuit may be turned on by the second control signal, or the second control circuit may be turned off by the second control signal.

For example, in the current limiting mode, the current limiting voltage is transmitted to the current limiting operation signal line, so that the current limiting voltage is transmitted to the current limiting circuit through the first control circuit (on state), the current limiting circuit is turned on, and the current on the load signal line is limited to be not higher than the preset current according to the current limiting voltage. For example, the magnitude of the preset current can be determined according to actual requirements, and the magnitude of the preset current on the load signal line can also be controlled by adjusting the magnitude of the current-limiting voltage.

For example, if it is desired that the drive circuit only operates in the current limit mode and not enter the self-stop mode, the second control circuit may be turned off by the second control signal.

For example, in at least one embodiment of the present disclosure, the second control circuit includes a feedback switching circuit and a sampling circuit.

For example, the feedback switch circuit receives the second control signal and the second operation signal, and the feedback switch circuit is turned on or off according to the second control signal, for example, when the second control signal is at a low level, the feedback switch circuit is turned on; when the second control signal is at a high level, the feedback switch circuit is turned off.

For example, a feedback switching circuit is coupled with the sampling circuit. The sampling circuit samples a feedback signal from the load signal line and is turned on under control of the feedback signal, thereby applying a second operation signal to the sampling circuit, and the sampling circuit turns off the current limiting circuit when the feedback signal reaches a threshold voltage. After the current limiting circuit is closed, the application of the first operation signal to the load signal line is stopped, so that the function of automatic stop driving is realized.

Embodiments of the present disclosure do not limit the driving object (load) of the driving circuit, for example, the load may be a resistive switching device (e.g., a resistive switching memory device, etc.), and may also be other electronic devices, such as electronic devices based on semiconductor materials or other memory devices based on the resistive switching principle, such as a magnetoresistive memory, a phase change memory device, etc.

For example, in one example, when the load on the load signal line is a resistive device, as the resistance value of the resistive device changes from high to low, the voltage of the feedback signal changes from high to low, and in response to the voltage of the feedback signal decreasing to the threshold voltage, the sampling circuit automatically turns off the current limiting circuit, thereby stopping the pulse voltage from being continuously applied to the resistive device, and thus the resistance value of the resistive device does not change any more. For example, the threshold voltage is a voltage at which the resistive device reaches a target resistance value.

For convenience of description, a circuit configuration and an operation mode of the driving circuit will be described in detail below taking a load of the driving circuit as a resistive random access memory as an example.

Fig. 3B is a schematic diagram of an exemplary driving circuit 32 according to at least one embodiment of the present disclosure. As shown in fig. 3B, the driving circuit 32 includes a first control circuit, a current limiting circuit, a feedback switching circuit, and a sampling circuit.

For example, in one example of an embodiment of the present disclosure, the voltages of the first and second operation signals vfs_bl and vfs_fb are the same, e.g., are each provided by a second voltage source (not shown in the figures), or are provided by different voltage sources (not shown in the figures).

For example, the first control circuit of the driving circuit 32 includes a first switching element including a first N-type transistor t1_n and a first P-type transistor t1_p, the current limiting circuit of the driving circuit 32 includes a second transistor T2, the feedback switching circuit includes a third transistor T3, and the sampling circuit includes a fourth transistor T4.

The configuration of the functional circuits of the first control circuit, the current limiting circuit, the feedback switching circuit, the sampling circuit, and the like in the driving circuit 32 shown in fig. 3B is merely exemplary and not limiting, and each functional circuit may have a smaller or larger number of transistors, or have other types or configurations of switching components, as desired. For example, in some embodiments of the present disclosure, the first switching component may also be comprised of only one transistor, e.g., the first switching component may include only one N-type transistor or only one P-type transistor.

For example, a first terminal of the first switching assembly is connected to a first voltage source (not shown) through a current-limiting operation signal line to receive a current-limiting operation signal vsc_pg for turning on (or off) the second transistor (current-limiting tube) T2. For example, the current limiting voltage determines the saturation current of the second transistor T2, and the current limiting voltage may be used to limit the final resistance variation range of the resistive memory device connected to the load signal line (e.g., bit line BL).

For example, as shown in fig. 3B, the control electrode (e.g., gate) of the first N-type transistor t1_n receives the first control signal vsc_en, and the control electrode (e.g., gate) of the first P-type transistor t1_p receives the first control signal vsc_enb. For example, the first N-type transistor t1_n is turned on when the first control signal vsc_en is at a high level, and the first P-type transistor t1_p is turned on when the first control signal vsc_enb is at a low level. That is, the first control circuit may be turned on when the first control signal vsc_en is at a high level and/or the first control signal vsc_enb is at a low level, and may be turned off when the first control signal vsc_en is at a low level and the first control signal vsc_enb is at a high level.

In some embodiments of the present disclosure, the driving strength of the transistor in the first switching element and the driving strength of the fourth transistor T4 together determine the threshold voltage of the off driving circuit.

For example, in the driving circuit 32 shown in fig. 3B, when the first control circuit is controlled to be turned on by using only the first N-type transistor t1_n, the threshold voltage of the off driving circuit is commonly determined by the driving strengths of the first transistor t1_n and the fourth transistor T4; when the first control circuit is controlled to be turned on by only the first P-type transistor T1_P, the threshold voltage of the turn-off driving circuit is determined by the driving strength of the first P-type transistor T1_P and the driving strength of the fourth transistor T4; when the first control circuit is controlled to turn on by the first N-type transistor t1_n and the first P-type transistor t1_p, the threshold voltage of the turn-off driving circuit is determined by the driving strengths of the first N-type transistor t1_n, the first P-type transistor t1_p and the fourth transistor T4.

For example, in other embodiments of the present disclosure, the first switch component may include only N-type transistors or only P-type transistors. For example, when the first switch assembly only includes the first N-type transistor, the threshold voltage of the turn-off driving circuit is determined by the driving strengths of the first N-type transistor and the fourth transistor; when the first switch assembly only comprises the first P-type transistor, the threshold voltage of the closed drive circuit is determined by the drive strength of the first P-type transistor and the fourth transistor.

A control electrode (e.g., a gate) of the second transistor T2 is connected to the second terminal of the first switching element, the first electrode of the second transistor T2 is connected to the second voltage source to receive the first operation signal vfs_bl, and the second electrode of the second transistor T2 is connected to the load signal line (e.g., bit line BL).

A control electrode (e.g., a gate) of the third transistor T3 is connected to a third voltage source (not shown) for receiving the second control signal vscfb_enb, a first electrode of the third transistor T3 is connected to a fourth voltage source for receiving the second operation signal vfs_fb, and a second electrode of the third transistor T3 is connected to a first electrode of the fourth transistor T4.

The control electrode of the fourth transistor T4 is connected to the load signal line (e.g., bit line BL) to receive the feedback signal from the bit line BL, the first electrode of the fourth transistor T4 is connected to the second electrode of the third transistor T3 to receive the second operation signal vfs_fb, and the second electrode of the fourth transistor T4 is connected to the control electrode of the second transistor T2.

For example, in the above example, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all P-type transistors.

For example, at least one embodiment of the present disclosure provides a driving circuit having three modes of operation: an off mode, a current limiting mode, and a self-stopping mode.

As shown in fig. 4, in the off mode, for example, the first control signal vsc_enb is low (e.g., vsc_enb=0), the first control signal vsc_en is low (e.g., vsc_en=0), and thus the first control circuit is turned on, i.e., the first P-type transistor t1_p transmits the current limiting operation signal vsc_pg to the gate of the second transistor T2. In the off mode, the off voltage is transmitted on the current limiting operation signal line, in this example, the off voltage is at a high level (for example, vsc_pg=vddh, and VDDH > vfs_bl- |vthp|, VTHP is the gate-source voltage at which the second transistor T2 is turned on), and thus the second transistor T2 is turned off, i.e., the current limiting circuit is not turned on, thereby cutting off the connection of the first operation signal vfs_bl to the bit line BL, at which time the driving circuit 32 does not operate. For example, in the off mode, the second control signal vscfb_enb may be low (e.g., vscfb_enb=0) to turn on the third transistor T3, or the second control signal vscfb_enb may be high (e.g., vscfb_enb=vddh) to turn off the third transistor T3.

For example, in the current limiting mode, for example, the first control signal vsc_enb is at a high level (e.g., vsc_enb=vddh), the first control signal vsc_en is at a high level (e.g., vsc_en=vddh), and thus the first control circuit is turned on, that is, the first N-type transistor t1_n transmits the current limiting operation signal to the gate of the second transistor T2. In the current limiting mode, a current limiting voltage is transmitted on a current limiting operation signal line, and the size of the current limiting voltage can be determined according to a target resistance value which needs to be achieved by the resistance change memory device. After the current-limiting voltage is transmitted to the gate of the second transistor T2 by the first N-type transistor t1_n, the second transistor T2 is turned on, and the second transistor T2 transmits the first operating signal vfs_bl to the bit line BL.

For example, in the current limiting mode, the first operation signal vfs_bl is a low-resistance operation voltage, that is, the first operation signal vfs_bl may be an initialization voltage for initializing the resistive memory device or a set voltage for setting the resistive memory device. For example, in the current limit mode, the second control signal vsfb_enb is high (e.g., vsfb_enb=vddh), thereby turning off the third transistor T3. Since the third transistor T3 is turned off, and thus the feedback branch is turned off, the feedback switching circuit and the sampling circuit do not perform feedback, the resistance of the resistive memory device gradually decreases as the low resistance operation proceeds, the voltage on the bit line BL also decreases, the second transistor T2 enters the saturation region, the saturation current is maintained stable, and the voltage on the bit line BL is substantially stabilized at a fixed value due to the limitation of the saturation current. As shown in fig. 4, in the current limiting mode, the voltage on BL gradually decreases, current I _R Gradually increases, after a period of time, the voltage and current I at BL _R Are limited to fixed values.

For example, in the self-stop mode, the first control signal vsc_enb is at a high level (e.g., vsc_enb=vddh), the first control signal vsc_en is at a high level voltage capable of adjusting the feedback intensity, and thus the first control circuit is turned on, i.e., the first N-type transistor t1_n transmits the current limiting operation signal to the gate of the second transistor T2. In the self-stop mode, the current-limiting operation signal vsc_pg may still be kept at the current-limiting voltage, but the second control signal vsfb_enb is at a low level (e.g., vsfb_enb=0), so that the third transistor T3 is turned on, whereby the feedback branch is opened, and the sampling circuit receives the second operation signal vfs_fb.

For example, in the self-stop mode, the first and second operation signals vfs_bl and vfs_fb are low-resistance operation voltages, that is, the first operation signal vfs_bl may be an initialization voltage for initializing the resistive memory device or a set voltage for setting the resistive memory device.

For example, during the low resistance operation, since the second transistor T2 in the initial state is in the on state, the resistance value of the resistive memory device is large, the second transistor T2 is in the linear region, the first operation signal vfs_bl is transmitted to the bit line BL almost without damage, and the fourth transistor T4 is in the off state. As the resistance of the resistive memory device is gradually reduced by the high voltage applied to the bit line BL, the voltage on the bit line BL is also gradually reduced as the resistance of the resistive memory device is reduced. As the voltage on the bit line BL gradually decreases, i.e., the voltage of the feedback signal gradually decreases, the fourth transistor T4 gradually turns on, and then the gate-source voltage of the fourth transistor T4 continuously increases, the pull-up capability of the fourth transistor T4 gradually increases, so that the voltage at the node VP slowly increases. When the voltage of the feedback signal on the bit line BL decreases to the threshold voltage, the voltage at the node VP increases to VFS_BL- |VTHP|, which is the gate-source voltage at which the second transistor T2 is turned on. That is, the voltage at the node VP reaches the off threshold voltage of the second transistor T2, and the second transistor T2 enters the off state, thereby stopping the application of the first operation signal vfs_bl to the resistance change memory device connected to the bit line BL. Finally, the bit line BL is rapidly discharged to 0, and the low resistance operation of the resistance change memory device is ended.

For example, in at least one embodiment of the present disclosure, the operating voltage ranges of the signals of the first operating signal vfs_bl, the current limiting operating signal vsc_pg, and the first control signal vsc_en may depend on different semiconductor processes, and the operating voltage ranges of the signals are not limited by the embodiments of the present disclosure. For example, at a process node of 28nm, for example, when initializing the resistive memory device, the typical operating voltage range of the first operating signal vfs_bl is 1V to 5V, the typical operating voltage range of the current limiting operating signal vsc_pg is 0V to 4V, and the typical operating voltage range of the first control signal vsc_en is 0V to 5V. For example, at a process node of 28nm, for example, in the case of performing a set operation on a resistive memory device, a typical operating voltage range of the first operating signal vfs_bl is 0.8V to 4V, a typical operating voltage range of the current limiting operating signal vsc_pg is 0 to 3V, and a typical operating voltage range of the first control signal vsc_en is 0 to 3V.

For example, in at least one embodiment of the present disclosure, in the off mode, the current limiting mode, and the self-stopping mode, only the first N-type transistor t1_n may be selected to be turned on, or only the first P-type transistor t1_p may be selected to be turned on, or the first N-type transistor t1_n and the first P-type transistor t1_p may be selected to be turned on simultaneously, so that the control manner is flexible and various.

For example, in at least one embodiment of the present disclosure, when the low resistance operation is performed on the resistive memory device using the driving circuit, the low resistance operation may be selected to be performed on the resistive memory device only by the current limiting mode, or the low resistance operation may be selected to be performed on the resistive memory device only by the self-stop mode, and the low resistance operation may be selected to be performed on the resistive memory device by first turning on the current limiting mode and then turning on the self-stop mode (as shown in fig. 4). It should be noted that, when the resistive memory device is operated with low resistance only in the self-stop mode, the driving circuit will immediately turn off the current limiting circuit in response to the voltage (feedback signal) on the BL reaching the threshold voltage.

For example, in at least one embodiment of the present disclosure, the current limiting circuit receives a first operation signal through a first operation signal line, and the second control circuit receives a second operation signal through a second operation signal line.

For example, as shown in fig. 3B, the driving circuit 32 further includes a first operation signal line VFS1 and a second operation signal line VFS2, the first operation signal line VFS1 being connected to the current limiting circuit (second transistor T2) to supply the first operation signal vfs_bl to the current limiting circuit, the second operation signal line VFS2 being connected to the feedback switching circuit (third transistor T3) to supply the second operation signal vfs_fb to the sampling circuit (fourth transistor T4).

For example, in the above example, the first pole of the second transistor T2 is connected to the second voltage source through the first operation signal line VFS1 to receive the first operation signal vfs_bl, and the first pole of the third transistor T3 is connected to the fourth voltage source through the second operation signal line VFS2 to receive the second operation signal vfs_fb, and the voltages of the first operation signal vfs_bl and the second operation signal vfs_fb are the same. When the feedback switch circuit (third transistor T3) is turned on, there is a current branch from vfs_fb to the third transistor T3, fourth transistor T4, first P-type transistor t1_p and first N-type transistor t1_n to vsc_pg, which has a small current, for example, less than 50 nanoamperes (nA), and since the first operation signal line VFS1 and the second operation signal line VFS2 are two separate wirings, current is not introduced into the second operation signal line VFS2, thereby reducing the voltage drop on the second operation signal line VFS2 when the resistive memory device is operated with low resistance.

In at least one embodiment of the present disclosure, as shown in fig. 3C, the current limiting circuit and the second control circuit receive the first operation signal and the second operation signal through the same operation signal line, and voltages of the first operation signal and the second operation signal are the same.

Fig. 3C is a schematic diagram of an exemplary driving circuit 32 according to at least one embodiment of the present disclosure. Other circuit structures of the driving circuit 33 shown in fig. 3C are the same as those of the driving circuit 32 shown in fig. 3B except for the number and connection manner of the operation signal lines, and detailed description of the circuit structure and the operation mode of the driving circuit 33 may be referred to the foregoing detailed description, and the repetition is omitted.

For example, as shown in fig. 3C, the first pole of the second transistor T2 is connected to the second voltage source through the operation signal line VFS to receive the first operation signal vfs_bl, and the first pole of the third transistor T3 is connected to the second voltage source through the operation signal line VFS to receive the second operation signal vfs_fb, and the voltages of the first operation signal vfs_bl and the second operation signal vfs_fb are the same. The second transistor T2 and the third transistor T3 receive the same operation voltage through the same operation signal line VFS, so that the number of wirings can be reduced, the area can be reduced, the complexity of circuit design can be reduced, and a large voltage drop can not be introduced because the current on the operation signal line VFS is small.

In at least one embodiment of the present disclosure, as shown in fig. 3D, the positions of the third transistor T3 and the fourth transistor T4 may be interchanged.

Fig. 3D is a schematic diagram of an exemplary driving circuit 34 according to at least one embodiment of the present disclosure. Except for the connection manner of the third transistor T3 and the fourth transistor T4, the other circuit structures of the driving circuit 34 shown in fig. 3D are the same as the circuit structures of the driving circuit 32 shown in fig. 3B, and the detailed description of the circuit structures and the operation modes of the driving circuit 34 may be referred to the foregoing detailed description, and the repetition is omitted.

For example, as shown in fig. 3D, the first pole of the second transistor T2 is connected to the second voltage source through the first operation signal line VFS1 to receive the first operation signal vfs_bl, and the first pole of the fourth transistor T4 is connected to the fourth voltage source through the second operation signal line VFS2 to receive the second operation signal vfs_fb, and the voltages of the first operation signal vfs_bl and the second operation signal vfs_fb are the same. The second pole of the fourth transistor T4 is connected to the first pole of the third transistor T3, and the control pole of the fourth transistor T4 is connected to the load signal line BL. The second pole of the third transistor T3 is connected to the control pole of the second transistor T2, and the control pole of the third transistor T3 is connected to a third voltage source for receiving the second control signal vsfb_enb.

As described above, parallel low resistance operation of a plurality of resistive memory devices in a memory array can reduce the verification operation, reduce the time cost of production and testing, but the parallel low resistance operation may cause serious voltage drop problem and may further affect the uniformity and reliability of the devices. In this regard, at least one embodiment of the present disclosure provides a memory device including one or more memory arrays and a driver module. According to the memory device, the driving circuit in the driving module is used for carrying out low-resistance operation on the resistance-change memory devices in the memory array, when the resistance of the resistance-change memory devices reaches a target resistance value, the process of reducing the resistance of the resistance-change memory devices can be automatically stopped, and the continuous application of the operation voltage to the resistance-change memory devices is stopped, so that the excessive reduction of the resistance-change memory devices is effectively prevented. In at least one example, the memory device can avoid the problem of voltage drop through parallel low-resistance operation of a plurality of resistance change memory devices by a plurality of driving circuits, improve the uniformity and reliability of the devices after the low-resistance operation, improve the low-resistance operation speed of the array, and reduce the power consumption.

For example, each memory array includes one or more columns of memory cells and one or more bit lines respectively connected to the one or more columns of memory cells. For example, the driving module includes one or more driving circuits, each driving circuit includes a first control circuit, a current limiting circuit and a second control circuit coupled, and in a self-stopping mode of operation of the driving circuit, the first control circuit is configured to be turned on according to a first control signal to transmit a current limiting voltage on a current limiting operation signal line to the current limiting circuit; the current limiting circuit is configured to be turned on according to the current limiting voltage to apply a first operation signal to a bit line connected to an output terminal of the driving circuit; the second control circuit is configured to be turned on according to the second control signal to transmit the second operation signal to the current limiting circuit, and to control the current limiting circuit to stop applying the first operation signal to the bit line according to the second operation signal and the feedback signal from the bit line.

For example, the memory cells in the memory array include at least one resistive memory device (or other memory based on the resistive switching principle) and at least one switching element, which may be, for example, the structure of the memory cell shown in fig. 2, and will not be described herein.

For example, in some embodiments of the present disclosure, a memory array includes a plurality of memory cells that form an array of N rows and M columns, where N and M are positive integers. For example, a memory array includes N rows of word lines, M columns of bit lines, and N rows of source lines, the control electrodes (e.g., gates of transistors) of the switching elements in the memory cells of each row are connected to the word line corresponding to the row, the memory in the memory cells of each column is connected to the bit line corresponding to the column, and the sources of the transistors in the memory cells of each row are connected to the source line corresponding to the row.

For example, the driving circuit may be the driving circuit 32 shown in fig. 3B, the driving circuit 33 shown in fig. 3C, or the driving circuit 34 shown in fig. 3D, and the detailed description of the driving circuit may be referred to the detailed description of the foregoing embodiments, and the repetition is omitted.

For example, after the low-resistance operation command starts, the resistance change memory cells of one row start to perform the low-resistance operation at the same time, and as the resistance value of the device decreases, the current on the wiring providing the low-resistance operation signal increases rapidly. The near end of the wiring has no voltage drop problem due to small wire resistance, the low-resistance operation speed is faster, the wire resistance of the far end of the wiring is large, the voltage drop problem is large, and the low-resistance operation speed is slow. When the resistance of the device at the near end of the wiring is low to a certain value, the low-resistance operation of the branch circuit is automatically stopped, the current is reduced to 0, and the total current on the wiring gradually decreases along with the increasing number of the turned-off branch circuits. Since the total current becomes smaller, the problem of voltage drop at the far end of the wiring is relieved, and the actual operation voltage of the device at the far end of the wiring can basically reach the voltage of the first operation signal, so that the resistive random access memory array can gradually complete low-resistance operation from the near end to the far end.

Fig. 5A-5C are schematic structural diagrams of an exemplary memory device provided in at least one embodiment of the present disclosure. As shown in fig. 5A to 5C, each driving circuit is connected to two separate operation signal lines. For example, the current limiting circuit in each driving circuit receives a first operation signal through the first operation signal line VFS1, and the second control circuit in each driving circuit receives a second operation signal through the second operation signal line VFS 2. Since the first operation signal line VFS1 and the second operation signal line VFS2 are separate two wirings, current is not drawn into the first operation signal line VFS1, thereby reducing a voltage drop on the first operation signal line VFS1 when the resistance change memory device is operated with low resistance.

Fig. 6A-6C are schematic structural diagrams of an exemplary memory device provided in at least one embodiment of the present disclosure. As shown in fig. 6A to 6C, each driving circuit shares one operation signal line VFS. For example, the current limiting circuit and the second control circuit in each driving circuit receive the first operation signal and the second operation signal through the same operation signal line, and the voltages of the first operation signal and the second operation signal are the same, so that the number of wires can be reduced, the area can be reduced, the complexity of circuit design can be reduced, and a large voltage drop can not be introduced because the current on the operation signal line VFS is small.

In some embodiments of the present disclosure, a memory device is provided in which the output terminals of one or more driving circuits are respectively connected to one or more bit lines. As shown in the memory device 51 of fig. 5A or the memory device 61 of fig. 6A, each of the memory device 51 and the memory device 61 includes only one memory array including m memory columns (memory column 0 to memory column m) corresponding to the bit lines BL0 to BLm, respectively, each of which is connected to one driving circuit.

For example, in some embodiments of the present disclosure, the output of one or more driver circuits is coupled to a selected one or more bit lines through a column select switch circuit. As shown in the memory device 52 of fig. 5B or the memory device 62 of fig. 6B, the memory array includes m×n memory columns (memory column 0 to memory column mn) corresponding to the bit lines BL0 to BLmn, respectively. For example, the column selection switch circuit may include a plurality of column selection switches, and the function of the column selection switch circuit is to select 1 column (or a plurality of columns) of bit lines from n columns of bit lines, for example, to be connected to the driving circuit. For example, in one example, n=3, each 3 bit lines in the memory array are connected to one column selection switch in the column selection switch circuit, and m bit lines are selected from 3m bit lines by m column selection switches of the column selection switch circuit, and are connected to m driving circuits in a one-to-one correspondence, for example, by load signal lines GBL0 to GBLm, respectively, when the memory array is subjected to the parallel low-resistance operation.

For example, in some embodiments of the present disclosure, the output of one or more driving circuits are respectively connected to one or more bit lines of a selected memory array of one or more memory arrays through an array selection switch circuit. As shown in memory device 53 of fig. 5C or memory device 63 of fig. 6C, the memory device may include n memory arrays 1-n, each including, for example, a plurality of rows and columns of memory cells, each including, for example, m columns of memory columns. For example, the array selection switch circuit includes a plurality of array selection switches, and the function of the array selection switch circuit is to select 1 memory array from n memory arrays, for example, and a plurality of bit lines in the selected memory array are connected to a plurality of driving circuits in one-to-one correspondence, respectively. For example, parallel low-resistance operation may be performed sequentially on the resistive memory devices in the memory arrays 1 to n.

The memory device may include any combination of block selection switch circuits, column selection switch circuits, or array selection switch circuits in the above-described embodiments, as embodiments of the present disclosure are not limited in this regard. For example, in one example, the memory device includes an array selection switch circuit and a column selection switch circuit through which outputs of one or more driver circuits are respectively connected to a selected one or more bit lines in a selected memory array.

At least one embodiment of the present disclosure further provides an operation method for the above memory device, including: in the automatic stop mode, one or more first control circuits in the driving module are started according to a first control signal so as to transmit the current limiting voltage on the current limiting operation signal line to the current limiting circuit of each driving circuit; turning on a current limiting circuit of each driving circuit according to the current limiting voltage, thereby applying a first operation signal to a memory cell connected to a bit line; turning on a second control circuit of each driving circuit according to the second control signal to transmit a second operation signal to a current limiting circuit of each driving circuit; the current limiting circuit is controlled by the second control circuit of each driving circuit to stop applying the first operation signal to the bit line according to the second operation signal and the feedback signal on the bit line.

For example, each driving circuit controls the current branch on one or more bit lines of the memory array, and by the self-stopping operation method of the driving circuit, the low-resistance operation process can be automatically stopped when the resistance of the resistance change memory device on each bit line falls below a certain value, the branch where the resistance change memory device is located is turned off, and the current on an operation signal line (bus) is reduced, so that the problem of voltage drop on the bus can be avoided, the uniformity and the reliability of the resistance change memory device after parallel operation are improved, the low-resistance operation speed of the array is improved, and the power consumption is reduced.

For example, in an operation method provided in at least one embodiment of the present disclosure, the first operation signal includes an initialization voltage or a set voltage for the memory cell.

For example, the operation method provided in at least one embodiment of the present disclosure further includes: in the off mode, the first control circuit is started according to the first control signal, and the off voltage on the current-limiting operation signal line is transmitted to the current-limiting circuit to close the current-limiting circuit; or in the current limiting mode, the first control circuit is started according to the first control signal so as to transmit the current limiting voltage on the current limiting operation signal line to the current limiting circuit, the current on the bit line is limited to be not higher than the preset current through the current limiting circuit according to the current limiting voltage, and the second control circuit is turned off according to the second control signal.

For example, in the off mode, the first control signals control the first control circuits of the driving circuits in the memory device to be in an on state, and the current limiting operation signals are, for example, high level to turn off the current limiting circuits to cut off the connection of the first operation signals to the bit lines BL (e.g., bit lines BL0 to BLm).

For example, in one example, when parallel low resistance operation is performed on memory cells of a memory array, the current limit mode is first turned on, and then the self-stop mode is turned on.

For example, in the current limiting mode, the first control signals control the first control circuits of the driving circuits in the memory device to be in an on state, the current limiting voltage is transmitted to the current limiting circuit through the first control circuits, and at this time, the current limiting circuit is turned on, so that the first operation signals are transmitted to the bit lines BL to perform parallel low-resistance operation on the resistive random access memory devices on the bit lines BL. For example, in performing an initialization operation on the memory array, the first operation signal is an initialization voltage, for example, 5V; in a set operation of the memory array, the first operation signal is a set voltage, for example, 3V.

For example, in the current limiting mode, the second control signal is, for example, at a high level, thereby turning off the plurality of second control circuits (or the feedback switch circuits shown in fig. 3B, 3C, or 3D) of the plurality of driving circuits in the memory device, and the sampling circuit in each driving circuit is thus turned off, resulting in the feedback branch being turned off, so that the feedback switch circuits and the sampling circuits do not exert feedback effects. As the low resistance operation proceeds, the resistances of the plurality of resistive memory devices in a row gradually decrease, and the voltage on the bit line BL decreases, and the voltage on the bit line BL is substantially stabilized at a fixed value by the limitation of the saturation current.

For example, when the self-stop mode is turned on, the second control signal is, for example, low level, so that the plurality of feedback switch circuits of the plurality of driving circuits in the memory device are turned on, whereby the plurality of feedback branches are turned on, and the sampling circuit in each driving circuit starts to receive the second operation signal. With the resistance value of the resistive random access memory device gradually decreasing due to the high voltage applied to the bit line BL, the voltage on the bit line BL also gradually decreases due to the decrease of the resistance value of the resistive random access memory device, the voltage of the feedback signal also gradually decreases, the pull-up capability of the sampling circuit gradually increases, and the current limiting circuit gradually enters an off state under the action of the second operation signal, so that the first operation signal is stopped from being continuously applied to a plurality of resistive random access memory devices connected with a plurality of bit lines BL. Finally, as the plurality of bit lines BL rapidly discharge to 0, the low resistance operation of all the resistance change memory devices ends. It should be noted that, because of the difference between the resistive random access memory devices, the time for completing the low resistance of the resistive random access memory devices on the bit lines BL is not necessarily the same, and after the current on the bit line BL where the resistive random access memory device is located after completing the low resistance becomes 0, the total current on the operation signal line is also reduced, and as the number of turned-off branches increases, the total current on the bus decreases, and the voltage drop problem is greatly alleviated.

While the disclosure has been described in detail with respect to the general description and the specific embodiments thereof, it will be apparent to those skilled in the art that certain modifications and improvements may be made thereto based on the embodiments of the disclosure. Accordingly, such modifications or improvements may be made without departing from the spirit of the disclosure and are intended to be within the scope of the disclosure as claimed.

For the purposes of this disclosure, the following points are also noted:

(1) The drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

(2) In the drawings for describing embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced for clarity, i.e., the drawings are not drawn to actual scale.

(3) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.

The foregoing is merely specific embodiments of the disclosure, but the scope of the disclosure is not limited thereto, and the scope of the disclosure should be determined by the claims.

Claims

1. A driving circuit, comprising: the first control circuit, the current limiting circuit and the second control circuit are coupled,

In the case where the operation mode of the driving circuit is a self-stop mode,

the first control circuit is configured to be turned on according to a first control signal so as to transmit a current-limiting voltage on a current-limiting operation signal line to the current-limiting circuit;

the current limiting circuit is configured to be turned on according to the current limiting voltage so as to apply a first operation signal to a load signal line connected with an output end of the driving circuit;

the second control circuit is configured to be turned on according to a second control signal to transmit a second operation signal to the current limiting circuit, and to control the current limiting circuit to stop applying the first operation signal to the load signal line according to the second operation signal and a feedback signal from the load signal line.

2. The drive circuit of claim 1, wherein the operating modes of the drive circuit further comprise an off mode and a current limiting mode,

in the off mode, the first control circuit is configured to be turned on according to the first control signal, and transmit an off voltage on the current limiting operation signal line to the current limiting circuit to turn off the current limiting circuit;

in the current limiting mode, the first control circuit is configured to be turned on according to the first control signal to transmit the current limiting voltage on the current limiting operation signal line to the current limiting circuit, the current limiting circuit is configured to limit the current on the load signal line to be not higher than a preset current according to the current limiting voltage, and the second control circuit is configured to be turned off according to the second control signal.

3. The drive circuit according to claim 1, wherein the current limiting circuit receives the first operation signal through a first operation signal line, the second control circuit receives the second operation signal through a second operation signal line,

or,

the current limiting circuit and the second control circuit receive the first operation signal and the second operation signal through the same operation signal line,

wherein the voltages of the first operation signal and the second operation signal are the same.

4. A driving circuit according to any one of claims 1 to 3, wherein the second control circuit comprises a feedback switching circuit and a sampling circuit,

the feedback switch circuit is configured to be turned on or off according to the second control signal to turn on or off the second control circuit,

the sampling circuit is configured to control the current limiting circuit to stop applying the first operation signal to the load signal line according to the feedback signal and the second operation signal when the sampling circuit is conducted.

5. The drive circuit of claim 4, wherein the first control circuit comprises a first switching component, the current limiting circuit comprises a second transistor, the feedback switching circuit comprises a third transistor, the sampling circuit comprises a fourth transistor,

The first end of the first switch component is connected with a first voltage source through a current limiting operation signal line;

the control electrode of the second transistor is connected with the second end of the first switch component, the first electrode of the second transistor is connected with a second voltage source to receive the first operation signal, and the second electrode of the second transistor is connected with the load signal line;

the control electrode of the third transistor is connected with a third voltage source to receive the second control signal, the first electrode of the third transistor is connected with a fourth voltage source to receive the second operation signal, and the second electrode of the third transistor is connected with the first electrode of the fourth transistor;

the control electrode of the fourth transistor is connected with the load signal line, the first electrode of the fourth transistor is connected with the second electrode of the third transistor to receive the second operation signal, and the second electrode of the fourth transistor is connected with the control electrode of the second transistor.

6. The drive circuit of claim 4, wherein the first control circuit comprises a first switching component, the current limiting circuit comprises a second transistor, the feedback switching circuit comprises a third transistor, the sampling circuit comprises a fourth transistor,

the control electrode of the third transistor is connected with a third voltage source to receive the second control signal, the first electrode of the third transistor is connected with the second electrode of the fourth transistor, and the second electrode of the third transistor is connected with the control electrode of the second transistor;

the control electrode of the fourth transistor is connected with the load signal line, and the first electrode of the fourth transistor is connected with a fourth voltage source to receive the second operation signal.

7. The drive circuit of claim 5 or 6, wherein the first switching element comprises a first N-type transistor and a first P-type transistor, the drive strengths of the first N-type transistor and/or the first P-type transistor and the fourth transistor together determining a threshold voltage for turning off the drive circuit; or,

The first switch component only comprises a first N-type transistor, and the driving strength of the first N-type transistor and the driving strength of the fourth transistor jointly determine the threshold voltage for turning off the driving circuit; or,

the first switch component only comprises a first P-type transistor, and the driving strength of the first P-type transistor and the driving strength of the fourth transistor jointly determine the threshold voltage for turning off the driving circuit.

8. A memory device, comprising:

one or more memory arrays, each of the memory arrays comprising one or more columns of memory cells and one or more bit lines respectively connected to the one or more columns of memory cells;

a driving module comprising one or more driving circuits, each driving circuit comprising a first control circuit, a current limiting circuit and a second control circuit which are coupled,

the current limiting circuit is configured to be turned on according to the current limiting voltage to apply a first operation signal to a bit line connected to an output terminal of the driving circuit;

The second control circuit is configured to be turned on according to a second control signal to transmit a second operation signal to the current limiting circuit, and to control the current limiting circuit to stop applying the first operation signal to the bit line according to the second operation signal and a feedback signal from the bit line.

9. The memory device of claim 8 wherein the operating modes of the drive circuit further comprise an off mode and a current limit mode,

in the current limiting mode, the first control circuit is configured to be turned on according to the first control signal to transmit the current limiting voltage on the current limiting operation signal line to the current limiting circuit, the current limiting circuit is configured to limit the current on the bit line to be not higher than a preset current according to the current limiting voltage, and the second control circuit is configured to be turned off according to the second control signal.

10. The memory device according to claim 8, wherein the current limiting circuit receives the first operation signal through a first operation signal line, the second control circuit receives the second operation signal through a second operation signal line,

Or,

11. The memory device of claim 8, wherein the second control circuit comprises a feedback switch circuit and a sampling circuit,

the sampling circuit is configured to control the current limiting circuit to stop applying the first operation signal to the bit line according to the feedback signal and the second operation signal when the sampling circuit is conducted.

12. The memory device of claim 11, wherein the first control circuit comprises a first switch component, the current limiting circuit comprises a second transistor, the feedback switch circuit comprises a third transistor, the sampling circuit comprises a fourth transistor,

the control electrode of the second transistor is connected with the second end of the first switch component, the first electrode of the second transistor is connected with a second voltage source to receive the first operation signal, and the second electrode of the second transistor is connected with the bit line;

the control electrode of the fourth transistor is connected with the bit line, the first electrode of the fourth transistor is connected with the second electrode of the third transistor to receive the second operation signal, and the second electrode of the fourth transistor is connected with the control electrode of the second transistor.

13. The memory device of claim 11, wherein the first control circuit comprises a first switch component, the current limiting circuit comprises a second transistor, the feedback switch circuit comprises a third transistor, the sampling circuit comprises a fourth transistor,

the control electrode of the fourth transistor is connected with the bit line, and the first electrode of the fourth transistor is connected with a fourth voltage source to receive the second operation signal.

14. The memory device of claim 12 or 13, wherein the first switching component comprises a first N-type transistor and a first P-type transistor, the drive strengths of the first N-type transistor and/or the first P-type transistor and the fourth transistor together determining a threshold voltage to turn off the drive circuit; or,

15. The memory device of any one of claims 8-13, wherein the output of the one or more driver circuits are respectively connected to the one or more bit lines; or,

the output ends of the one or more driving circuits are connected with one or more selected bit lines through a column selection switch circuit; or,

the output ends of the one or more driving circuits are respectively connected with one or more bit lines of a selected memory array in the one or more memory arrays through an array selection switch circuit; or,

the output ends of the one or more driving circuits are respectively connected with one or more bit lines selected in the selected memory array through the array selection switch circuit and the column selection switch circuit.

16. A method of operation of the memory device of claim 8, comprising:

in a self-stopping mode, turning on the one or more first control circuits in the driving module according to the first control signal to transmit a current limiting voltage on the current limiting operation signal line to the current limiting circuit of each driving circuit;

turning on the current limiting circuit of each of the driving circuits according to the current limiting voltage, thereby applying the first operation signal to the memory cell connected to the bit line;

Turning on the second control circuit of each driving circuit according to the second control signal to transmit the second operation signal to the current limiting circuit of each driving circuit;

and controlling the current limiting circuit to stop applying the first operation signal to the bit line according to the second operation signal and the feedback signal on the bit line through the second control circuit of each driving circuit.

17. The method of operation of claim 16, further comprising:

in a turn-off mode, turning on the first control circuit according to the first control signal, and transmitting a turn-off voltage on the current-limiting operation signal line to the current-limiting circuit to turn off the current-limiting circuit; or,

in the current limiting mode, the first control circuit is started according to the first control signal so as to transmit the current limiting voltage on the current limiting operation signal line to the current limiting circuit, the current on the bit line is limited to be not higher than a preset current through the current limiting circuit according to the current limiting voltage, and the second control circuit is turned off according to the second control signal.