WO2007060587A1 - Chiffrement et dechiffrement multvoie ultrarapide - Google Patents

Chiffrement et dechiffrement multvoie ultrarapide Download PDF

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Publication number
WO2007060587A1
WO2007060587A1 PCT/IB2006/054319 IB2006054319W WO2007060587A1 WO 2007060587 A1 WO2007060587 A1 WO 2007060587A1 IB 2006054319 W IB2006054319 W IB 2006054319W WO 2007060587 A1 WO2007060587 A1 WO 2007060587A1
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WO
WIPO (PCT)
Prior art keywords
cipher
key
stream
block
words
Prior art date
Application number
PCT/IB2006/054319
Other languages
English (en)
Inventor
Michael A. Epstein
James Ross Goodman
Original Assignee
Koninklijke Philips Electronics, N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Koninklijke Philips Electronics, N.V. filed Critical Koninklijke Philips Electronics, N.V.
Priority to JP2008541867A priority Critical patent/JP2009516976A/ja
Priority to EP06821487A priority patent/EP1955473A1/fr
Publication of WO2007060587A1 publication Critical patent/WO2007060587A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
    • H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
    • H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
    • H04L9/0662—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
    • H04L2209/125—Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations

Definitions

  • This application claims the benefit of U.S. Provisional Patent Application 60/739,219 filed 23 November 2005.
  • This invention relates to the field of communications and data security, and in particular to a method and system that facilitates high-speed multi-lane, parallel data channel, encryption and decryption.
  • a stream cipher is a cipher in which the input stream is encrypted sequentially, generally one data unit (word/byte/bit) at a time, and in which the transformation of subsequent data units varies during the encryption.
  • a block cipher is a cipher that operates on large blocks of data with a fixed, unvarying transformation. That is, a block cipher of a given block of data and a given encryption key will always produce the same encrypted output block.
  • a stream cipher's output is dependent upon the state of the cipher system at the time that the data unit is being encrypted.
  • a stream cipher combines the input stream with a generated keystream, the keystream being pseudorandomly generated based on a given encryption key, or set of keys. Because the sequential generation of a keystream is generally a less complex operation than the block-encryption of a data block, stream ciphers are typically substantially faster than block ciphers, and require substantially fewer hardware components.
  • Stream ciphers are particularly well suited for the high-speed encryption/decryption of streams of data of unknown length, such as telephone conversations, streaming video, and so on.
  • block ciphers When block ciphers are used on such data, the design must include provisions for padding input streams that terminate prior to filling a block.
  • Many stream ciphers are configured to produce a multi-bit output at each clock cycle.
  • the SNOW cipher, and it successor SNOW-2 by Ekdahl and Johansson of Lund University, for example, use a linear feedback shift register that drives a state machine that is configured to output a 32-bit word on each cycle.
  • parallel encryption is often used, wherein an input stream is demultiplexed into a data set that includes the same number of bits as the output cipher, the data set is encrypted using the multi-bit cipher, and then multiplexed into an output stream in the same form as the input stream.
  • the input stream comprises data bytes on an 8-bit wide bus, and a 32-bit cipher word is available, each set of four 8-bit bytes on the bus are spread into a 32-bit word, the 32-bit word is encrypted using the 32-bit cipher word, and the resultant 32-bit output word is de-spread into four output bytes corresponding to the encryption of the four input bytes.
  • the cipher generator can support a throughput rate of the input stream as high as four times the speed of the cipher generation.
  • the input data rate may be substantially less than the maximum speed that a particular cipher generator can support.
  • multiple data streams may be supported by a single cipher generator.
  • the speed of the 8-bit wide input data stream is twice the speed of the 32-bit cipher generator, two such 8- bit data streams can be supported by this 32-bit cipher generator; if the speed of the 8-bit wide input data stream is equal to the speed of the 32-bit cipher generator, four such input data streams can be supported by the cipher generator; and so on.
  • stream ciphers are less secure than block ciphers, in that they are more susceptible to distinguishing attacks that use less than an exhaustive search. Further, all stream ciphers are vulnerable to attack if the keystream is repeated.
  • the keystream's repeat-length is 2 128 bits, which is acceptable in most applications, but at an encryption rate of 100Mb per second, the recycle time of such a cipher amounts to under 25 minutes, which renders the cipher unsuitable for long-running applications, such as streaming video.
  • the complexity of block ciphers renders them either too costly or too slow for such consumer applications. It would be advantageous to provide a cipher that provides the speed of a stream cipher and the security of a block cipher.
  • a cipher system comprises a combination of block and stream ciphers.
  • the block cipher provides a changing key that is used to periodically re-key one or more stream ciphers.
  • an AES Advanced Encryption Standard, from the U.S. National Institute of Standards and Technology (NIST)
  • block cipher provides a set of 128-bit keys that are used to provide a stream of 576-bit keys that is used to re-key one or more SNO W-2 stream ciphers.
  • the output of the stream ciphers are used to encrypt multiple input data streams, or 'lanes' of data, using an optimized arrangement of the block and stream ciphers relative to these multiple lanes of data.
  • FIGs. IA- 1C illustrate an example multi-bit stream encryption system, in accordance with one embodiment of the present invention, that is systematically re-keyed using keys provided by a block cipher generator.
  • FIGs. 2A-2B and 3A-3B illustrate other example multi-bit stream encryption systems, in accordance with other embodiments of the present invention, that are systematically re- keyed using keys provided by a block cipher generator.
  • FIGs. 4A and 4B illustrate mixing systems, in accordance with various embodiments of the present invention, for encrypting data bytes using a cipher output that spans multiple bytes.
  • the same reference numeral refers to the same element, or an element that performs substantially the same function.
  • the drawings are included for illustrative purposes and are not intended to limit the scope of the invention.
  • FIG. IA illustrates an example block and stream cipher system, in accordance with one embodiment of the present invention, for multi-bit parallel encryption of an input stream 163 having a word size that is less than the word size of the stream cipher generator 150.
  • the input stream comprises 8-bit data bytes
  • a SNO W-2 stream cipher generator is used to provide the stream cipher.
  • the SNO W-2 process uses a 576-bit key 149 as an initial state for generating a sequence of 32-bit wide cipher output words 159.
  • a mixing unit 160 is used to perform the encryption of the input stream 163 by mixing the cipher output words 159 of the stream cipher generator 150 with the input stream 163.
  • the 8-bit input bytes 163 are 'spread' by a one-input, four- output demultiplexer 164 to form four 8-bit channels.
  • the 32-bit cipher word 159 is similarly partitioned into four 8-bit cipher bytes, one cipher byte for each channel.
  • a mixer 165 combines the 8-bit data byte on the channel with the cipher byte assigned to the channel to produce an encrypted byte.
  • the mixer 165 performs an exclusive-OR function to combine the data and cipher bytes.
  • the encrypted bytes of the four channels are provided to a four- input, one-output multiplexer 164' to form a sequence of encrypted output bytes 169 corresponding to each byte in the input stream 163.
  • FIG. IB illustrates a timing diagram corresponding to the operation of the encryption system of FIG. IA.
  • the first line illustrates the sequence of bytes in the input stream 163.
  • the second line illustrates the sequence of cipher output words 159 of the stream cipher generator 150. Because each cipher output word 159 is used to encode four bytes of the input stream 163, the sequence of output words from the stream cipher generator has a frequency of one-quarter the input byte rate. That is, in FIG. IA, the cipher clock CLK-2 151 that is used to provide each cipher word is operated at one-quarter the frequency of the clock CLK-3 161 that is used to input each input data byte.
  • the encryption-channel structure of FIG. IA is merely provided for ease of reference, and other structures may be used as well.
  • the demultiplexer 164 will be structured to provide two 16-bit channels.
  • the cipher clock CLK-2 151 will be operated at half the frequency of the clock CLK-3 161 that is used to input each input data word.
  • a serial register configuration or other structures may be used in lieu of the illustrated multiplexer structure as discussed further below with regard to FIGs. 4 and 5.
  • the stream cipher generator 150 receives its 576-bit key 149 from a block cipher generator 130.
  • the block cipher generator 130 receives its key from a session key generator 110 that generates a different key each time a user initiates an encryption session.
  • the session key is updated regularly to improve security.
  • an AES encryptor 135 generates a 128-bit block cipher output 139 that is an encryption of the current contents of a running counter 132 at each cycle of a controlling clock CLK-I 131.
  • the example SNO W-2 stream cipher generator uses a 576-bit key; as such, five cycles of the controlling clock CLK- 1 131 are required to provide a sufficient number of bits to form this key.
  • the 576-bit key corresponds to four and a half 128-bit cipher words from the AES encryptor 135, and the block cipher generator 130 includes a register 140 that is configured to store three and a half of these cipher words. When the fifth 128-bit cipher word is produced, a 576-bit output is provided using this current word and the previously stored three and a half words in the register 140.
  • stream cipher generators are generally significantly faster than block cipher generators, stream ciphers are less secure than block ciphers because the stream cipher repeats itself. If an attacker is able to determine some or all of the cipher sequences produced, and the repeat rate, the attacker would be able decrypt the encrypted material at each repetition of the determined sequence.
  • a new 576-bit key 149 is generated by the block cipher generator 130 and used to re-key the stream cipher generator 150 before the stream cipher generator 150 repeats itself. In this manner, a decryption of a prior segment of a stream-cipher-encrypted output cannot be used to facilitate decryption of a future segment.
  • FIG. 1C illustrates an example timing sequence for the generation and use of keys 149 in the example embodiment of FIG. IA.
  • the 128-bit block cipher output 139 of the AES encryptor 135 at each clock cycle CLK-I is identified as cipher words A 0 , A 1 , A 2 , etc.
  • the content of the register 140 of FIG. IA is identified for ease of reference as a stream 142 in FIG. 1C.
  • the current output A 4 and the stream 142 are available for keying the stream cipher generator 150.
  • another five cipher words A5-A9 are generated, and are used to re-key the stream cipher generator 150. As noted above, this re-keying preferably occurs before the stream cipher generator 150 repeats itself.
  • FIG. 2A illustrates an example embodiment of a "dual-lane" encryption system wherein two input streams 263, 264 are encrypted using a single block-stream cipher system comprising the session key generator 110, block cipher generator 130 and stream cipher generator 150 as detailed above.
  • FIG. 2A illustrates an example embodiment of a "dual-lane" encryption system wherein two input streams 263, 264 are encrypted using a single block-stream cipher system comprising the session key generator 110, block cipher generator 130 and stream cipher generator 150 as detailed above.
  • each cipher word 259 is demultiplexed across respective lanes corresponding to the input streams 263, 264.
  • a one- input two-output demultiplexer 220 provides each even cipher word 259 to the first two bytes of each of the input streams 263, 264, and each odd cipher word 259 to the next two bytes of each of the input streams 263, 264.
  • FIG. 2B illustrates an example timing arrangement for the embodiment of FIG. 2A.
  • each cipher word 259 is applied to a pair of input data bytes of each of the input streams 263, 264.
  • the block cipher generator 130 is preferably clocked to produce a new key 249 for the stream cipher generator using five new AES words (designated by reference numeral 139 of FIG. IA) before the stream cycle repeats itself.
  • each lane may be structured as a two-byte lane, as contrast to the four-byte lanes of FIGs. IA and 2 A.
  • the odd/even demultiplexer 220 would not be required.
  • An advantage of the four-byte-lane embodiment of FIG. 2A is the use of the same lane structure independent of whether one or two (or, as detailed below, four) input streams are being encrypted using the block-stream encryption system of this invention.
  • FIG. 3 A illustrates the use of multiple stream cipher generators with a single block cipher generator to encode, for example, four lanes of input data.
  • the dual-lane mixing unit 260 of FIG. 2A is used to encrypt each pair of the four-lanes of input data, and two stream cipher generators 150, 150' are used to provide the stream ciphers to these two mixing units 260. Because of the dual structure, the encryption of the four lanes can be effected at the same rate (CLK-2 251) as the encryption of the two lanes of FIG. 2 A.
  • the dual structure need not include a pair of block cipher generators to supply the keys to the pair of stream cipher generators.
  • the 576-bit key 349 that is used for the stream cipher generator 150 requires four and a half 128-bit cipher words 339 from an AES encryptor 135.
  • a multiplexer 342 is used to provide alternative half words 344 to the register 340.
  • two complete keys 349 may be produced from nine cipher words 339, instead of ten words 339. That is, instead of requiring a doubling of the rate of CLK-I 331 to support the two stream cipher generators 150, 150', the rate of CLK-I 331 need only be increased by a factor of 1.8. Because power consumption is generally related to speed, this 10% reduction in speed for the AES components may be significant.
  • FIG. 3B illustrates an example timing diagram for the embodiment of FIG. 3A.
  • a 576-bit key 349 can be generated using four of these words and half 344 of the cipher word that is stored in the register 341. This first key is used to key the "even" stream cipher generator 150.
  • another key 349 can be generated, using these four new words and the half of the cipher word 344 that had not been used for the first key. This second key is used to key the "odd" stream cipher generator 150'.
  • One of ordinary skill in the art will recognize that alternative structures are feasible in view of this disclosure.
  • the use of nine cipher words 339 to provide two keys 349 could be applied to the embodiments of FIGs. IA, 2A as well.
  • the relative speed of block and stream cipher generators generally do not demand such efficiency when the block cipher generator is coupled to a single stream cipher generator.
  • a single 32-bit stream cipher generator could be simply configured to directly encrypt each of the four data 8-bit input streams, but this would require that the stream cipher generator operate at twice the speed of the generators of FIG. 3 A, or that the data rate of the input data of FIG. 3 A be reduced in half.
  • a single block cipher generator may be used to provide keys to more than two stream cipher generators; a single stream cipher generator may be used to encrypt more than four data lanes, and so on.
  • FIGs. 4A and 4B illustrate example alternative embodiments of a mixing system that applies a 32-bit cipher word to a lane of 8-bit data words.
  • four shift registers R1-R4 420 are used to sequentially receive the 8-bit words of the data input stream, clocked in by the input data clock CLK-3.
  • the 32-bit cipher output 450 is partitioned into four 8-bit segments that are provided to the registers R1-R4 420 via encryption multiplexer 410.
  • Each encryption multiplexer 410 determines whether each register receives the unencrypted data input from the previous stage, or an encryption of the data input from the previous stage.
  • Each encryption multiplexer 410 includes an 8- bit wide XOR gate 412, and an input switch 411 that determines one of the inputs of the XOR gate. To effect a pass-through of the input data without encryption, the switch 411 provides a fixed "0" output, so that the XOR gate 412 has no effect on the input data.
  • the input switch 411 When the "encrypt" signal is enabled, the input switch 411 provides eight bits of the cipher to the XOR gate 412 to effect an encryption of the input data.
  • the encrypt signal is enabled after three input data words are clocked into the registers R1-R3 420 and the fourth data word is available at the input of the first encryption multiplexer 410.
  • the registers are next clocked while the encrypt signal is enabled, and each register R1-R4 420 will be loaded with an encrypted data word.
  • the encrypt signal is then disabled, and the process is repeated.
  • the encrypt signal is enabled once for every four data clock CLK-3 cycles, and thus the cipher output 450 need only be provided at one-quarter the data-input rate, as expected.
  • a switch 440 is used to sequentially select each of the four 8-bit segments of the cipher output 450.
  • the selected cipher segment is XOR'd with the current 8-bit data-input word, and preferably clocked into a register 420 to avoid switching transients.
  • a single 8-bit encryption stage comprising XOR gate 412 and register 420 provides an encrypted output at the data input rate of clock CLK-3.
  • the cipher output 450 is preferably updated every four cycles of the data input clock CLK-3, so that no 8-bit cipher segment from the switch 440 is reused.
  • alternative encryption schemes may be used to assure the optimal/efficient use of each of the cipher bits provided by the stream cipher generator.

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Storage Device Security (AREA)

Abstract

L'invention concerne un système de chiffrement qui présente une configuration combinant des générateurs de chiffre par blocs (130) et des générateurs de chiffre continu (150). Le générateur de chiffre par blocs (130) produit une clé changeante (149) qui sert à mettre à jour périodiquement un ou plusieurs générateurs (150) de chiffre continu. Le système décrit comprend de préférence un chiffreur AES par blocs (135) fournissant un ensemble de chiffres de 128 bits (139) qui servent à produire un flux continu de clés de 576 bits (149) utilisées pour la mise à jour périodique d'un ou de plusieurs générateurs de chiffre continu SNO W-2 (150). La sortie (159) des générateurs de chiffre continu (150) est utilisée pour chiffrer une pluralité de flux de données d'entrée (263-264), ou 'voies' de données, au moyen d'une combinaison optimisée de chiffres par blocs (130) et de chiffres continus (150) pour ces voies de données (263-264).
PCT/IB2006/054319 2005-11-23 2006-11-17 Chiffrement et dechiffrement multvoie ultrarapide WO2007060587A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008541867A JP2009516976A (ja) 2005-11-23 2006-11-17 マルチレーン高速暗号化及び復号
EP06821487A EP1955473A1 (fr) 2005-11-23 2006-11-17 Chiffrement et dechiffrement multvoie ultrarapide

Applications Claiming Priority (2)

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US73921905P 2005-11-23 2005-11-23
US60/739,219 2005-11-23

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JP (1) JP2009516976A (fr)
KR (1) KR20080073348A (fr)
CN (1) CN101313509A (fr)
RU (1) RU2008125109A (fr)
WO (1) WO2007060587A1 (fr)

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WO2010142083A1 (fr) * 2009-06-12 2010-12-16 中国科学院数据与通信保护研究教育中心 Procédé et dispositif adaptés pour mettre en oeuvre un chiffre continu
KR101068367B1 (ko) * 2008-02-27 2011-09-28 인텔 코오퍼레이션 병렬 연산 모드에서 ａｅｓ 암호화 및 암호 해독을 최적화하는 방법 및 장치
EP2416523A1 (fr) * 2010-08-04 2012-02-08 STMicroelectronics (Grenoble 2) SAS Procédé de chiffrement d'un flux de données
US8533456B2 (en) 2010-10-07 2013-09-10 King Saud University Accelerating stream cipher operations using single and grid systems
US8666064B2 (en) 2009-11-26 2014-03-04 Samsung Electronics Co., Ltd. Endecryptor capable of performing parallel processing and encryption/decryption method thereof
US8995652B1 (en) 2013-08-09 2015-03-31 Introspective Power, Inc. Streaming one time pad cipher using rotating ports for data encryption
US9584488B2 (en) 2013-08-09 2017-02-28 Introspective Power, Inc. Data encryption cipher using rotating ports
EP3751781A1 (fr) * 2019-07-12 2020-12-16 INTEL Corporation Réduction de surdébit pour protection de liaison
US11283619B2 (en) * 2019-06-20 2022-03-22 The Boeing Company Bit mixer based parallel MAC and hash functions

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CN103365581B (zh) * 2012-03-31 2019-01-25 百度在线网络技术（北京）有限公司 一种基于解锁密码对用户设备进行触摸解锁的方法和设备
JP2017005682A (ja) * 2016-02-16 2017-01-05 国立大学法人京都大学 データ処理装置、データ送信方法、コンピュータプログラム、及びデータサーバ
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KR102097702B1 (ko) * 2018-10-18 2020-04-07 주식회사 우리넷 저지연 블록 암호 운영모드를 위한 키 생성 방법
KR102479689B1 (ko) * 2020-12-24 2022-12-20 주식회사 우리넷 저지연 블록 암호 처리 방법 및 그 장치

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US8600049B2 (en) 2008-02-27 2013-12-03 Intel Corporation Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation
KR101068367B1 (ko) * 2008-02-27 2011-09-28 인텔 코오퍼레이션 병렬 연산 모드에서 ａｅｓ 암호화 및 암호 해독을 최적화하는 방법 및 장치
US8194854B2 (en) 2008-02-27 2012-06-05 Intel Corporation Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation
WO2010142083A1 (fr) * 2009-06-12 2010-12-16 中国科学院数据与通信保护研究教育中心 Procédé et dispositif adaptés pour mettre en oeuvre un chiffre continu
US8666064B2 (en) 2009-11-26 2014-03-04 Samsung Electronics Co., Ltd. Endecryptor capable of performing parallel processing and encryption/decryption method thereof
FR2963713A1 (fr) * 2010-08-04 2012-02-10 St Microelectronics Grenoble 2 Procede de chiffrement d'un flux de donnees
EP2416523A1 (fr) * 2010-08-04 2012-02-08 STMicroelectronics (Grenoble 2) SAS Procédé de chiffrement d'un flux de données
US8533456B2 (en) 2010-10-07 2013-09-10 King Saud University Accelerating stream cipher operations using single and grid systems
US8995652B1 (en) 2013-08-09 2015-03-31 Introspective Power, Inc. Streaming one time pad cipher using rotating ports for data encryption
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JP2009516976A (ja) 2009-04-23
KR20080073348A (ko) 2008-08-08
CN101313509A (zh) 2008-11-26
RU2008125109A (ru) 2009-12-27

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