WO2007043130A1 - Traceur d’image, circuit intégré semi-conducteur, et procédé de tracé - Google Patents

Traceur d’image, circuit intégré semi-conducteur, et procédé de tracé Download PDF

Info

Publication number
WO2007043130A1
WO2007043130A1 PCT/JP2005/018291 JP2005018291W WO2007043130A1 WO 2007043130 A1 WO2007043130 A1 WO 2007043130A1 JP 2005018291 W JP2005018291 W JP 2005018291W WO 2007043130 A1 WO2007043130 A1 WO 2007043130A1
Authority
WO
WIPO (PCT)
Prior art keywords
thread
end detection
threads
image
processing
Prior art date
Application number
PCT/JP2005/018291
Other languages
English (en)
Japanese (ja)
Other versions
WO2007043130A9 (fr
Inventor
Hideaki Yamauchi
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2005/018291 priority Critical patent/WO2007043130A1/fr
Publication of WO2007043130A1 publication Critical patent/WO2007043130A1/fr
Publication of WO2007043130A9 publication Critical patent/WO2007043130A9/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Definitions

  • the present invention relates to a drawing device, a semiconductor integrated circuit device, and a drawing method, and more particularly to a drawing device, a semiconductor integrated circuit device, and a drawing method for processing a plurality of drawing threads.
  • 3D computer graphics which has been used in high-performance workstations and game machines, has been rapidly applied to embedded devices.
  • LSI Large Scale Integrated circuit
  • real-time rendering that draws moving objects at high speed and limited processing time is required under limited performance and cost constraints. It is required to perform graphics drawing processing.
  • FIG. 9 is a diagram showing a configuration of a conventional basic drawing apparatus.
  • the drawing apparatus 800 includes a CPU (Central Processing Unit) 801, a drawing module 802, a drawing end detection module 803, a memory controller 804, and a frame buffer 805.
  • the drawing module 802, the drawing end detection module 803, and the memory controller 804 force S1 are integrated as one graphics LSI.
  • two different drawing threads (a set of drawing commands and drawing target data, typically one frame of the movie) A and B are shown together, and arrows Sa,
  • the length of Sb schematically shows the processing time in the drawing module 802 of each drawing thread (hereinafter abbreviated as thread) A and B.
  • thread A is a thread that requires real-time drawing
  • thread B is a thread that requires high-load drawing processing.
  • the frame buffer 805 has two buffers 80 5-1 for surface 1 and surface 2 for threads A and B, respectively, in order to realize double buffering that can prevent flickering of the display image. 805-2, 805-3, and 805-4, which hold the image data generated by the threads A and B, and then output them to a display (not shown).
  • FIG. 10 is a timing chart showing the operation of the conventional drawing apparatus. T20 to T26 indicate the timing of each process.
  • the drawing end flag which is an interrupt signal from the drawing end detection module 803 to the CPU 801
  • the drawing module 802 performs the drawing process for the thread ⁇ sent from the CPU 801 and writes the image data into the buffer 805-1 of the frame buffer 805.
  • the image data is output from the buffer 805-2 on the surface 2 of the thread A and displayed on a display (not shown).
  • the drawing process of the surface 1 of the thread B is in an idle state, and the image data is output from the buffer 805-4 of the surface 2 and displayed on a display (not shown).
  • the drawing module 802 sets the drawing process of thread A to the idle state, and this time the drawing process of surface 1 of thread B is performed.
  • the image data generated by the drawing process at this time is written into the nota 805-3.
  • the drawing process of the thread B is a high-load drawing process, and therefore takes more time than the drawing process of the thread A (T21 to T22).
  • the drawing module 802 sets the drawing process of surface 1 of thread ⁇ ⁇ ⁇ ⁇ to the idle state.
  • the drawing end detection module 803 turns on the drawing end flag and ends the drawing process of frame 1.
  • the drawing process for frame 2 in ⁇ 24, ⁇ 25, and ⁇ 26 is almost the same as the drawing process for 121, ⁇ 22, and ⁇ 23 in frame 1. This time, the drawing process for surface 2 of thread ⁇ and ⁇ is performed, and the image data is buffered. Write to 805-2 and 805-4. At this time, the image data of frame 1 drawn by ⁇ 20 to ⁇ 22 is output and displayed on the display (not shown) from the noffers 805-1 and 805-3.
  • FIG. 11 is a diagram showing a configuration of a conventional drawing apparatus having a plurality of drawing modules.
  • the drawing apparatus 900 shown here includes a CPU 901, for example, three drawing modules 902-1, 902-2, 902-3, and three corresponding drawing end detection modules 903-1, 903-2, 903— 3, a memory controller 904, a frame buffer 905, and a scheduler 906 that divides a thread into thread pieces (hereinafter referred to as sub-threads) and inputs them in parallel to the respective drawing modules 902-1 to 902-3.
  • a CPU 901 for example, three drawing modules 902-1, 902-2, 902-3, and three corresponding drawing end detection modules 903-1, 903-2, 903— 3, a memory controller 904, a frame buffer 905, and a scheduler 906 that divides a thread into thread pieces (hereinafter referred to as sub-threads) and inputs them in parallel to the respective drawing modules 902-1 to 902-3.
  • sub-threads thread pieces
  • the frame buffer 905 consists of these three threads A, B, and C.
  • the sofas 905-1, 905-2, 905-3, 9 05-4, 905-5, 905 — Has 6 and realizes double buffering.
  • the lengths of the arrows Sal, Sa2, Sa3, Sbl, Sb2, Sb3, Scl, Sc2, Sc3 are the processing times of the drawing modules 902-1 to 902-3 for the sub-threads of each thread A, B, C. Show.
  • thread A is a thread that requires real-time drawing
  • thread B is a thread that requires medium-load drawing processing
  • thread C requires high-load drawing processing. Is a thread.
  • the scheduler 906 divides threads A, B, and C into sub-threads and distributes them in a balanced manner to the drawing modules 902-1 to 902-3. Can be increased.
  • Patent Document 1 Japanese Patent Laid-Open No. 2001-14478
  • An advantage of some aspects of the invention is that it provides a drawing apparatus capable of efficiently processing a plurality of different threads.
  • Another object of the present invention is to provide a semiconductor integrated circuit device that can efficiently process a plurality of different threads.
  • Another object of the present invention is to provide a drawing method capable of efficiently processing a plurality of different threads.
  • a drawing apparatus 100 comprising: a drawing end detection unit 104 that detects the end of processing independently for each drawing thread and sends an independent drawing end detection signal for each drawing thread.
  • the image drawing unit 103 performs an image drawing process based on the drawing thread
  • the drawing end detection unit 104 indicates the end of the drawing process in the image drawing unit 103. Detection is performed independently for each drawing thread, and an independent drawing end detection signal is transmitted for each drawing thread.
  • the end of the drawing process in the image drawing means that performs the drawing process of the image based on the drawing thread is detected independently for each drawing thread, and an independent drawing end detection signal for each drawing thread.
  • FIG. 1 is a diagram showing a configuration of a drawing apparatus according to a first embodiment.
  • FIG. 2 is a diagram showing an example of a digital dashboard.
  • FIG. 3 is a timing chart showing the operation of the drawing apparatus of the first embodiment.
  • FIG. 4 is a diagram showing a specific example of a thread.
  • FIG. 5 is a diagram showing a configuration of a drawing apparatus according to a second embodiment.
  • FIG. 6 is a diagram showing an example of threads assigned to each drawing module.
  • FIG. 7 is a timing chart for explaining the operation of the drawing apparatus according to the second embodiment.
  • FIG. 8 is a diagram showing a configuration of a drawing apparatus according to a third embodiment.
  • FIG. 9 is a diagram showing a configuration of a conventional basic drawing apparatus.
  • FIG. 10 is a timing chart showing the operation of a conventional drawing apparatus.
  • FIG. 11 is a diagram showing a configuration of a conventional drawing apparatus having a plurality of drawing modules.
  • FIG. 1 is a diagram illustrating a configuration of a drawing apparatus according to the first embodiment.
  • the drawing apparatus 100 includes a CPU 101, a scheduler 102, an image drawing unit 103, a drawing end detection unit 104, a selector 105, a memory controller 106, and a frame buffer 107.
  • scheduler 102, image drawing unit 103, drawing end detection unit 1 04, selector 105, and memory controller 106 are integrated in one graphics LSI.
  • the CPU 101 controls the sending of threads A and B and the memory controller 106.
  • the scheduler 102 sends the threads A and B sent from the CPU 101 to the image drawing unit 103, extracts the identifiers of which the thread A and B forces are identification information, and sends them to the selector 105.
  • the image drawing unit 103 performs an image drawing process based on the input threads A and B.
  • the drawing end detection unit 104 detects the end of the drawing process in the image drawing unit 103 independently for each of the threads A and B, and sends an independent drawing end detection signal to the CPU 101 for each of the threads A and B.
  • the drawing end detection unit 104 includes two drawing end detection modules 104a and 104b.
  • the drawing end detection module 104a detects the end of the drawing processing of the thread A and sends a drawing end detection signal.
  • the drawing end detection module 104b detects the end of drawing processing of the thread B and sends a drawing end detection signal. These are processed asynchronously and independently of each other.
  • the drawing end detection signal is cleared independently as well.
  • the selector 105 selects one of the drawing end detection modules 104a and 104b according to the identifier sent from the scheduler 102, and detects the end of the drawing processing of the threads A and B.
  • the memory controller 106 outputs the image data processed by the image drawing unit 103 to the frame buffer 107 under the control of the CPU 101.
  • the frame buffer 107 has two buffers 107-1 for surface 1 and surface 2 for threads A and B, respectively, in order to realize double buffering that can prevent flickering of the displayed image.
  • 107-2, 107-3, 107-4 which hold the image data generated by each thread A and B, and then output it to a display (not shown).
  • the image drawing unit 103 and the drawing end detection unit 104 also receive a vertical synchronization signal as a synchronization signal for frame update control in the external force.
  • thread A is a thread that requires real-time drawing
  • thread B is a thread that requires high-load drawing processing.
  • FIG. 2 is a diagram illustrating an example of a digital dashboard.
  • the tachometer needle 110 and the speedometer needle 111, etc. require real-time drawing to faithfully reproduce the engine speed and speed while driving. For example, high-speed drawing processing at a frame rate of 60 fps (frame per second) is required.
  • the vehicle body information 112 that is three-dimensionally drawn requires high-load drawing processing. The process is performed at about 8 fps, for example.
  • the blinker 113, the information display 114, the warning light 115, and the like need to be drawn with threads having different required frame rates (for example, 20 fps).
  • the dial and background are still images.
  • a thread for drawing the tachometer needle 110 is a thread A and a thread for drawing the vehicle body information 112 is a thread B.
  • FIG. 3 is a timing chart showing the operation of the drawing apparatus according to the first embodiment.
  • T1 to T6 indicate the timing of each process.
  • the drawing end flag (drawing end detection signal) output to the CPU 101 is cleared by the force of each of the drawing end detection modules 104a and 104b in synchronization with the rising of the vertical synchronization signal to the ⁇ level. (Tl).
  • the image drawing unit 103 performs a drawing process for the thread ⁇ sent from the CPU 101 via the scheduler 102, and writes the image data in the buffer 107-1 of the frame buffer 107.
  • the image data is output from the buffer 107-2 on the surface 2 of the thread A and displayed on a display (not shown).
  • the drawing process of the surface 1 of the thread B is in an idle state, and the image data is output from the buffer 107-4 of the surface 2 to a display (not shown) and displayed.
  • FIG. 4 is a diagram showing a specific example of a thread.
  • a thread is a set of drawing commands and drawing target data, and is typically a motion. Handles the processing of one frame of an image.
  • the CPU 101 inputs drawing data 1, 2, 3,..., A drawing end command, and a drawing end detection command to the scheduler 102 in order from the drawing start command, and the scheduler 102 sends these to the image drawing unit 103. Let it be processed.
  • the bit length of each command is 32 bits, for example.
  • the identifier for identifying the thread is embedded using, for example, some empty bits of the drawing end detection command. For example, by using 4 bits, 16 different threads can be identified.
  • the identifier is extracted by the scheduler 102 and sent to the selector 105.
  • the selector 105 finishes drawing according to the identifier extracted from the drawing end detection command by the scheduler 102. Select the detection destination of the drawing end detection information generated by the detection command.
  • the image drawing unit 103 sends drawing end detection information to the drawing end detection module 104a.
  • the drawing end detection module 104a turns on the drawing end flag and notifies the CPU 101 that the drawing processing of frame 1 of thread A has ended.
  • the image drawing unit 103 sets the drawing process of the thread A to the idle state, and this time, the drawing process of the surface 1 of the thread B is performed.
  • the CPU 101 issues a thread as shown in FIG. 4, and the image drawing unit 103 similarly performs a drawing process.
  • the image data generated by the drawing process at this time is written into the buffer 107-3.
  • the drawing end detection module 104a clears the drawing end flag related to the thread A drawing processing. Then, the CPU 101 starts drawing the frame 2 of the thread A. At this time, the image drawing unit 103 interrupts drawing of the thread B that is being drawn and yields resources for the drawing process of the thread A. Then, the drawing process for frame 2 of thread A is performed, and the image data is written into the buffer 107-2. At this time, the image data of frame 1 is output from the buffer 107-1 on the surface 1 of the thread A and displayed on the display (not shown).
  • the selector 105 sends the drawing end detection information generated by the drawing end detection command in the image drawing unit 103 to the drawing end detection module 104a. Send it out.
  • the drawing end detection module In step 104a the drawing end flag is turned on to notify the CPU 101 that the drawing process of frame 2 of thread A has been completed.
  • the image drawing unit 103 resumes the drawing process for frame 1 of thread B that has been suspended.
  • the scheduler 102 When the drawing end command of thread B is input to the image drawing unit 103 (T5), the scheduler 102 extracts the identifier of the drawing end detection command of thread B and sends it to the selector 105. Thereby, the drawing end detection information generated by the drawing end detection command of the image drawing unit 103 is sent to the drawing end detection module 104b.
  • the drawing end detection module 104b turns on a drawing end flag which is a drawing end detection signal of the thread B, and notifies the CPU 101 that the drawing process of the frame 1 of the thread B has ended.
  • the image drawing unit 103 puts the drawing process of the thread B into an idle state.
  • the drawing end detection module 104b clears the drawing end flag related to the thread B drawing processing, and the thread B frame 2 drawing processing is performed. Is in an idle state. Also, the image data is output from the buffer 103-3 holding the image data of frame 1 of the thread B and displayed on a display (not shown).
  • the thread A proceeds with image processing for one frame using the synchronization signal (vertical synchronization signal) for frame update control as a trigger.
  • thread B which requires high-load non-real-time processing, performs one frame of drawing processing over four cycles of thread A.
  • the drawing end detection unit 104 detects the end of the drawing processing of the threads A and B independently for each of the threads A and B, and the thread Since an independent drawing end detection signal is sent for each of A and B, the processing of different threads A and B can proceed asynchronously.
  • the tachometer needle 110 of the digital dashboard shown in FIG. when drawing at high speed, it is not necessary for thread A to wait until one frame of high-load thread B such as body information 112 to be three-dimensionally drawn is completed, and real-time drawing is possible.
  • the rendering process of thread B can be resumed when the process of thread A is completed, normal image data can be obtained without destroying the information being rendered by thread B.
  • thread A that requires real-time drawing is processed as a high-priority thread
  • thread B that requires high-load drawing processing is a low-priority thread
  • high-priority thread is interrupted during the drawing process of A.
  • These priorities may be distinguished by identifiers, or may be determined by the order in which threads A and B are inserted into the scheduler 102 or the image drawing unit 103. Further, priority information may be added to a drawing start command of each thread.
  • the priority information is represented by, for example, a numerical value or the number of requested frames (frame rate) per second.
  • the scheduler 102 recognizes the identifier and temporarily stores it when the drawing start command is read.
  • the stored identifier is sent to the selector 105, so that the same effect as when an identifier is added to the drawing end detection command can be obtained. .
  • the identifier may be generated and added by the scheduler! For example,
  • the drawing end detection unit 104 has a drawing end detection module according to the number of threads.
  • the drawing end detection unit 104 does not have a plurality of drawing end detection modules, and directly receives drawing end detection information with an identifier from the image drawing unit 103, and provides an independent drawing end detection signal for each thread. May be sent out.
  • FIG. 5 is a diagram illustrating a configuration of a drawing apparatus according to the second embodiment.
  • the drawing apparatus 200 of the second embodiment includes a CPU 201, a scheduler 202, an image drawing unit 203 having three drawing modules 203-1, 203-2, 203-3, and a drawing end detection unit. 204.
  • the selector 105, the memory controller 106, and the frame buffer 107 shown in FIG. 1 are not shown.
  • the thread A is a thread that requires real-time drawing
  • the thread B is a thread that requires a medium-load drawing process
  • the thread C is a thread that requires a high-load drawing process.
  • the scheduler 202 divides the threads A, B, and C sent from the CPU 201 into sub-threads, and distributes them in a balanced manner in parallel to the drawing modules 203-1 to 203-3.
  • Arrows Sal, Sa2, Sa3, Sbl, Sb2, Sb3, Scl, Sc2, Sc3 are the lengths of the sub-thread drawing modules 203-1 to 203-3 of each thread A, B, and C. Shows
  • Identifiers for identifying the threads A, B, and C are added by the power applied to the drawing start command or the drawing end detection command (see FIG. 4) and the scheduler 202.
  • the scheduler 202 generates an identifier for each sub-thread to be divided in accordance with the identifier for each thread A, B, or C.
  • each drawing module 203-1 to 203-3 is added to the end of the sub-thread to be processed.
  • a drawing end command and a drawing end detection command are generated.
  • the above-described subthread identifier is added to the drawing end detection command added here.
  • FIG. 6 is a diagram illustrating an example of threads assigned to each drawing module.
  • Drawing module 203 1 includes thread A sub-thread data Al,..., Ai, thread B sub-thread data Bl,..., Bi, thread C sub-thread data CI,. Ci is assigned, and after the data Ai, Bi, Ci of the last sub thread of each thread A, B, C, a drawing end command and a drawing end detection command are sent by the scheduler 202. Is added. In addition, the identifiers al, bl, and cl of each sub thread are added to the drawing end detection command.
  • the drawing module 203-2 is assigned the data A2 of the sub-threads of threads A, B, and C,... ⁇ Aj, B2,... ⁇ Bj, C2,... ⁇ Cj power ij. 203—3, Thread A, B, C sub-thread data A3,... ⁇ Ak, B3, ..., Bk, C3, ..., Ck force assigned. Identifiers a2, b2, c2, a3, b3, and c3 are added to the drawing end detection commands.
  • the drawing modules 203-1 to 203-3 input the assigned sub threads in order from the top of FIG.
  • each of the drawing modules 203-1 to 203-3 draws drawing end detection information generated from the drawing end detection command via a selector (not shown) according to the subthread identifier. It is sent to the end detection unit 204.
  • the drawing end detection unit 204 includes three drawing end detection modules 204-1, 204-2, and 204-3 in order to detect the states of the three threads A, B, and C.
  • the drawing end detection module 204-1 aggregates the drawing end detection information of the sub-threads (identifiers al, a2, and a3) of the thread A assigned to the drawing modules 203-1 to 203-3, so that one frame of the thread A When the drawing end detection information is restored, the thread A drawing end detection signal is sent to the CPU 201.
  • the drawing end detection modules 204-2 and 204-3 collect the drawing end detection information of the threads B and C ⁇ sub-threads (identifiers bl, b2, and b3 and identifiers cl, c2, and c3), respectively.
  • the drawing end detection signals of thread B and thread C are sent to the CPU 201 independently.
  • FIG. 7 is a timing chart for explaining the operation of the drawing apparatus according to the second embodiment.
  • threads 8, B, and C are given high priority (threads that require real-time drawing), and threads B and C Are of the same priority.
  • each of the drawing modules 203-1 to 203-3 preferentially processes the sub-threads (identifiers al, a2, and a3) of thread A that require real-time drawing (T10).
  • the sub-thread drawing processing related to thread A is set to the idle state.
  • the drawing end detection information generated by the drawing end detection command is sent to the drawing end via a selector (not shown). Send to detection module 204-1.
  • the drawing end detection module 204-1 When the drawing end detection module 204-1 receives the drawing end detection information of the sub thread of thread A from all the drawing modules 203-1 to 203-3, the drawing end detection module 204-1 aggregates them and sends one frame of thread A to the CPU 201 A drawing end detection signal is sent to indicate that the process has been completed (the drawing end flag is turned on).
  • each of the drawing modules 203-1 to 203-3 performs the drawing process of the sub thread (identifiers bl, b2, b3) of thread B to be input next.
  • the drawing process of the sub thread of the thread B is interrupted when the drawing process of the sub thread of the thread C is started (T12).
  • the drawing process of the sub thread of thread C is interrupted when the drawing end flag related to the drawing process of thread A is cleared and the drawing process of the thread piece of the next frame of thread A starts again (T13). .
  • each drawing module 203-1 to 203-3 executes the drawing end command for the sub thread of thread B and completes the processing of the sub thread of thread B (T14).
  • the processing related to B is set in the idle state, and the drawing end detection information is sent to the drawing end detection module 204-2 by referring to the sub-thread identifiers bl, b2, and b3 attached to the drawing end detection command as shown in FIG. Sent to.
  • the drawing end detection module 204-2 receives drawing end detection information of the sub-thread of thread B from all the drawing modules 203-1 to 203-3, the drawing end detection module 204-2 saves about one frame of the thread B to the CPU 201.
  • a drawing end detection signal indicating that the process has been completed is sent.
  • the drawing end detection module 204-3 includes all the drawing modules 203-1 to 2-2.
  • these are collected and a drawing end detection signal indicating that processing of one frame of thread C has been completed is sent to the CPU 201 (T15 ).
  • the drawing end detection modules 204-1 to 204-3 end drawing of the threads A, B, and C. Since the detection unit 204 detects each thread A, B, and C independently and sends an independent drawing end detection signal for each thread A, B, and C, a plurality of drawing modules 203-1 to 203-3 are used. In the high-efficiency drawing apparatus 200 that processes the threads A, B, and C into sub-threads and processes them in parallel, the processing of the different threads A, B, and C can be performed asynchronously.
  • the drawing end detection unit 204 has a drawing end detection module corresponding to the number of threads.
  • FIG. 8 is a diagram illustrating a configuration of a drawing apparatus according to the third embodiment.
  • the drawing apparatus 300 processes sub-threads in parallel from a plurality of drawing modules 203-1 to 203-3 like the drawing apparatus 200 according to the second embodiment.
  • the drawing end detection unit 304 directly detects the drawing end flag of the sub thread together with the identifier of each sub thread from each of the drawing modules 203-1 to 203-3.
  • a thread that does not have a plurality of drawing end detection modules is the maximum that can be expressed by the bit width of the identifier added to the drawing start command and the drawing end detection command described above. Recognize up to numbers. This can contribute to the reduction of hardware resources and the reduction of parallel processing capacity due to a lack of hardware resources.

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Processing (AREA)
  • Image Generation (AREA)

Abstract

Différents filets sont traités de manière efficace. Un traceur d'image (103) réalise un traitement de tracé d'image selon des filets de tracé, et un détecteur de fin de tracé (104) détecte le terme du traitement de tracé réalisé par le traceur d'image (103) indépendamment pour chacun des filets de tracé et envoie un signal de détection de fin de tracé indépendamment pour chaque filet de tracé. De cette manière, différents filets de tracé sont traités de manière asynchrone. Ainsi, par exemple, il n’est pas nécessaire qu’un filet que l’on souhaite tracer à grande vitesse soit maintenu en attente jusqu’au terme du traitement d’un autre filet de poids important. Ceci permet le traitement efficace de différents filets.
PCT/JP2005/018291 2005-10-03 2005-10-03 Traceur d’image, circuit intégré semi-conducteur, et procédé de tracé WO2007043130A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2005/018291 WO2007043130A1 (fr) 2005-10-03 2005-10-03 Traceur d’image, circuit intégré semi-conducteur, et procédé de tracé

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2005/018291 WO2007043130A1 (fr) 2005-10-03 2005-10-03 Traceur d’image, circuit intégré semi-conducteur, et procédé de tracé

Publications (2)

Publication Number Publication Date
WO2007043130A1 true WO2007043130A1 (fr) 2007-04-19
WO2007043130A9 WO2007043130A9 (fr) 2007-05-31

Family

ID=37942400

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2005/018291 WO2007043130A1 (fr) 2005-10-03 2005-10-03 Traceur d’image, circuit intégré semi-conducteur, et procédé de tracé

Country Status (1)

Country Link
WO (1) WO2007043130A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012064215A (ja) * 2010-09-20 2012-03-29 Internatl Business Mach Corp <Ibm> アシスト・ハードウエア・スレッドの拡張可能な状態追跡のための方法、情報処理システム、およびプロセッサ
JP2012123821A (ja) * 2009-04-03 2012-06-28 Sony Corp 情報処理装置、情報処理方法、及び、プログラム

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07282272A (ja) * 1994-04-13 1995-10-27 Hitachi Ltd 描画処理システム
JPH08138060A (ja) * 1994-11-04 1996-05-31 Hitachi Ltd 並列プロセッサを用いる表示処理装置
WO2002031769A1 (fr) * 2000-10-10 2002-04-18 Sony Computer Entertainment Inc. Procede et systeme de traitement de donnees, programme informatique, et support enregistre

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07282272A (ja) * 1994-04-13 1995-10-27 Hitachi Ltd 描画処理システム
JPH08138060A (ja) * 1994-11-04 1996-05-31 Hitachi Ltd 並列プロセッサを用いる表示処理装置
WO2002031769A1 (fr) * 2000-10-10 2002-04-18 Sony Computer Entertainment Inc. Procede et systeme de traitement de donnees, programme informatique, et support enregistre

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
FUJII S. ET AL: "Media Shoriyo Kumikomi OS", INFORMATION PROCESSING SOCIETY OF JAPAN KENKYU HOKOKU, vol. 98, no. 15, 26 February 1998 (1998-02-26), pages 61 - 66, XP003010988 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012123821A (ja) * 2009-04-03 2012-06-28 Sony Corp 情報処理装置、情報処理方法、及び、プログラム
JP2012064215A (ja) * 2010-09-20 2012-03-29 Internatl Business Mach Corp <Ibm> アシスト・ハードウエア・スレッドの拡張可能な状態追跡のための方法、情報処理システム、およびプロセッサ

Also Published As

Publication number Publication date
WO2007043130A9 (fr) 2007-05-31

Similar Documents

Publication Publication Date Title
US10078882B2 (en) Priority-based command execution
JP5774699B2 (ja) マルチメディアプロセッサにおける順序通りでないコマンド実行
US9489763B2 (en) Techniques for setting up and executing draw calls
US8087029B1 (en) Thread-type-based load balancing in a multithreaded processor
KR101552079B1 (ko) 그래픽스 프로세싱 유닛 상의 그래픽스 및 비그래픽스 어플리케이션들의 실행
US10078879B2 (en) Process synchronization between engines using data in a memory location
US20070076246A1 (en) Image processing apparatus
TW200926050A (en) Shader processing systems and methods
JP5578713B2 (ja) 情報処理装置
US10275275B2 (en) Managing copy operations in complex processor topologies
US20150206596A1 (en) Managing a ring buffer shared by multiple processing engines
JP5534426B2 (ja) 画像形成装置およびそのプログラム
CN113892134A (zh) 具有优化的性能的多媒体系统
US20150189012A1 (en) Wireless display synchronization for mobile devices using buffer locking
WO2007043130A1 (fr) Traceur d’image, circuit intégré semi-conducteur, et procédé de tracé
JP4011082B2 (ja) 情報処理装置、グラフィックプロセッサ、制御用プロセッサおよび情報処理方法
US20110029757A1 (en) Stream processor and task management method thereof
US9170820B2 (en) Syscall mechanism for processor to processor calls
US20080313436A1 (en) Handling of extra contexts for shader constants
JP2009003633A (ja) 情報処理装置
US10037169B2 (en) Image processing semiconductor device and image processing device
US10423424B2 (en) Replicated stateless copy engine
JP3456443B2 (ja) 並列ソート装置及び該装置のプログラムを記録した記録媒体
US20240045736A1 (en) Reordering workloads to improve concurrency across threads in processor-based devices
US20150199833A1 (en) Hardware support for display features

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 05788053

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP