WO2007033905A1

WO2007033905A1 - Data processing system for checking and correcting a data word and operating method therefor

Info

Publication number: WO2007033905A1
Application number: PCT/EP2006/066059
Authority: WO
Inventors: Thomas Kottke; Yorck Collani; Markus Ferch
Original assignee: Robert Bosch Gmbh
Priority date: 2005-09-23
Filing date: 2006-09-06
Publication date: 2007-03-29
Also published as: DE102005045400A1

Abstract

A data processing system comprises at least one execution unit (1) and an addressable memory (2), with which the execution unit (1) communicates using an address bus (3) and a data bus (4), as well as a bus monitoring unit (6) which is set up to recognize a read access to a given memory location of the memory (2) by the execution unit (1) and to instead convey a read access to an alternative memory location associated with the given memory location to the processor (1). The given memory location contains a data word which is coded using an error correction code, and the alternative memory location contains the same data word in corrected form. The data processing system comprises a device (14) for checking that the data word, which has been read from the given memory location, is free of errors and, in the event of an error, for correcting the data word and storing the corrected data word in the alternative memory location.

Description

DATA PROCESSING SYSTEM FOR VERIFYING AND CORRECTING A DATA RESPONSE AND OPERATING METHOD THEREFOR

10 State of the art

The present invention relates to a data processing system having at least one execution unit, such as a microprocessor and an address processor.

A memory to which the execution unit communicates via an address bus and a data bus and a bus monitoring unit configured to read access the execution unit to a given memory location of the execution unit

20 memory to recognize and instead provide the processor read access to an alternative memory space associated with the given memory space.

Known data processing systems of this type include a plurality of processors which share the addressable memory and each have their own associated cache memory into which areas of the memory are copied,

The processor has recently accessed or is expected to access for other reasons. The cache Memory, because of its circuit structure and / or its greater proximity to its associated processor, is able to handle read or write requests faster than the shared memory, thereby increasing the performance of the associated processor.

One problem with multi-processor systems with caching is that inconsistencies between the cache and shared memory can occur when a processor alters a variable in its cache without immediately writing the changed value back to the corresponding shared memory location. A second processor, which reads a variable from shared memory after a first one has changed its cache, but before the changed value is written back to common memory, receives therefrom an out-of-date value of the variable incorrect program execution leads.

To address this problem, so-called bus snooping units have been developed for such multiprocessor systems. Such a bus snooping unit is in each case associated with a microprocessor or its cache memory. One of its tasks is to monitor read access by processors other than the one to which it is assigned, whether they are addressing a memory address of which a copy is stored in the associated cache, and, if so, memory access and cache the requesting processor with the contents of the corresponding cell instead of the contents of the requested shared memory cell. This ensures that the other processor receives a current variable value, even if this changed value is not yet written back to shared memory.

The use of a bus snooping unit in this manner only makes sense in a multiprocessor system when the shared memory is a random access memory. For a read-only memory, i. A memory whose contents are not changed by a processor accessing it, or at least not under normal operating conditions, makes no sense using a bus snooping unit in the manner described above, since the content of the latter is currently not available from the processors is changed and consequently no inconsistencies between cache and memory can arise.

Such read-only memory generally includes program instructions or parameters of an application program to be executed by a processor of the data processing system in a data processing system. Circuit defects or ionizing radiation may cause individual bits of such memory to change value over time, with the result that the application program is operating with incorrect parameter values - A -

the processor even executes incorrect program instructions. For data processing systems used in applications that depend on the safety of persons, for example, brake or engine control devices for motor vehicles, such errors must be avoided with certainty. It has therefore already been proposed that parameters and data of the application program of such a system, referred to below together as application data, be stored in an error correction code such as e.g. to store a Reed-Solomon or Hamming code coded form. The coding, when accessing a data word of this application data, allows it to detect whether it is correct or whether it contains erroneous bits and to correct the erroneous bits as long as they are not too numerous. The higher the number of redundant bits of the code, the greater the number of erroneous bits that can be corrected. the larger the number of bits that a coded data word is longer than an uncoded one.

As the number of bad bits in memory increases over time, the likelihood that a new error will occur in a data word that already has an error increases. Thus, over time, the probability increases that errors occur in a data word in a number that exceeds the correcting capability of the code used. This problem can be delayed by using a code with a higher number of correctable bit errors. However, this also requires an increased number of stored redundant bits, which increases the cost of the memory.

Advantages of the invention

A very high degree of reliability with low storage space according to the invention in a data processing system with at least one execution unit and an addressable memory, with which the execution unit communicates via an address bus and a data bus, and with a bus monitoring unit, which is set, a read access of the execution unit to recognize a given memory location of the memory and instead provide the processor with read access to an alternate memory location associated with the given memory, thereby ensuring that the alternate memory location contains a data word erroneously stored at the given memory location in corrected form. While an added bit error at the given memory location with already erroneous content could exceed the correction capability of the error correction code, this danger does not exist at the alternate memory location.

Alternatively, the high reliability is achieved in that the given memory space contains a data word coded with an error correction code and that the data processing system has a Includes means for checking the data word read from the given memory location for accuracy and, in the event of failure, correcting the data word and storing the corrected data word at the alternate memory location.

In one case as in the other case, the bus monitoring unit expediently has a table for storing at least any given address to which an alternative address is assigned.

The alternative storage location is preferably located in the memory which can be addressed by the execution unit. In practice, this memory is usually somewhat larger than the space requirement of an application program running on the data processing system, so that otherwise unused space is available which can be used as an alternative storage space without additional costs.

The bus monitoring unit can be arranged in the address bus between the execution unit and the memory in order to pass on the address of the alternative memory location to the memory instead of an address of the given memory location output by the execution unit. An address of the memory containing a defective data word which has been corrected and stored at an alternate address is thus never addressed in this embodiment. Alternatively, the bus monitoring unit can be arranged in the data bus between the execution unit and the memory in order to pass on the contents of the alternative memory space to the execution unit instead of the content of the given memory location output by the memory on the data bus. Although the defective memory location of the memory is still addressed here, the data word output therefrom from the memory does not reach the execution unit.

In order to avoid access conflicts in this embodiment, it is expedient that the alternative memory location is located in a second memory which can only be selected by the bus monitoring unit.

In particular, the alternate memory location may reside in an allocation table arranged to store entries each containing a given address and the data word read and corrected at the given address.

The high selection reliability of the memory is also achieved according to the invention by a method in which a data word stored at a given storage location of a memory with an error correction code is checked for accuracy, in the case of an error the data word is corrected and stored in an alternative memory location and then inserted Read access to the given Storage space is redirected to the alternate storage location.

For this purpose, the address of any given memory location to which an alternate memory location has been assigned can be stored in a table.

As a backup space, a previously used storage space of the memory can be selected. In this case, the address of the associated alternate memory location is expediently also stored in the table for each given memory location.

Alternatively, it is possible to accommodate the backup storage space for any given storage space even in the table.

A device for storing the corrected data word at the alternative storage location can be installed together with the memory in a data processing system, so that the storage can take place in each case promptly after detection of an error in a data word. However, it is also possible to connect such a device only temporarily to a data processing system in which the memory is built in order to correct incorrectly found data words from time to time and store them in alternate storage locations. Further features and advantages of the invention will become apparent from the following description of exemplary embodiments.

characters

Show it:

1 is a block diagram of a data processing system according to the invention according to a first, simple embodiment;

2 shows a further development of the data processing system of FIG. 1 with built-in

Data correction device;

FIG. 3 is a flow chart of an operating method of the data processing system of FIG. 2; FIG.

4 is a block diagram of a data processing system according to a second embodiment;

FIG. 5 shows a further development of the data processing system from FIG. 4 with built-in data correction device; FIG. and

6 shows a modification of the data processing system of FIG. 4. Description of the embodiments

1 shows a block diagram of a data processing system according to a first embodiment of the invention. It comprises a microprocessor 1 as an execution unit, a programmable read only memory such as a flash memory 2 containing application data of an application to be executed by the microprocessor, and an address bus 3 and a data bus 4, via which the microprocessor 1 to the memory 2 and various other units such as a read / write memory, input / output devices or the like. which, as known per se, are not shown in the figure.

The memory locations of the memory 2 comprise a larger number of bits than the width of the data words processed by the microprocessor 1; the surplus or redundant bits contain additional information obtained for each data word by a known error correction coding method, such as Reed-Solomon or Hamming coding, which allows a certain encoding-dependent number of bit errors in the memory location to be allocated capture and correct the erroneous bits.

In the data bus 4, a decoder 5 is arranged between the memory 2 and the microprocessor 1, which receives the contents of addressed memory cells from the memory 2, the above-mentioned memory cells. tion and correction possibly erroneous bits performs and a the data content of the addressed memory cell corresponding correct data word passes to the microprocessor 1 for processing.

In the address bus 3, a bus monitoring unit 6 is arranged between the microprocessor 1 and the memory 2, the internal structure of which is simplified here by an associative memory AS 7 and a switch 8 is shown. The associative memory AS is organized as a two-column list, of which one column, referred to here as left column 9, contains so-called defective addresses, and the second, right column 10 contains so-called fallback addresses uniquely assigned to the defective addresses. Normally, the switch 8, as shown in the figure, connects an address output of the microprocessor 1 directly to an address input of the memory 2. However, if an address output by the microprocessor 1 belongs to the defective addresses, the associative memory 7 recognizes this. outputs the alternate address assigned to the received defective address and sets the changeover switch 8 to apply the alternate address to the memory 2.

The operation of the data processing system of Fig. 1 is as follows. Immediately after fabrication of the system, the application data only partially fills the memory 2, as indicated in the figure by Schraffer. The addresses of unused memory cells are in the associative memory 7 as Alternative addresses 10 entered; Defective addresses are not registered. The associative memory therefore can not detect a match between addresses issued by the microprocessor 1 and defective addresses, and the switch 8 is always in the position shown in FIG.

After an operating time of the system specified by the manufacturer, a test device (not shown in FIG. 1) is connected directly to the address input and data output of the memory 2 via terminals 11, 12. The checking device successively reads all memory locations of the memory 2 occupied by application data and checks the read data encoded with the error correction code for accuracy. If a read memory cell proves to be faulty, the test unit reads via a connection 13 from the associative memory 7 a fallback address to which no defective address has yet been assigned, programs the corrected content of the defective memory cell to the found fallback address and carries the address of the erroneous memory cell in association with the alternate address in the left column 9 of the associative memory 7 a.

If after such a maintenance operation, the microprocessor 1 accesses this defective address, this is recognized by the associative memory 7, and this prevents by switching the switch 8, the relevant defective address is applied to the memory 2, and instead puts the assigned Nete alternate address from which the required by the processor data word can then be read correctly.

FIG. 2 shows a further developed modification of the embodiment of FIG. 1, in which the functions of the decoder 5 and the external checking unit are connected in a decoder unit 14 permanently integrated into the system. The decoder unit 14 has a data input / output 15, which is connected to the data bus 4, an input 16, which receives the associated redundant bits for each data word output from the memory 2, an address input 17, which is connected to the address bus 3, and is arranged to control a breaker switch 18, which is arranged in the data bus 4 between the microprocessor 1 and the memory 2.

The operation of this modification will be explained with reference to the flowchart shown in FIG. The first method step S1 of the flowchart is a read access RDx of the microprocessor to a memory location of the memory 2 with the address x. The address x is received by the associative memory 7 of the bus monitoring unit 6 and compared with the stored defective addresses of the left column 9 (S2). If no match is found with a defective address, the switch 8 remains in the normal position shown in FIG. 2 and passes the address x to the memory 2 (S3). Otherwise, the switch 8 is switched over and instead of the recognized as defective address x an alternate address AS (x) assigned to it is applied to the memory 2. The memory 2 thus supplies as the data word W in the former case the content [x] of the memory location x, in the latter the content [AS (x)] of the alternate address AS (x) on the data bus 4 (S4).

In step S5, the decoder unit 14 checks whether the output data word W is free of bit errors. If so, it is passed to the microprocessor 1 and it processes it in step S9. If not, the decoder unit 14 opens the breaker switch 18 to prevent the microprocessor 1 from receiving the erroneous value W, and enters the address x among the defective addresses in the left column of the associative memory 7 (S6). At the same time, it uses the redundant bits to determine the correct value EC (W) of the data word W and enters it in an alternative memory location of the memory 2 whose address AS (x) assigned to the address x already precedes the right column of the associative memory 7 finds registered addresses of free memory locations. Simultaneously with the write access to the address AS (x) in step S8, the decoder unit 14 also closes the breaker switch 18 so that the microprocessor receives the corrected data word W and processes it in the next step S9.

Fig. 4 shows a block diagram of a second embodiment of the present invention. microprocessor Sensor 1 and memory 2 are the same as in the previously considered embodiment, and bus monitoring unit 6 again contains an associative memory 7 organized as a two-column list whose left column 9 is provided to store defective addresses. However, a switch 19 controlled by the associative memory 7 is not arranged here in the address bus 3 but in the data bus 4 between the memory 2 and the microprocessor 1 and connects the microprocessor 1 either to the memory 2 or to a data output of the associative memory 7.

In a newly manufactured data processing system according to the embodiment of FIG. 4, the associative memory 7 is completely empty. After a predetermined operating time, a test device 20 is also connected to the memory 2 via terminals 11, 12 in order to read the data stored therein, including redundant bits, and to check for freedom from errors. If an error is detected, the checking unit 20 enters in the left column 9 of the associative memory 7 the address of the erroneous memory location and in the right column 10 the corrected content of this memory location. At memory 2, no change is made. Therefore, it is not necessary for the applicability of this embodiment that the application occupies the memory 2 only incomplete, nor that this is reprogrammable. When the associative memory 7 recognizes a defective address registered in its left-hand column 9 among the addresses output by the microprocessor 1, it connects its output to the data bus 4 via the switch 8 and supplies to the microprocessor 1 the corresponding correct data value stored in its right-hand column 10 ,

Fig. 5 shows a similar to Fig. 3 modification of the data processing system of FIG. 4, with a decoder unit 14, which performs the functions of the decoder 5 and the test device 20. The operation of the system is essentially the same as described with reference to FIG. 3, except that in step S8 the corrected data W does not refer to an existing entry ASr (x) in the right column of the associative memory 7 Memory space of the memory 2 is written, but is itself registered at the corresponding location of the associative memory 7.

FIG. 6 shows a further modification of the embodiment of FIG. 4, in which the changeover switch 19 controlled by the associative memory 7 is omitted and instead the output of the associative memory 7 is connected to the data bus 4 in parallel to the memory 2. An R / W signal line 21 assumes the level 1 when the microprocessor 1 writes to a memory cell, and the level 0 when it reads. In this R / W line, an OR gate 22 is arranged so that an input gear with the microprocessor 1, a second input to the associative memory 7 and the output to the memory 2 is connected. When the microprocessor 1 read accesses a defective address recorded in the associative memory 7, the input of the OR gate 22 connected to the associative memory goes to level 1, and consequently the memory 2 also receives the level 1, which gives it a write address. The memory 2 thus outputs no data so that the associative memory 7 can output the data address assigned to the defective address undisturbed to the data bus 4.

The assignment of the associative memory 7 to data is done in the same way as described with reference to FIG. 4 and therefore need not be explained again.

A further development of the system of FIG. 6 with integrated decoder unit 14 will be apparent to those skilled in the art from the examples of FIGS. 2 and 5.

Claims

claims

A data processing system comprising at least one execution unit (1) and an addressable memory (2) to which the execution unit (1) communicates via an address bus (3) and a data bus (4), and to a bus monitoring unit (6) to recognize a read access of the execution unit (1) to a given memory location of the memory (2) and to instead provide the processor (1) read access to an alternate memory location associated with the given memory space, characterized in that the given memory location is one encoded with an error correction code , faulty

Data word contains and the alternate memory location contains the same data word in corrected form.

2. Data processing system having at least one execution unit (1) and an addressable memory (2) to which the execution unit (1) via an address bus (3) and a data bus (4) communicates, and with a bus monitoring unit (6) which is set up to recognize a read access of the execution unit (1) to a given memory location of the memory (2) and instead to provide the processor (1) with a read to provide access to an alternate storage location associated with the given storage space, characterized in that the given storage space includes a data word encoded with an error correction code, and the data processing system includes means (14) for checking the data word read from the given storage space for accuracy and, in the case of Includes error, correcting the data word and storing the corrected data word at the alternate memory location.

Data processing system according to one of the preceding claims, characterized in that the bus monitoring unit (6) has a table (7) for storing at least any given address associated with an alternate address.

4. Data processing system according to one of the preceding claims, characterized in that the alternative storage location is located in the addressable by the execution unit memory (2).

5. Data processing system according to one of the preceding claims, characterized in that the Busuberwachungseinheit (6) in the address bus (3) between execution unit (1) and memory (2) is arranged in place of one of the execution unit (1) output address of the given memory location the address of the soft memory space to the memory (2) pass.

6. Data processing system according to one of claims 1 to 3, characterized in that the bus monitoring unit (6) in the data bus (4) between the execution unit (1) and memory (2) is arranged to instead of the memory (2) on the Data bus (4) output contents of the given

Memory space to pass the content of the backup storage space to the execution unit (1).

7. Data processing system according to claim 6, characterized in that the alternative memory location is located in a selectable only by the bus monitoring unit (6) second memory (10).

8. Data processing system according to claim 6 or 7, characterized in that the alternative memory location is in a mapping table (7), which is set up to feed erhern of entries, each containing a given address and the read at the given address and corrected data word ,

A method of improving the security of a memory (2), wherein a data word stored at a given memory location of the memory (2) having an error correction code is checked for accuracy (S5), in case of an error the data word is corrected (S7) and stored in an alternate memory location (S8), and then a read access to the given memory space is diverted to the alternate memory location (S1, S2, S4).

10. The method according to claim 9, characterized in that the address of each given memory space to which an alternative memory location has been assigned is stored in a table (S6).

11. The method according to claim 9 or 10, characterized in that a previously unused space of the memory (2) is selected as a backup memory space.

12. The method according to claim 11, characterized in that the address of the associated alternative memory location is also stored in the table for each given memory location.

13. The method according to claim 10, characterized in that the alternative storage location is arranged for each given storage location in the table.

14. The method according to any one of claims 9 to 13, characterized in that means (14) for storing the corrected data word at the alternative memory location is installed together with the memory (2) in a data processing system.

15. The method according to any one of claims 9 to 13, characterized in that means (14) for storing the corrected data word at the alternative storage location temporarily to a data processing system in which the memory (2) is installed, is connected.