WO2007029391A1

WO2007029391A1 - Calculation function-equipped memory control device and memory device

Info

Publication number: WO2007029391A1
Application number: PCT/JP2006/311996
Authority: WO
Inventors: Junichi Kuchinishi; Akira Maruko; Daigo Senoo
Original assignee: Matsushita Electric Industrial Co., Ltd.
Priority date: 2005-09-09
Filing date: 2006-06-15
Publication date: 2007-03-15

Abstract

A calculation which has been conventionally executed in a correction device (30) is executed in a memory device (10) or a memory control device (20). Thus, adjustment which has been conventionally required when reading and writing data from/into a memory should be executed only when starting a calculation.

Description

Specification

Memory control device with arithmetic function and memory device

Technical field

The present invention relates to a memory control device and a memory device, and more particularly to a memory system that performs operations such as error correction on memory data. Background art

[0002] As video information having a large amount of information is recorded / reproduced and transmitted as digital signals, error detection and correction is performed to increase the reliability of recorded information or transmitted information. Is essential. In addition, because of its large capacity, high-speed processing is required.

[0003] Such a system, for example, a system for performing an error correction operation of an optical disk device, stores data before correction in a large-capacity buffer memory and repeats reading and writing of the buffer memory a plurality of times. It is common to perform error detection and correction. For example, optical disks such as CD and DVD use DRAM as buffer memory to detect and correct errors.

[0004] For example, in a DVD or the like, it is often necessary to perform correction processing and data output at the same time while reading from a disc. In such a system, since there are a plurality of devices that simultaneously read from and / or write to the memory device, a memory control device that performs arbitration of access to the memory device from each device is placed in the system. Access to is not performed directly by each device but via the memory controller.

FIG. 5 illustrates the processing time and the data flow between devices when correcting memory data in such a system.

[0006] Hereinafter, the time from when the memory control device 20 issues a command until the access is actually started is referred to as arbitration time, and the time from when the memory control device 20 performs the memory access to completion is referred to as the access time. .

[0007] First, the correction device 30, which is an arithmetic device related to error detection and correction, includes a memory control device 2 For 0, pass the address of the data you want to read and issue a data read command. The memory control device 20 starts reading data from the memory device 10. Here, arbitration time for the read command is required first.

Subsequently, the memory control device 20 performs reading from the memory device 10. Here, memory access time for reading is required.

The read data returns to the correction device 30 via the memory control device 20. Correction device 3

At 0, necessary calculations are performed on the read data. Here, computation time is required.

[0010] The correction device 30 passes the address of the data to be written and the corrected data to the memory control device 20, and issues a data write command. The memory control device 20 writes data to the memory device 10. Again, arbitration time for the write command is required.

[0011] Finally, the memory control device 20 performs writing to the memory device 10, and the memory device 10 stores data. Here, memory access time for writing is required.

As described above, in order to correct the memory data, in addition to the calculation time, the arbitration time for each read / write and the read / write access time are required.

[0013] By the way, there are memory devices that have a calculation function, particularly a correction function. The purpose of this is to reduce the occurrence of memory cell soft errors by performing a correction operation when refreshing inside the memory device, but in order to improve the performance of the memory system, the memory device performs the operation. It's not that. (See Patent Document 1).

Patent Document 1: Japanese Patent Application Laid-Open No. 62-54892

Disclosure of the invention

Problems to be solved by the invention

[0014] In a memory system that performs operations such as error correction on memory data, in order to improve the processing speed, for example, in the case of an optical disc, to improve the playback speed, the calculation time, the read / write arbitration time, Need to shorten or reduce read / write access time. [0015] For example, if a dedicated memory device is used for each correction step, arbitration becomes unnecessary, so that the processing time can be reduced. However, the circuit scale of the memory device increases, and The strike will be high.

Means for solving the problem

In order to solve the above-described problem, in the present invention, a calculation that has been performed in a conventional correction device is performed in a memory control device or a memory device.

The invention's effect

[0017] By performing operations such as error correction in the memory control device or the memory device, the arbitration required for each of the conventional read and write operations can be performed without a significant increase in circuit. It can be reduced only at the start of calculation. Therefore, the processing time can be shortened, and the processing speed of the entire memory system can be improved.

Brief Description of Drawings

FIG. 1 is an operation explanatory diagram of a memory system provided with a memory control device according to the present invention.

FIG. 2 is a block diagram showing a configuration example of a memory control device according to the present invention.

FIG. 3 is an operation explanatory diagram of a memory system including a memory device according to the present invention.

FIG. 4 is a block diagram showing a configuration example of a memory device according to the present invention.

FIG. 5 is an operation explanatory diagram of a conventional memory system.

Explanation of symbols

[0019] 10 memory device

11 Memory cell array

12 sense amplifier

13 Selector

14 Refresh control circuit

15 Output data buffer

16 input data buffer

17 Arithmetic circuit 20 Memory controller

21 flip-flop

22 Selector

23 Arithmetic unit

30 Correction device

BEST MODE FOR CARRYING OUT THE INVENTION

[0020] FIG. 1 shows a case where an operation performed by the correction device 30 is performed by the memory control device 20.

The processing time and the data flow between the devices 10, 20, 30 are described.

First, the correction device 30 passes to the memory control device 20 the type of operation to be performed and one of the operation target data, and issues a data operation command. The memory control device 20 starts reading data from the memory device 10. Here, first, mediation time for the calculation command is required.

Next, the read data is held in the memory control device 20. The memory control device 20 performs a specified operation on the stored data. Here, computation time is required.

[0024] The memory control device 20 performs writing to the memory device 10, and the memory device 10 stores the data. Here, memory access time for writing is required.

[0025] As described above, since the memory control device 20 continuously performs reading, calculation, and writing, no new arbitration time is required. Therefore, in order to correct the memory data, in addition to the calculation time and the read / write access time, only the arbitration time for one calculation command is required. In other words, mediation time can be reduced compared to the conventional case.

With reference to FIG. 2, the configuration of the memory control device 20 with an arithmetic function according to the present invention will be described. 2 includes a flip-flop 21, a selector 22, and an arithmetic device 23. The flip-flop 21 is a means for temporarily storing data therein. When reading data, the selector 22 at the input of the flip-flop 21 selects data from the memory device 10, and the data from the memory device 10 is stored in the flip-flop 21 over time. The data is retained until the correction device 30 reads it.

[0028] When writing data, the selector 22 at the input of the flip-flop 21 selects the data from the correction device 30 if it is a write command from the correction device 30, for example, and the data to be written is It is temporarily stored in the flip-flop 21. Data is retained until it is written to memory device 10.

[0029] In the case of a data operation command, the selector 22 at the input of the flip-flop 21 selects data from the correction device 30 if the operation command is from the correction device 30, for example. Is temporarily stored in Subsequently, when the data from the arithmetic unit 23 is selected by the selector 22 and the data is read from the memory unit 10, the arithmetic result is stored in the flip-flop 21. Subsequently, when data is written to the memory device 10, the memory data calculation is completed.

[0030] As shown in FIG. 2, by simply adding the selector 22 and the arithmetic unit 23 to the conventional memory control device, as shown in FIG. This makes it possible to reduce the processing time of the entire memory system. Furthermore, since it is guaranteed that reading and writing are always performed continuously, for example, when DRAM is used as the memory device 10, page access becomes possible, so that access time can be minimized. .

FIG. 3 illustrates the processing time and the data flow between the devices 10, 20, and 30 when the calculation performed by the correction device 30 is performed by the memory device 10.

Subsequently, the memory control device 20 controls the memory device 10 to perform a calculation operation. Based on the information from the memory control device 20, the memory device 10 performs its own reading, calculation, and writing, and the processing is completed. Inside the memory device 10, read and write Access time is required. Furthermore, calculation time is also required.

[0034] As described above, since the memory device 10 sequentially performs reading, calculation, and writing, no new arbitration time is required. Therefore, in order to correct the memory data, in addition to the calculation time and the read / write access time, only the arbitration time for the calculation command is required. That is, the mediation time can be reduced compared to the conventional case.

The configuration of the memory device 10 with an arithmetic function according to the present invention will be described with reference to FIG. Here, it is assumed that the memory device 10 is a memory that requires data reading and writing called refresh operation at regular intervals called DRAM. In FIG. 4, 11 is a memory cell array, 12 is a sense amplifier, and the sense amplifier 12 determines the potential of the data stored in the memory cell array 11 and outputs the determination result. A selector 13 selects input / output data for the memory cell array 11. Reference numeral 14 denotes a refresh control circuit that controls the refresh operation of the DRAM. 15 is an output data buffer, and 16 is an input data buffer. Reference numeral 17 denotes an arithmetic circuit.

In the case of writing data, data input from the input data buffer 16 is written to the memory cell array 11.

When reading data, the data in the memory cell array 11 is taken out, the potential is determined by the sense amplifier 12, the necessary data is selected by the selector 13, and sent to the output data buffer 15.

In addition, refresh is performed in order to maintain the storage state of the memory cell array 11. At the time of refresh, the refresh control circuit 14 refreshes predetermined data in the memory cell array 11. In that case, the potential of the data from the memory cell array 11 is determined by the sense amplifier 12 and stored in the memory sensing array 11 again.

At the time of calculation, the potential from the data from the memory cell array 11 is determined by the sense amplifier 12, sent to the calculation circuit 17, and stored again in the memory cell array 11, and the operation is repeated.

[0040] Here, the operation is almost the same in that the data is read from the memory cell array 11 and stored again at the time of calculation and at the time of refresh, and a little circuit is added to the arithmetic circuit 17 in the conventional memory device. Thus, the memory device 10 having the configuration of the present invention can be obtained. In the above description, the calculation is performed by the error correction system. However, any calculation can be performed between the data in the memory device 10 and some data, and the memory device 10 or the memory control device 20. By carrying out the above, the processing time can be shortened in the same manner. Industrial applicability

[0042] As described above, the memory control device with an arithmetic function and the memory device according to the present invention have an effect that the processing speed of the entire memory system can be improved. Useful as.

Claims

The scope of the claims

[1] a memory device;

A memory control device that arbitrates reading and writing to the memory device;

A memory system comprising an arithmetic device for performing arithmetic operations on data on the memory device,

When an operation is performed on the data read from the memory device and the data from the arithmetic device, and the operation result is written back to the memory device, the read data and the arithmetic device A memory system, wherein an operation with data is performed by the memory control device or the memory device.

[2] The memory system according to claim 1,

The arithmetic device is a correction device for performing error correction arithmetic on data on the memory device;

The memory control device or the memory device performs an error correction operation based on data read from the memory device and data from the correction device.

[3] a memory device;

In a memory system comprising an arithmetic device for performing arithmetic operations on data on the memory device,

When an operation is performed on the data read from the memory device and the data from the arithmetic device, and the operation result is written back to the memory device, the read data and the arithmetic device A memory control device that performs operations with data by itself.

[4] The memory control device according to claim 3,

The memory control device performs an error correction operation based on data read from the memory device and data from the correction device.

[5] a memory device;

When an operation is performed on the data read from the memory device and the data from the arithmetic device, and the operation result is written back to the memory device, the read data and the arithmetic device A memory device characterized by its own operation with data.

[6] The memory device according to claim 5,

The memory device performs an error correction operation based on data read from the memory device and data from the correction device.