WO2007028942A1

WO2007028942A1 - Time-triggered co-operative hardware scheduler

Info

Publication number: WO2007028942A1
Application number: PCT/GB2006/003007
Authority: WO
Inventors: Zemian Mark Hughes; Michael Joseph Pont
Original assignee: The University Of Leicester
Priority date: 2005-09-09
Filing date: 2006-08-14
Publication date: 2007-03-15
Also published as: GB0518364D0

Abstract

The invention concerns a time-triggered co-operative (TTC) hardware scheduler, for use with a central processing unit (CPU) (13). The scheduler comprises: a clock tick input means; an update means (11) for determining which, if any, tasks are due to be initiated on the next clock tick input; and a dispatch means (12) for instructing the CPU (13) to run the tasks when they are due.

Description

TIME-TRIGGERED CO-OPERATIVE HARDWARE SCHEDULER

Technical Field

This invention relates to the design of a time-triggered co-operative hardware scheduler specifically for use with processors employing time-triggered software. A particular aim is to increase the reliability of processors employed in embedded systems.

Background Art

Embedded processors are ubiquitous: they form a core component of a vast range of everyday items (cars, aircraft, medical equipment, factory systems, mobile phones, DVD players, music players, microwave ovens, toys etc). In some cases several embedded processors may be employed, each for a specific function. For example, a typical modern car may contain around fifty embedded processors.

In applications where safety is an important consideration - such as in automotive systems - it is vital that a reliable processor is used and that it operates in a highly predictable manner. For instance, when a driver presses the brake pedal on a car, he/she needs to be assured that the related processor will operate within an appropriate time-interval to initiate slowing the car. Thus, in safety applications or other time-critical systems it is important that a processor with a predictable timing feature is used.

Over recent years, the issue of reliability in embedded systems has been addressed in various ways by employing time-triggered software solutions. The Applicants have themselves been involved in creating such software for industry-standard hardware platforms such as the 8051 micro-controller, ARM™ processor and PC platform. Developing reliable applications using this approach can be effective, but there is a mismatch between generic processor architectures and time-triggered software designs. For example, most processors support a wide range of interrupts, while the use of a (pure) time-triggered software architecture generally requires that only a single interrupt can be supported by each processor. This leads to software design 'guidelines', like the 'one interrupt per micro-controller rule' . Such guidelines can be adhered to by use of appropriate tools in software creation. However, it is possible for changes to be made to the software (for example, during software maintenance or upgrades) that lead to the creation of unreliable systems.

More specifically, a standard processor employing time-triggered cooperative (TTC) scheduling software works by splitting up the time of the shared processor resource into tick intervals of typically 1 millisecond. Tasks are initialised at system start up to be executed either periodically, e.g. every 3 milliseconds or ticks, as illustrated by task A in Figure 1, or as one shot tasks where they run only once. In a true co-operative system, each task must finish and pass control back to the scheduler before the next task is run.

The tasks are initialised using a software function like that shown in Figure 2, called SCH_Add_Task. In this example, line 20 of the code initialises a Task A with a '0' delay and a '3' millisecond period. Line 21 defines an element in a Task Array. Line 22, defines a pointer (or address) to the task and this must be a 'void (void)' function. Line 23 defines a delay or number of clock ticks before the function will (next) be run. Line 24 defines an interval or number of clock ticks between subsequent runs. Line 25 defines a task array. Thus, the function address, delay before the task is executed and the period of execution are stored in the task array.

A conventional timer has prescaler reload and count registers to bring down the high onboard clock frequency of (for example) 50Mhz to a reasonable value to make good use of the available bits in the timer reload and count registers. As shown in Figure 3, the prescaler count register is decremented every onboard clock cycle. When this register reaches an underflow (i.e. less than '0'), a tick is set high and the prescaler reload value is placed in the prescaler count register. The timer registers operate in the same manner, but are instead driven by the clock tick input. On underflow of the timer count register, the interrupt pin is set high and the processor loads the default interrupt vector address and executes the Interrupt Service Routine (ISR) .

Thus, in operation, a conventional timer generates the only single interrupt enabled on the system, to run an update ISR. The ISR counts down the delay values of the tasks within the task array. The ISR then returns from the interrupt to a super loop program that checks for tasks with a delay value of '0' and calls them by jumping to the stored task address within the task array. Any '0' delay values are reloaded with the period value and once all scheduled tasks for that tick interval are executed, the processor is placed into a suitable idle mode to await the next timer interrupt.

However, if there are programming errors in the ISR or the task array this processor will not operate in a reliable and predictable manner. In addition, using a standard processor in a time-triggered system requires a significant amount of memory for the time-triggered software. In general, there is a correlation between memory size and cost for such devices, thus the embedded processor described above would entail significant costs.

It is therefore an object of the present invention to provide improved processor hardware for use with time-triggered software, which alleviates the aforementioned problems.

Disclosure of Invention

In accordance with the present invention there is provided a time-triggered co-operative (TTC) hardware scheduler, for use with a central processing unit (CPU), comprising: a clock tick input means; an update means for determining which, if any, tasks are due to be initiated on the next clock tick input; and a dispatch means for instructing the CPU to run the tasks when they are due.

Thus, the present invention provides a hardware scheduler that has been designed specifically to support time-triggered software. In particular, scheduler and system functions, traditionally incorporated into software, have been implemented within the hardware. Consequently, this system eliminates the need for much of the traditional scheduler code, and the opportunity for programming errors is significantly reduced. This increases the reliability of the system, reduces the required program size and therefore reduces the required memory size and attendant cost of the device. Thus, a TTC processor employing a TTC hardware scheduler, according to the present invention, provides an effective solution to the aforementioned problems.

In a preferred embodiment, the update means comprises: registers for storing information about one or more tasks to be performed; at least one register for each task containing a variable value; means for automatically altering the contents of the variable value registers; means for checking the contents of the variable value registers; and means for initiating an action when the value of a variable value register equals a defined value.

More preferably, the variable value registers are initially set to a desired delay period for each task, the automatic altering means acts to count down from this delay value, and when the variable value register reaches zero delay, the task is initiated.

Even more preferably, non-variable value registers are initialised with the desired delay period for each task, and when the associated variable value register reaches zero delay, and the task is initiated, the desired delay is reloaded from the non- variable value register into the variable value register.

In another preferred embodiment of the invention, the update means comprises: a clock tick input means, task count and reload registers for each task that may be run, a task list which identifies tasks due to run in the coming tick interval, and a cycle complete flag. Each clock tick input drives each individual task count register to decrement. If a task count register reaches an underflow, the task is "flagged" in the task list to indicate that that task is due to run in the coming tick interval, and that task count register is loaded with its reload value. When all task count registers have been decremented and reloaded if necessary, and all tasks, if any, due to run in the coming tick interval have been identified in the task list, the cycle complete flag is set.

In an alternative embodiment of the invention, the update means comprises: a clock tick input means, task count and reload registers for each task that may be run, a task list which identifies tasks due to run in the coming tick interval, and an interrupt pending flag. Each clock tick input drives each individual task count register to decrement. If a task count register reaches an underflow, the task is identified in the task list to indicate that that task is due to run in the coming tick interval, and that task count register is loaded with its reload value. When all task count registers have been decremented and reloaded if necessary, and all tasks, if any, due to run in the coming tick interval have been identified in the task list, the interrupt pending flag is set, if there are any tasks in the task list that are due to run.

Preferably, the dispatch means comprises: an input means, registers for storing information about one or more tasks to be performed, at least one register for each task containing a task identification, means for automatically checking a task list, and means for initiating an action when a task that is due to run is found in the task list.

More preferably, the input means is a cycle complete flag, and if set, the dispatch means checks the task list, and if any tasks that are due to run are found in the task list, an interrupt is sent to a central processing unit along with the task identification, to initiate the task.

Alternatively, the input means is an interrupt pending flag, and if set, the dispatch means checks the task list and sends an interrupt signal to a central processing unit along with the task identification, to initiate the task.

Preferably, once a task is complete and the dispatch means receives a task complete signal from the central processing unit, the dispatch means checks for any tasks in the task list that are still to be run, and if any are found, an interrupt is sent to a central processing unit along with the task identification, to initiate the task.

In another preferred embodiment of the invention, the dispatch means comprises: a cycle complete flag input means, task identification registers for each task that may be run, an interrupt flag, and a task complete input means. When the cycle complete flag is set, the task list is checked and if a task that is due to run is found in the task list, the interrupt flag is set and transmitted to a central processing unit along with the task identification. The central processing unit is then required to execute the identified task by means of an appropriate Interrupt Service Routine. When the task complete flag is detected, upon completion of the task by the central processing unit, the dispatch means checks for any remaining tasks in the task list and follows the above operation until all tasks in the list (that are due to run) are complete.

In another preferred embodiment of the invention, the dispatch means comprises: a cycle complete flag input means, an interrupt flag, and a task complete input means. When the cycle complete flag is set, the task list is checked and if a task is found to be due to execute, the interrupt flag is set and transmitted to a central processing unit along with the task identification. The central processing unit is then required to execute the identified task by means of an appropriate Interrupt Service Routine. When the task complete flag is detected, upon completion of the task by the central processing unit, the dispatch means checks the task list again and follows the above operation until all tasks (that are due to run) in the list are complete.

In an alternative embodiment, the dispatch means comprises: an interrupt pending flag input means, task identification registers for each task that may be run, an interrupt flag, and a task complete input means. When the interrupt pending flag is set, the task list is checked, and the interrupt flag is set and transmitted to a central processing unit along with the task identification. The central processing unit is then required to execute the identified task by means of an appropriate Interrupt Service Routine. When the task complete flag is detected, upon completion of the task by the central processing unit, the dispatch means checks for any remaining tasks in the task list and follows the above operation until all tasks in the list are complete.

In a preferred embodiment, the time-triggered co-operative hardware scheduler is comprised in a self-contained unit adapted to be linked to an external central processing unit by means of a suitable data bus.

In an alternative embodiment, the time-triggered co-operative hardware scheduler is integrated within a central processing unit. Brief Description of the Drawings

Figure 1 is a schematic illustration of task scheduling in a standard processor known from the prior art.

Figure 2 is an example of a task initialising software function known from the prior art.

Figure 3 is a schematic illustration of operation of a conventional timer in a standard processor known from the prior art.

Figure 4 is a schematic representation of a TTC hardware scheduler, according to the present invention.

Figure 5 is a schematic illustration of operation of an update unit, according to the present invention.

Figure 6 is a schematic illustration of operation of a dispatch unit, according to the present invention.-

Figure 7 is a schematic illustration of task scheduling using a TTC hardware scheduler, according to the present invention.

Detailed Description of the Invention

The Applicants realised that a conventional task array, traditionally formed through a software function like that of Figure 2, resembled something similar to a traditional timer and interrupt system, shown in Figure 3; with the task address being akin to an interrupt vector, the delay being akin to the timer count value and the period being akin to the timer reload value. Thus, it was proposed that this form of scheduling could be generated in hardware, using a modified timer and enough registers for each task. This would eliminate the need for much of the scheduler code and therefore reduce memory requirements, increasing execution time and reliability. Thus forming the basic concept of the TTC hardware scheduler of the present invention.

Referring to the drawings, a time-triggered co-operative (TTC) hardware scheduler 10, according to the present invention, is illustrated in Figure 4. This comprises an update unit 11 in communication with a dispatch unit 12. The TTC hardware scheduler 10 is itself in communication with a central processing unit (CPU) 13. As shown in this example, the TTC hardware scheduler 10 may be formed as a discrete unit that can be linked to an existing CPU 13. Alternatively, the TTC hardware scheduler 10 may be fully integrated with a bespoke CPU 13.

A schematic representation of the update unit 11 is illustrated in Figure 5. The purpose of the update unit 11 is to determine which tasks should be run in the next clock tick interval. Thus, as illustrated, the clock input causes the task count registers to be decremented periodically. This is typically at a rate of IkHz, but can be user defined. Whenever an individual task count register reaches an underflow, a task list is updated to identify that particular task and the task reload value is added to the task count register. Once all task count registers have been decremented and reloaded if necessary, and all tasks, if any, due to be executed have been identified in the task list, a TDone flag will be set. Thus, in this example the TDone flag is equivalent to a cycle complete flag and indicates that all task count registers have been decremented, regardless of whether there are any tasks due to run in the task list. A further refinement could be to only set TDone if there are tasks due to be run in the coming tick interval. In this case, TDone would be equivalent to an interrupt pending flag. However, this operation would require more logic gates.

In the example shown, the TDone flag and the task list are then communicated to the dispatch unit 12, as shown in Figure 6. Upon detection that TDone is set, the task list is checked and if a task that is due to run is found in the task list, an interrupt flag is set and transmitted to a CPU 13 along with the task identification. The CPU 13 is then required to execute the identified task by means of an appropriate Interrupt Service Routine (ISR). While the task is being executed, operation of the dispatch unit 12 is paused until the CPU 13 sets a task complete flag. The dispatch unit 12 then checks for any remaining tasks in the task list and follows the above operation until all tasks in the list are complete. This allows the dispatch unit 12 to schedule more than one task in any given tick interval, as shown in Figure 7. However, to ensure reliable operation of the device, all tasks due to be run during the same tick interval must either be able to complete within that tick interval or additional safety mechanisms must be employed.

Naturally, implementing the scheduling functionality into the hardware of a system will reduce the code requirements. The only scheduling functions required to be coded into the present scheduler relate to adding tasks by loading values to the registers and starting the timer. Also, as the task data is stored in registers, there is no need for a task array to be stored in data RAM. The Applicants have devised a system whereby the code required is 1.5 times smaller and the data 12.5 times smaller than in a conventional system. This can have a huge impact in many systems when considering the large equivalent number of gates required for generating RAM.

Table 1 below highlights the differences between the software requirements for a simple application built using a conventional processor implementation and a TTC hardware scheduler implementation.

Table 1

In order to compare the scheduler loads of both a conventional and TTC hardware scheduler implementation, the Applicants created a test implementation. From this, they noted that the scheduler load of the conventional system is almost three times that of the TTC device. Also, it was noted that the conventional system (with only one task assumed, running at 25MHz), utilised 7.84μs of the tick interval whereas a similar task on a TTC system utilised only 2.84μs of the tick interval.

A TTC hardware scheduler 10, according to the present invention, therefore provides a hardware-based replacement for a software-based 'time-triggered co-operative scheduler' (or 'cyclic executive'), which is employed in many embedded systems. Use of such a TTC hardware scheduler 10 simplifies the process of implementing a scheduler in the system in question. It also reduces the opportunities for coding errors that can make the system behaviour much less easy to predict. Thus, used in the manner described, a TTC hardware scheduler 10 is likely to result in the creation of embedded systems with more predictable patterns of behaviour. Use of a TTC hardware scheduler 10 is also likely to reduce memory requirements (for both data and code) for the application. It will also offer the potential for system power savings with some task combinations.

Claims

1. A time-triggered co-operative hardware scheduler, for use with a central processing unit (CPU), comprising: a clock tick input means; an update means for determining which, if any, tasks are due to be initiated on the next clock tick input; and a dispatch means for instructing the CPU to run the tasks when they are due.

2. A time-triggered co-operative hardware scheduler of Claim 1 wherein the update means comprises: registers for storing information about one or more tasks to be performed; at least one register for each task containing a variable value; means for automatically altering the contents of the variable value registers; means for checking the contents of the variable value registers; and means for initiating an action when the value of a variable value register equals a defined value.

3. A time-triggered co-operative hardware scheduler of Claim 2 wherein the variable value registers are configured to be initially set to a desired delay period for each task, the automatic altering means being configured to count down from this delay value, so that when the variable value register reaches zero delay, the task is initiated.

4. A time-triggered co-operative hardware scheduler of Claim 3 wherein non-variable value registers are configured to be initialised with the desired delay period for each task, so that when the associated variable value register reaches zero delay, and the task is initiated, the desired delay is reloaded from the non-variable value register into the variable value register.

5. A time-triggered co-operative hardware scheduler of Claim 1 wherein the update means comprises: task count and reload registers for each task that may be run, a task list which identifies tasks due to run in the coming tick interval, and a cycle complete flag, wherein each clock tick input drives each individual task count register to decrement; and wherein the scheduler is configured such that: if a task count register reaches an underflow the task is flagged in the task list to indicate that that task is due to run in the coming tick interval, and that task count register is loaded with its reload value; and when all task count registers have been decremented and reloaded if necessary, and all tasks, if any, due to run in the coming tick interval have been identified in the task list, the cycle complete flag is set.

6. A time-triggered co-operative hardware scheduler of Claim 1 wherein the update means comprises: task count and reload registers for each task that may be run, a task list which identifies tasks due to run in the coming tick interval and an interrupt pending flag, wherein each clock tick input drives each individual task count register to decrement; and wherein the scheduler is configured such that: if a task count register reaches an underflow, the task is flagged in the task list to indicate that that task is due to run in the coming tick interval, and that task count register is loaded with its reload value; and when all task count registers have been decremented and reloaded if necessary, and all tasks, if any, due to run in the coming tick interval have been identified in the task list, the interrupt pending flag is set if there are any tasks that are due to run in the task list.

7. A time-triggered co-operative hardware scheduler of Claim- 1 wherein the dispatch means comprises: an input means; registers for storing information about one or more tasks to be performed; at least one register for each task containing a task identification; means for automatically checking a task list; and means for initiating an action when a task that is due to execute is found in the task list.

8. A time-triggered co-operative hardware scheduler of Claim 7 wherein the input means comprises a cycle complete flag, and the dispatch means is configured, when the cycle complete flag is set, to check the task list, and if any tasks that are due to execute are found in the task list, to send an interrupt to a central processing unit along with the task identification, to initiate the task.

9. A time-triggered co-operative hardware scheduler of Claim 7 wherein the input means comprises an interrupt pending flag, and the dispatch means is configured to check the task list and send an interrupt signal to a central processing unit along with the task identification, to initiate the task.

10. A time-triggered co-operative hardware scheduler of Claim 8 or Claim 9 configured so that once a task is complete and the dispatch means receives a task complete signal from the central processing unit, the dispatch means checks for any tasks in the task list that are still to be run, and if any are found, an interrupt is sent to a central processing unit along with the task identification, to initiate the task.

11. A time-triggered co-operative hardware scheduler of Claim 1 wherein the dispatch means comprises: a cycle complete flag input means, task identification registers for each task that may be run, an interrupt flag, and a task complete input means; configured such that when the cycle complete flag is set, the task list is checked and if a task that is due to ran is found in the task list:

(i) the interrupt flag is set and transmitted to a central processing unit along with the task identification;

(ii) the central processing unit is then instructed to execute the identified task by means of an appropriate Interrupt Service Routine; and

(iii) when the task complete flag is detected, upon completion of the task by the central processing unit, the dispatch means is configured to check for any remaining tasks in the task list that are also due to run and to follow (i) to (iii) above until all tasks in the list that are due to ran are complete.

12. A time-triggered co-operative hardware scheduler of Claim 1, wherein the dispatch means comprises: a cycle complete flag input means, an interrupt flag, and a task complete input means configured such that when the cycle complete flag is set, the task list is checked and

(i) if a task is found to be due to execute, the interrupt flag is set and transmitted to a central processing unit along with the task identification,

(ii) the central processing unit is then instructed to execute the identified task by means of an appropriate Interrupt Service Routine, and

(iii) when the task complete flag is detected, upon completion of the task by the central processing unit, the dispatch means is configured to check the task list again and to follow (i) to (iii) above until all tasks in the list that are due to run are complete.

13. A time-triggered co-operative hardware scheduler of Claim 1 wherein the dispatch means comprises: an interrupt pending flag input means, task identification registers for each task that may be run, an interrupt flag, and a task complete input means; configured such that when the interrupt pending flag is set, the task list is checked, and

(i) the interrupt flag is set and transmitted to a central processing unit along with the task identification,

(iii) when the task complete flag is detected, upon completion of the task by the central processing unit, the dispatch means is configured to check for any remaining tasks in the task list that are due to run and to follow (i) to (iii) above until all tasks in the list that are due to run are complete.

14. A time-triggered co-operative hardware scheduler, as claimed in any preceding claim, comprised in a self-contained unit adapted to be linked to an external central processing unit by means of suitable data bus.

15. A time-triggered co-operative hardware scheduler, as claimed in any of claims 1 to 13, that is integrated within a central processing unit.

16. A time-triggered co-operative hardware scheduler, substantially as hereinbefore described, with reference to and as shown in Figures 4 through 7.