WO2007027671A3 - Scheduling mechanism of a hierarchical processor including multiple parallel clusters - Google Patents

Scheduling mechanism of a hierarchical processor including multiple parallel clusters Download PDF

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Publication number
WO2007027671A3
WO2007027671A3 PCT/US2006/033662 US2006033662W WO2007027671A3 WO 2007027671 A3 WO2007027671 A3 WO 2007027671A3 US 2006033662 W US2006033662 W US 2006033662W WO 2007027671 A3 WO2007027671 A3 WO 2007027671A3
Authority
WO
WIPO (PCT)
Prior art keywords
including multiple
multiple parallel
processor including
scheduling mechanism
hierarchical processor
Prior art date
Application number
PCT/US2006/033662
Other languages
French (fr)
Other versions
WO2007027671A2 (en
Inventor
Andrew F Glew
Original Assignee
Searete Llc
Andrew F Glew
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/215,833 external-priority patent/US20070083735A1/en
Priority claimed from US11/215,835 external-priority patent/US7644258B2/en
Application filed by Searete Llc, Andrew F Glew filed Critical Searete Llc
Priority to KR1020087007583A priority Critical patent/KR101355496B1/en
Priority to GB0805594A priority patent/GB2444455A/en
Publication of WO2007027671A2 publication Critical patent/WO2007027671A2/en
Publication of WO2007027671A3 publication Critical patent/WO2007027671A3/en

Links

Classifications

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    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G—PHYSICS
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    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
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    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
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    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
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    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
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    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G06F9/3828—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage with global bypass, e.g. between pipelines, between clusters
    • G—PHYSICS
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    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
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    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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    • G—PHYSICS
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    • G06F9/00—Arrangements for program control, e.g. control units
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    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3848—Speculative instruction execution using hybrid branch prediction, e.g. selection between prediction techniques
    • G—PHYSICS
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    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
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    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
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    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G06F9/3891—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
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    • G06F9/46—Multiprogramming arrangements
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    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Document Processing Apparatus (AREA)

Abstract

The abstract shall consist of a smmary of the disclosure as contained in the description, the claims, and the drawings; the summary shall indicate the technical field to which the inventino pertains and shall be drafted in a way which allows the clear understanding of the technical problem, the gist of the solution of that problem through the invention, and the principal use or uses of the invention.
PCT/US2006/033662 2005-08-29 2006-08-28 Scheduling mechanism of a hierarchical processor including multiple parallel clusters WO2007027671A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020087007583A KR101355496B1 (en) 2005-08-29 2006-08-28 Scheduling mechanism of a hierarchical processor including multiple parallel clusters
GB0805594A GB2444455A (en) 2005-08-29 2006-08-28 Scheduling mechanism of a hierarchical processor including multiple parallel clusters

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/215,833 US20070083735A1 (en) 2005-08-29 2005-08-29 Hierarchical processor
US11/215,835 US7644258B2 (en) 2005-08-29 2005-08-29 Hybrid branch predictor using component predictors each having confidence and override signals
US11/215,835 2005-08-29
US11/215,833 2005-08-29

Publications (2)

Publication Number Publication Date
WO2007027671A2 WO2007027671A2 (en) 2007-03-08
WO2007027671A3 true WO2007027671A3 (en) 2007-12-06

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/033662 WO2007027671A2 (en) 2005-08-29 2006-08-28 Scheduling mechanism of a hierarchical processor including multiple parallel clusters

Country Status (3)

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KR (1) KR101355496B1 (en)
GB (1) GB2444455A (en)
WO (1) WO2007027671A2 (en)

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US20150039859A1 (en) * 2011-11-22 2015-02-05 Soft Machines, Inc. Microprocessor accelerated code optimizer
KR101703401B1 (en) 2011-11-22 2017-02-06 소프트 머신즈, 인크. An accelerated code optimizer for a multiengine microprocessor
WO2013077872A1 (en) * 2011-11-22 2013-05-30 Soft Machines, Inc. A microprocessor accelerated code optimizer and dependency reordering method
US20140281391A1 (en) * 2013-03-14 2014-09-18 Qualcomm Incorporated Method and apparatus for forwarding literal generated data to dependent instructions more efficiently using a constant cache
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
KR102083390B1 (en) 2013-03-15 2020-03-02 인텔 코포레이션 A method for emulating a guest centralized flag architecture by using a native distributed flag architecture
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
WO2014150806A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for populating register view data structure by using register template snapshots
KR101708591B1 (en) 2013-03-15 2017-02-20 소프트 머신즈, 인크. A method for executing multithreaded instructions grouped onto blocks
KR20140126195A (en) * 2013-04-22 2014-10-30 삼성전자주식회사 Processor for batch thread, batch thread performing method using the processor and code generation apparatus for performing batch thread
KR102177871B1 (en) 2013-12-20 2020-11-12 삼성전자주식회사 Function unit for supporting multithreading, processor comprising the same, and operating method thereof
US9864700B1 (en) * 2016-08-17 2018-01-09 Advanced Micro Devices, Inc. Method and apparatus for power reduction in a multi-threaded mode

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US5592679A (en) * 1994-11-14 1997-01-07 Sun Microsystems, Inc. Apparatus and method for distributed control in a processor architecture
US6829764B1 (en) * 1997-06-23 2004-12-07 International Business Machines Corporation System and method for maximizing usage of computer resources in scheduling of application tasks

Also Published As

Publication number Publication date
GB0805594D0 (en) 2008-04-30
KR101355496B1 (en) 2014-01-28
KR20080043378A (en) 2008-05-16
GB2444455A (en) 2008-06-04
WO2007027671A2 (en) 2007-03-08

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