WO2007020274A3 - System and method for communicating instructions and data between a processor and external devices - Google Patents

System and method for communicating instructions and data between a processor and external devices Download PDF

Info

Publication number
WO2007020274A3
WO2007020274A3 PCT/EP2006/065372 EP2006065372W WO2007020274A3 WO 2007020274 A3 WO2007020274 A3 WO 2007020274A3 EP 2006065372 W EP2006065372 W EP 2006065372W WO 2007020274 A3 WO2007020274 A3 WO 2007020274A3
Authority
WO
WIPO (PCT)
Prior art keywords
processor
data
blocking
channels
communicating
Prior art date
Application number
PCT/EP2006/065372
Other languages
French (fr)
Other versions
WO2007020274A2 (en
Inventor
Michael Norman Day
Charles Ray Johns
John Samuel Liberty
Todd Swanson
Thuong Quang Truong
Original Assignee
Ibm
Ibm Uk
Michael Norman Day
Charles Ray Johns
John Samuel Liberty
Todd Swanson
Thuong Quang Truong
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/207,970 external-priority patent/US7778271B2/en
Priority claimed from US11/207,971 external-priority patent/US7500039B2/en
Application filed by Ibm, Ibm Uk, Michael Norman Day, Charles Ray Johns, John Samuel Liberty, Todd Swanson, Thuong Quang Truong filed Critical Ibm
Priority to EP06792852A priority Critical patent/EP1917600A2/en
Priority to CN200680030145XA priority patent/CN101243421B/en
Priority to JP2008526500A priority patent/JP5558713B2/en
Publication of WO2007020274A2 publication Critical patent/WO2007020274A2/en
Publication of WO2007020274A3 publication Critical patent/WO2007020274A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Abstract

A system and method for communicating instructions and data between a processor and external devices are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power 'stall' state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
PCT/EP2006/065372 2005-08-19 2006-08-16 System and method for communicating instructions and data between a processor and external devices WO2007020274A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP06792852A EP1917600A2 (en) 2005-08-19 2006-08-16 System and method for communicating instructions and data between a processor and external devices
CN200680030145XA CN101243421B (en) 2005-08-19 2006-08-16 System and method for communicating instructions and data between a processor and external devices
JP2008526500A JP5558713B2 (en) 2005-08-19 2006-08-16 Method for communicating instructions and data related to events in a processor within a data processing system

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/207,970 US7778271B2 (en) 2005-08-19 2005-08-19 Method for communicating instructions and data between a processor and external devices
US11/207,971 2005-08-19
US11/207,970 2005-08-19
US11/207,971 US7500039B2 (en) 2005-08-19 2005-08-19 Method for communicating with a processor event facility

Publications (2)

Publication Number Publication Date
WO2007020274A2 WO2007020274A2 (en) 2007-02-22
WO2007020274A3 true WO2007020274A3 (en) 2007-04-19

Family

ID=37308797

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2006/065372 WO2007020274A2 (en) 2005-08-19 2006-08-16 System and method for communicating instructions and data between a processor and external devices

Country Status (3)

Country Link
EP (1) EP1917600A2 (en)
JP (1) JP5558713B2 (en)
WO (1) WO2007020274A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101291348B (en) * 2008-06-12 2011-11-30 巴别塔（北京）科技有限公司 Prompt method for wireless channel awaking
JP5293165B2 (en) * 2008-12-25 2013-09-18 富士通セミコンダクター株式会社 Simulation support program, simulation apparatus, and simulation support method
CN105511320A (en) * 2015-12-11 2016-04-20 中国航空工业集团公司西安航空计算技术研究所 Method for realizing communication control inside FC recorder
CN114546905A (en) * 2022-01-20 2022-05-27 广州广电五舟科技股份有限公司 Channel synchronization control method and device for multi-channel CPU

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5870627A (en) * 1995-12-20 1999-02-09 Cirrus Logic, Inc. System for managing direct memory access transfer in a multi-channel system using circular descriptor queue, descriptor FIFO, and receive status queue
EP1026596A2 (en) * 1999-02-03 2000-08-09 Sun Microsystems, Inc. Direct memory access control
US6453365B1 (en) * 1998-02-11 2002-09-17 Globespanvirata, Inc. Direct memory access controller having decode circuit for compact instruction format
US20040193754A1 (en) * 2003-03-27 2004-09-30 International Business Machines Corporation DMA prefetch

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000003285A (en) * 1998-06-11 2000-01-07 Nec Saitama Ltd Method for processing interruption and circuit therefor
US7409483B2 (en) * 2003-12-19 2008-08-05 Intel Corporation Methods and apparatuses to provide message signaled interrupts to level-sensitive drivers

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5870627A (en) * 1995-12-20 1999-02-09 Cirrus Logic, Inc. System for managing direct memory access transfer in a multi-channel system using circular descriptor queue, descriptor FIFO, and receive status queue
US6453365B1 (en) * 1998-02-11 2002-09-17 Globespanvirata, Inc. Direct memory access controller having decode circuit for compact instruction format
EP1026596A2 (en) * 1999-02-03 2000-08-09 Sun Microsystems, Inc. Direct memory access control
US20040193754A1 (en) * 2003-03-27 2004-09-30 International Business Machines Corporation DMA prefetch

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1917600A2 *

Also Published As

Publication number Publication date
EP1917600A2 (en) 2008-05-07
JP2009505258A (en) 2009-02-05
JP5558713B2 (en) 2014-07-23
WO2007020274A2 (en) 2007-02-22

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