CN114546905A - Channel synchronization control method and device for multi-channel CPU - Google Patents
Channel synchronization control method and device for multi-channel CPU Download PDFInfo
- Publication number
- CN114546905A CN114546905A CN202210068178.4A CN202210068178A CN114546905A CN 114546905 A CN114546905 A CN 114546905A CN 202210068178 A CN202210068178 A CN 202210068178A CN 114546905 A CN114546905 A CN 114546905A
- Authority
- CN
- China
- Prior art keywords
- bit width
- synchronous
- training
- processor
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 52
- 238000012549 training Methods 0.000 claims abstract description 211
- 230000001360 synchronised effect Effects 0.000 claims abstract description 210
- 230000003247 decreasing effect Effects 0.000 claims abstract description 16
- 238000004891 communication Methods 0.000 claims abstract description 8
- 238000004364 calculation method Methods 0.000 claims description 4
- 238000004590 computer program Methods 0.000 claims description 2
- 230000001105 regulatory effect Effects 0.000 abstract 1
- 238000012545 processing Methods 0.000 description 16
- 230000000903 blocking effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 102100032489 Heat shock 70 kDa protein 13 Human genes 0.000 description 2
- 101001016638 Homo sapiens Heat shock 70 kDa protein 13 Proteins 0.000 description 2
- 101000720079 Stichodactyla helianthus DELTA-stichotoxin-She4a Proteins 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004883 computer application Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F18/00—Pattern recognition
- G06F18/20—Analysing
- G06F18/21—Design or setup of recognition systems or techniques; Extraction of features in feature space; Blind source separation
- G06F18/214—Generating training patterns; Bootstrap methods, e.g. bagging or boosting
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a channel synchronization control method and device of a multi-channel CPU, electronic equipment and a computer readable storage medium, wherein the method comprises the following steps: the synchronous training controller triggers the master processor and each slave processor to carry out synchronous training, and when the training of the master processor or any slave processor fails, the bit width of the training can be adjusted in a step-by-step decreasing mode, so that the master processor and each slave processor carry out synchronous training again until the training is successful or the bit width cannot be adjusted. The invention can limit the times of synchronous training in a limited way by regulating the bit width step by step, thereby avoiding the repeated uninterrupted full bit width synchronous training, effectively reducing the time consumption of training and improving the training efficiency; and the invention can avoid missing the successful result of the full bit width synchronization caused by random communication error code by adjusting the bit width to carry out the synchronization training again, thereby further improving the success rate of the training.
Description
Technical Field
The invention relates to the technical field of synchronous control of a CPU (central processing unit), in particular to a method and a device for synchronously controlling channels of a multi-channel CPU.
Background
With the continuous development of computer application technology, the computing power and processing speed of a single processor (CPU) are gradually hard to meet the increasing demands of high-density computing and mass data processing. In order to meet the processing requirements of mass data, the cluster application of multiple servers, multiple hosts and multiple multi-core CPUs is one of the important technologies. The computing capability of the computer can be improved by the mutual cooperative processing calculation, data access, control communication and other operations of the multi-path and multi-core CPUs.
Before the multi-path multi-core CPU works, a stable and reliable synchronization mechanism needs to be established for the multi-path multi-core CPU to realize efficient cooperation among subsystems in the architecture, and the synchronization mechanism needs to be established before the multi-path multi-core CPU is cooperatively interconnected. The synchronous control method of the multi-path and multi-core CPU commonly used at present is that based on a synchronous training control and interconnection channel, the multi-path and multi-core CPU participating in cooperative interconnection transmits interconnection instructions and data through a special interconnection data channel, before cooperative interconnection is established, a main CPU and each level of slave CPU respectively send asynchronous synchronous training pulse signals to a synchronous training controller, and the synchronous training controller is triggered to judge the logic relation of the asynchronous synchronous training pulse signals of the main CPU and each level of slave CPU. When the synchronous training pulses of the main CPU and the slave CPUs at all levels meet the preset logic operation result, the synchronous training controller simultaneously sends the starting signal of the synchronous counter to the receiving ends of the synchronous counters of the main CPU and the slave CPUs at all levels. If all the interconnection channels can be successfully trained, the main CPU or the slave CPU returns a successful synchronization result to the synchronous controller after receiving the initial signal of the synchronous counter, when all the cooperative synchronous CPUs return a successful synchronization signal, the synchronous controller judges that the synchronous establishment is completed, and the synchronized CPUs are communicated by using a special interconnection data channel. If the synchronous controller does not receive the result that all the CPUs return the successful synchronization, the synchronous controller waits for receiving the result that all the CPUs return the successful synchronization within the set overtime, and when the result that all the CPUs return the successful synchronization is not received after the set overtime, the synchronous controller informs the main CPU and the slave CPUs at all levels of the synchronous training process to restart.
However, the currently common synchronization control method has the following technical problems: once any one interconnection data channel has channel bit width blocking or high bit error rate, the sub-synchronous training is not successfully established, so that all interconnection channels need to be synchronized again, the processing time length is increased, and the processing efficiency is reduced; in the resumed synchronous training, when the number of the CPU systems that need to be cooperatively interconnected is large, the number of the interconnected data channels is also large, and the probability of channel bit width blocking or bit error rate is also high, thereby improving the probability of repeated training, further reducing the processing time, even under extreme conditions, the main CPU and each level of slave CPU are always in the process of repeated training, so that each CPU cannot complete synchronization of all the interconnected data channels.
Disclosure of Invention
The invention provides a method and a device for synchronously controlling channels of a multi-channel CPU, wherein the method can be used for controlling a main CPU and slave CPUs at all levels to carry out synchronous training when a synchronous controller controls the main CPU and the slave CPUs at all levels, and gradually reducing the bit width of an interconnection channel of the main CPU and controlling the main CPU and the slave CPUs at all levels to restart the synchronous training when any one CPU is not successfully trained, so that the problem of repeatedly executing the synchronous training due to the bit width blockage or high bit error rate of the interconnection channel can be avoided, the time consumed by the training can be reduced, and the processing efficiency of the training control can be improved.
A first aspect of an embodiment of the present invention provides a method for synchronously controlling channels of a multi-channel CPU, where the method involves a synchronous training controller, and a master processor and a plurality of slave processors that respectively communicate with the synchronous training controller, and the method includes:
respectively sending a first synchronization signal to the master processor and each slave processor through the synchronization training controller, enabling each slave processor to synchronously train the self interconnection channel by adopting the first synchronization signal, and enabling the master processor to synchronously train the self interconnection channel by adopting the first synchronization signal according to a first bit width, wherein the first bit width is the current bit width of the interconnection channel of the master processor;
if the synchronous training of the interconnection channel of the master processor is unsuccessful or the synchronous training of the interconnection channel of any slave processor is unsuccessful, gradually reducing the first bit width to a second bit width, and repeatedly executing control of the synchronous training controller to respectively send a second synchronous signal to the master processor and each slave processor so as to trigger the master processor to adopt the second synchronous signal, synchronously train the interconnection channel of the slave processor according to the second bit width, and trigger each slave processor to adopt the second synchronous signal to synchronously train the interconnection channel of the slave processor until the synchronous training of the interconnection channel of the master processor is successful and the synchronous training of the interconnection channel of each slave processor is successful.
In a possible implementation manner of the first aspect, before the step of gradually decreasing the first bit width to the second bit width, the method further includes:
triggering the primary processors to adopt the first synchronous signals, and performing synchronous training on the self interconnection channels according to the first bit width again, and triggering each secondary processor to adopt the first synchronous signals to perform synchronous training on the self interconnection channels.
In a possible implementation manner of the first aspect, before the step of sending, by the synchronization training controller, the first synchronization signal to the master processor and each slave processor respectively, the method further includes:
controlling the primary processor to send a synchronization trigger signal to the synchronization training controller;
triggering the synchronous training controller to perform logic operation by adopting the synchronous trigger signal;
and when the operation result of the logic operation is synchronous operation, generating a first synchronous signal.
In a possible implementation manner of the first aspect, the calculation manner of the logical operation is specifically:
respectively acquiring the logic value output by each slave stage processor;
if the logic values output by the secondary processors are the same, taking the logic values output by the secondary processors as secondary operation values, otherwise, acquiring historical logic values as secondary operation values, wherein the historical logic values are the same logic values output by each secondary processor at the previous time;
carrying out exclusive OR operation by adopting the slave operation numerical value and the synchronous trigger signal to obtain an operation numerical value;
when the operation value is the same as a preset value and the operation value is kept unchanged within a preset time, the operation result of the logic operation is synchronous operation;
otherwise, the operation result of the logic operation is asynchronous operation.
In a possible implementation manner of the first aspect, the preset duration specifically is: and the slave processor adopts the first synchronization signal to synchronously train the self interconnection channel, or the master processor adopts the first synchronization signal to synchronously train the self interconnection channel according to the second bit width.
In a possible implementation manner of the first aspect, the step-wise decreasing the first bit width to the second bit width includes:
judging whether the bit width value of the first bit width is an even number or not;
and if the bit width value of the first bit width is an even number, taking the bit width corresponding to half of the bit width value of the first bit width as a second bit width.
In a possible implementation manner of the first aspect, the method further includes:
and if the bit width value of the first bit width is not an even number, triggering the synchronous training controller to send an out-of-step alarm signal to the primary processor.
A second aspect of an embodiment of the present invention provides a channel synchronization control apparatus for a multi-channel CPU, where the apparatus relates to a synchronization training controller, and a master processor and a plurality of slave processors that communicate with the synchronization training controller, respectively, and the apparatus includes:
a sending module, configured to send a first synchronization signal to the master processor and each slave processor through the synchronization training controller, so that each slave processor performs synchronization training on its own interconnect channel by using the first synchronization signal, and the master processor performs synchronization training on its own interconnect channel by using the first synchronization signal according to a first bit width, where the first bit width is a current bit width of the interconnect channel of the master processor;
and the training module is used for gradually reducing the first bit width to a second bit width if the synchronous training of the interconnection channel of the master processor is unsuccessful or the synchronous training of the interconnection channel of any slave processor is unsuccessful, and repeatedly controlling the synchronous training controller to respectively send a second synchronous signal to the master processor and each slave processor so as to trigger the master processor to adopt the second synchronous signal, synchronously train the interconnection channel of the slave processor according to the second bit width, and trigger each slave processor to adopt the second synchronous signal to synchronously train the interconnection channel of the slave processor until the synchronous training of the interconnection channel of the master processor is successful and the synchronous training of the interconnection channel of each slave processor is successful.
Compared with the prior art, the method and the device for synchronously controlling the channels of the multi-channel CPU have the advantages that: according to the invention, after the synchronous training fails, the bit width of the training is adjusted in a step-by-step decreasing mode, so that the number of times of the synchronous training is limited to a limited extent, the full bit width synchronous training is prevented from being repeatedly and uninterruptedly carried out, the time consumption of the training is reduced, and the training efficiency is improved; and the bit width is adjusted to carry out synchronous training again, so that the condition that the successful synchronization result of the full bit width is missed due to random communication error codes can be avoided, and the success rate of training is further improved.
Drawings
Fig. 1 is a schematic connection diagram of components involved in a method for controlling channel synchronization of a multi-channel CPU according to an embodiment of the present invention;
fig. 2 is a schematic flowchart of a channel synchronization control method for a multi-channel CPU according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating an operation of a method for controlling channel synchronization of a multi-channel CPU according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a channel synchronization control apparatus for a multi-channel CPU according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The currently common synchronous control method has the following technical problems: once any one interconnection data channel has channel bit width blocking or high bit error rate, the sub-synchronous training is not successfully established, so that all interconnection channels need to be synchronized again, the processing time length is increased, and the processing efficiency is reduced; in the resumed synchronous training, when the number of the CPU systems that need to be cooperatively interconnected is large, the number of the interconnected data channels is also large, and the probability of channel bit width blocking or bit error rate is also high, thereby improving the probability of repeated training, further reducing the processing time, even under extreme conditions, the main CPU and each level of slave CPU are always in the process of repeated training, so that each CPU cannot complete synchronization of all the interconnected data channels.
In order to solve the above problem, the following detailed embodiments will describe and explain a channel synchronization control method of a multi-channel CPU provided in the embodiments of the present application.
Referring to fig. 1, a connection diagram of components involved in a method for controlling channel synchronization of a multi-channel CPU according to an embodiment of the present invention is shown.
In an embodiment, the method may involve a synchronous training controller, and a master processor and a number of slave processors in communication with the synchronous training controller, respectively.
Specifically, referring to fig. 1, the synchronous training controller may be coupled to the master processor via a synchronous training signal path STCH, and may also be communicatively coupled to each of the slave processors via a synchronous training signal path STCH, respectively. A master processor may also be connected to each slave processor.
In practice, the synchronous training controller may be used to control the master processor and the slave processor to perform a synchronous training operation to synchronize the master processor with several slave processors.
Referring to fig. 2, a flowchart of a channel synchronization control method for a multi-channel CPU according to an embodiment of the present invention is shown.
As an example, the method for controlling channel synchronization of a multi-channel CPU may include:
and S11, controlling the main-stage processor to send a synchronous trigger signal to the synchronous training controller.
In one embodiment, the synchronization trigger signal may be initiated directly by the master processor to inform the synchronization training controller to send the pulse signals required for training to the master and slave processors, respectively. Wherein the synchronization trigger signal may be a synchronization counter start signal.
The main processor triggers the synchronous training controller to execute subsequent judgment and training control operations, so that random interference data at the non-effective synchronous time can be effectively shielded.
And S12, triggering the synchronous training controller to perform logic operation by adopting the synchronous trigger signal.
In one embodiment, the synchronization training controller may perform a logic operation on the primary processor and the secondary processor using the synchronization trigger signal to determine whether the primary processor and the secondary processor meet the synchronization condition, so as to avoid wasting training time and training resources by performing synchronization training on the non-meeting primary processor and the non-meeting secondary processor.
To accurately determine whether both the master processor and the slave processor meet the synchronization condition, in an alternative embodiment, step S12 may include the following sub-steps:
and a substep S121 of obtaining the logic value output by each slave stage processor respectively.
And a substep S122, if the logic values output by each secondary processor are the same, taking the logic values output by the secondary processor as secondary operation values, otherwise, obtaining historical logic values as secondary operation values, wherein the historical logic values are the logic values of which the logic values output by each secondary processor are the same at the previous time.
And a substep S123 of performing an exclusive OR operation by using the slave operation value and the synchronous trigger signal to obtain an operation value.
And a substep S124, when the operand value is the same as a preset value and the operand value is kept unchanged within a preset time duration, performing synchronous operation on the operation result of the logical operation.
In an optional embodiment, the preset duration specifically includes: and the slave processor adopts the first synchronization signal to synchronously train the self interconnection channel, or the master processor adopts the first synchronization signal to synchronously train the self interconnection channel according to the second bit width.
And step S125, otherwise, the operation result of the logic operation is asynchronous operation.
For example, assuming that the synchronous outputs of the slave processors of each stage are the same logic number 1, the operation value of the slave stage is 1; assuming that the synchronous output of each stage of slave stage processor is the same as logic number 0, the operation value of the slave stage is 0; if at least one of the slave-stage operation values of each stage is different, the last logic output state is kept, namely the last slave-stage operation value is adopted.
And then, carrying out exclusive OR operation on the slave-level operation numerical value and the synchronous training pulse signal of the master-level processor, and when the operation result meets the condition that the logic number is kept to be 1 in a preset time period, determining that the operation result of the logic operation is synchronous operation, otherwise, determining that the operation result of the logic operation is asynchronous operation.
And S13, generating a first synchronous signal when the operation result of the logic operation is synchronous operation.
In one embodiment, when the operation result of the logical operation is determined to be a synchronous operation, the synchronous training controller may send a first synchronous signal to the primary processor, wherein the first synchronous signal may be a synchronous counter start signal TFS.
Specifically, the synchronous training controller may be composed of a synchronous signal logic operation unit STLU, a synchronous counter start signal processing unit SCSTU. The synchronization signal logic operation unit may be configured to receive a synchronization training pulse signal fed back from the master processor and each of the slave processors to determine whether the master processor and each of the slave processors are trained completely. The synchronous counter start signal processing unit may be configured to select a synchronous counter start signal TFS output from the main CPU according to a logic operation result of the synchronous signal logic operation unit.
S14, sending a first synchronization signal to each of the master processors and the slave processors through the synchronization training controller, so that each of the slave processors performs synchronization training on its own interconnect channel by using the first synchronization signal, and so that the master processor performs synchronization training on its own interconnect channel by using the first synchronization signal according to a first bit width, where the first bit width is a current bit width of the interconnect channel of the master processor.
In one embodiment, the synchronous training controller sends a first synchronous signal to the master processor and each slave processor, and each slave processor may start resetting its internal counter since receiving the synchronous counter start signal TFS to receive a clock signal from the same source and same phase as the master processor for performing the synchronous training. And the primary processor can also start to reset the counter inside the processor thereof after receiving the synchronous counter starting signal TFS, and automatically carry out synchronous training.
In training, in order to adapt the bit width of the master processor, the first synchronization signal may be transmitted to the master processor and the slave processor at corresponding frequencies based on the current bit width of the master processor.
After the training is completed, the training state or the training result can be sent to the synchronous training controller, so that the synchronous training controller can check the synchronous training result according to the result to determine whether the synchronous training of each processor is completed.
In training, the primary processor may train at its current bit width. For example, the current bit width is 64 bits, which may be denoted as FIT [63:0 ].
S15, if the synchronous training of the interconnect channel of the master processor is unsuccessful or the synchronous training of the interconnect channel of any one of the slave processors is unsuccessful, gradually decreasing the first bit width to a second bit width, and repeatedly controlling the synchronous training controller to send a second synchronous signal to the master processor and each of the slave processors, respectively, so as to trigger the master processor to adopt the second synchronous signal, perform synchronous training on its own interconnect channel according to the second bit width, and trigger each of the slave processors to adopt the second synchronous signal to perform synchronous training on its own interconnect channel until the synchronous training of the interconnect channel of the master processor is successful and the synchronous training of the interconnect channel of each of the slave processors is successful.
After receiving the training result, if it is determined that the training of the master processor is unsuccessful or that the training of any slave processor is unsuccessful, the synchronous training controller may determine that the current synchronous training fails and needs to adjust the current bit width of the master processor, and then perform a second training on the master processor and each slave processor to synchronize each processor. Specifically, after the bit width of the primary processor is adjusted, the step of training operation may be executed again, so that the synchronous training may be performed again.
The current bit width of the master processor is modified, so that the synchronous training controller can be triggered to send the second synchronous signal, the frequency for sending the second synchronous signal can be adjusted, and the second synchronous signal is respectively sent to the master processor and the slave processors through a new communication frequency, so that the master processor and each slave processor can perform synchronous training again.
By actively adjusting the bit width of the main processor, the problem that the same synchronous training is repeatedly executed due to the bit width blocking or high bit error rate of an interconnection channel can be avoided, and further the continuous and unproductive training can be avoided, so that the time consumption of the training can be reduced, and the processing efficiency of the training can be improved.
In order to improve the training efficiency, in an embodiment, the first bit width is gradually decreased to the second bit width by taking a half of the first bit width as the second bit width. For example, the first bit width is 64 bits, and the second bit width obtained by stepwise decreasing is 32 bits. And when the training is unsuccessful by adopting the second bit width, taking 32 bits as the first bit width, submitting step by step to obtain 16 bits as the second bit width, and performing the training again, and so on.
In the step-wise decreasing process, the first bit width may not be continuously decreased, and in order to jump out the operation flow of the repetitive training, in an alternative embodiment, the step S15 may include the following sub-steps:
and S151, judging whether the bit width value of the first bit width is an even number.
S152, if the bit width value of the first bit width is an even number, taking the bit width corresponding to one half of the bit width value of the first bit width as a second bit width.
And S153, if the bit width value of the first bit width is not an even number, triggering the synchronous training controller to send an out-of-step alarm signal to the master processor.
If the first bit width is an even number, the first bit width can be decreased step by step, and if the first bit width is an odd number, the first bit width cannot be decreased step by step.
Specifically, if the bit width value of the first bit width is 64 bits and the bit width value of the first bit width is an even number, the bit width 32 corresponding to one half of the bit width value of the first bit width is used as the second bit width, and then the master processor performs synchronous training with the bit width of 32 bits. If the bit width value of the first bit width is 1 bit and the bit width value of the first bit width is an odd number, the first bit width cannot be gradually decreased to the second bit width, the synchronous training operation needs to be skipped, and an out-of-step alarm signal can be sent to the primary processor to stop the synchronous training.
In order to avoid the above situation, in the process of performing the synchronization training, which may also be caused by various uncertainties that result in unsuccessful training of the master processor or any slave processor, in an embodiment, before the step of stepping down the first bit width to the second bit width, the method may further include:
and S16, triggering the master-level processors to adopt the first synchronization signals, and performing synchronous training on the self interconnection channels according to the first bit width again, and triggering each slave-level processor to adopt the first synchronization signals to perform synchronous training on the self interconnection channels.
Specifically, the synchronization training controller may re-determine whether the master processor and the slave processor satisfy the synchronization training condition, and when both the master processor and the slave processor satisfy the synchronization training condition, send the first synchronization signal to the master processor and the slave processor, so that the master processor uses the first synchronization signal, re-performs synchronization training on its own interconnection channel according to the first bit width, and each slave processor uses the first synchronization signal to perform synchronization training on its own interconnection channel.
By triggering the primary processor and the secondary processor to perform synchronous training again by using the first synchronous signal, the condition that the synchronous training of the primary processor and the secondary processor is unsuccessful due to other uncertain factors can be eliminated.
In an optional embodiment, the present invention may perform two times of synchronous training using the same bit width, and when the bit width decreases gradually, the bit width may be divided into a high bit width and a low bit width. E.g., 64 bits, may be 32 higher and 32 lower bits, respectively.
In order to further improve the success rate of training, the first synchronous training can be performed by first adopting the high bit width, and if the first synchronous training fails, the second synchronous training can be performed by adopting the low bit width, so that the situation that the full bit width training is repeated for many times in the prior art can be effectively avoided, and the successful synchronization efficiency of the cooperative interconnection channel can be improved. And synchronous training is carried out by gradually decreasing from the highest bit width, so that the bit width of the cooperative interconnection channel between the master processor and each slave processor can be kept symmetrical, and the lowest guaranteed bit width reaches a single special interconnection data channel.
Referring to fig. 3, an operation flowchart of a channel synchronization control method for a multi-channel CPU according to an embodiment of the present invention is shown.
Specifically, after the synchronous training is started, the master processor and the slave processor can perform the first synchronous training according to the current bit width, if any one of the master processor and the slave processor is unsuccessful, whether the current bit width is adopted for the first synchronous training is judged, if the current bit width is adopted for the first synchronous training, the current bit width is adopted again for the synchronous training of the master processor and the slave processor, if the current bit width is not adopted for the first synchronous training, the current bit width is adjusted, the adjusted bit width is adopted again for the first synchronous training of the master processor and the slave processor, if any one of the master processor and the slave processor is unsuccessful, whether the adjusted bit width is adopted for the first synchronous training is judged, and so on until the synchronous training of the master processor and the slave processor is successful, or stopping the processing until the current bit width can not be adjusted.
In this embodiment, an embodiment of the present invention provides a method for synchronously controlling channels of multiple CPUs, which has the following beneficial effects: according to the invention, after the synchronous training fails, the bit width of the training is adjusted in a step-by-step decreasing mode, so that the number of times of the synchronous training is limited to a limited extent, the full bit width synchronous training is prevented from being repeatedly and uninterruptedly carried out, the time consumption of the training is reduced, and the training efficiency is improved; and the bit width is adjusted to carry out synchronous training again, so that the condition that the successful synchronization result of the full bit width is missed due to random communication error codes can be avoided, and the success rate of training is further improved.
An embodiment of the present invention further provides a device for controlling channel synchronization of multiple CPUs, and referring to fig. 4, a schematic structural diagram of the device for controlling channel synchronization of multiple CPUs according to an embodiment of the present invention is shown.
The apparatus involves a synchronous training controller, and a master processor and a number of slave processors in communication with the synchronous training controller, respectively;
as an example, the channel synchronization control device of the multi-CPU may include:
a sending module 401, configured to send a first synchronization signal to the master processor and each slave processor through the synchronization training controller, so that each slave processor performs synchronization training on its own interconnect channel by using the first synchronization signal, and the master processor performs synchronization training on its own interconnect channel by using the first synchronization signal according to a first bit width, where the first bit width is a current bit width of the interconnect channel of the master processor;
a training module 402, configured to, if the synchronous training of the interconnect channel of the master processor is unsuccessful or the synchronous training of the interconnect channel of any one of the slave processors is unsuccessful, gradually decrease the first bit width to a second bit width, and repeatedly execute the control of the synchronous training controller to send a second synchronous signal to the master processor and each of the slave processors, respectively, so as to trigger the master processor to use the second synchronous signal, perform synchronous training on its own interconnect channel according to the second bit width, and trigger each of the slave processors to perform synchronous training on its own interconnect channel by using the second synchronous signal, until the synchronous training of the interconnect channel of the master processor is successful and the synchronous training of the interconnect channel of each of the slave processors is successful.
Optionally, the apparatus further comprises:
and the retraining module is used for triggering the master-level processors to adopt the first synchronous signals, retraining the synchronous training of the self interconnection channels according to the first bit width, and triggering each slave-level processor to adopt the first synchronous signals to carry out the synchronous training of the self interconnection channels.
Optionally, the apparatus further comprises:
the control module is used for controlling the main-stage processor to send a synchronous trigger signal to the synchronous training controller;
the operation module is used for triggering the synchronous training controller to perform logic operation by adopting the synchronous trigger signal;
and the generating module is used for generating a first synchronous signal when the operation result of the logic operation is synchronous operation.
Optionally, the calculation manner of the logical operation is specifically:
respectively acquiring the logic value output by each slave stage processor;
if the logic values output by the secondary processors are the same, taking the logic values output by the secondary processors as secondary operation values, otherwise, acquiring historical logic values as secondary operation values, wherein the historical logic values are the same logic values output by each secondary processor at the previous time;
carrying out exclusive OR operation by adopting the slave operation numerical value and the synchronous trigger signal to obtain an operation numerical value;
when the operation value is the same as a preset value and the operation value is kept unchanged within a preset time, the operation result of the logic operation is synchronous operation;
otherwise, the operation result of the logic operation is asynchronous operation.
Optionally, the preset duration specifically includes: and the slave processor adopts the first synchronization signal to synchronously train the self interconnection channel, or the master processor adopts the first synchronization signal to synchronously train the self interconnection channel according to the second bit width.
Optionally, the training module is further configured to:
judging whether the bit width value of the first bit width is an even number or not;
and if the bit width value of the first bit width is an even number, taking the bit width corresponding to half of the bit width value of the first bit width as a second bit width.
Optionally, the training module is further configured to:
and if the bit width value of the first bit width is not an even number, triggering the synchronous training controller to send an out-of-step alarm signal to the primary processor.
It can be clearly understood by those skilled in the art that, for convenience and brevity, the specific working process of the apparatus described above may refer to the corresponding process in the foregoing method embodiment, and is not described herein again.
Further, an embodiment of the present application further provides an electronic device, including: the system comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor executes the program to realize the channel synchronization control method of the multi-channel CPU according to the embodiment.
Further, an embodiment of the present application further provides a computer-readable storage medium, where computer-executable instructions are stored, and the computer-executable instructions are configured to enable a computer to execute the method for controlling channel synchronization of a multi-channel CPU according to the foregoing embodiment.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A method for channel synchronization control of a multi-CPU, the method involving a synchronization training controller, and a master processor and a plurality of slave processors in communication with the synchronization training controller, respectively, the method comprising:
respectively sending a first synchronization signal to the master processor and each slave processor through the synchronization training controller, enabling each slave processor to synchronously train the self interconnection channel by adopting the first synchronization signal, and enabling the master processor to synchronously train the self interconnection channel by adopting the first synchronization signal according to a first bit width, wherein the first bit width is the current bit width of the interconnection channel of the master processor;
if the synchronous training of the interconnection channel of the master processor is unsuccessful or the synchronous training of the interconnection channel of any slave processor is unsuccessful, gradually reducing the first bit width to a second bit width, and repeatedly executing control of the synchronous training controller to respectively send a second synchronous signal to the master processor and each slave processor so as to trigger the master processor to adopt the second synchronous signal, synchronously train the interconnection channel of the slave processor according to the second bit width, and trigger each slave processor to adopt the second synchronous signal to synchronously train the interconnection channel of the slave processor until the synchronous training of the interconnection channel of the master processor is successful and the synchronous training of the interconnection channel of each slave processor is successful.
2. The method according to claim 1, wherein before the step of gradually decreasing the first bit width to the second bit width, the method further comprises:
triggering the primary processors to adopt the first synchronous signals, and performing synchronous training on the self interconnection channels according to the first bit width again, and triggering each secondary processor to adopt the first synchronous signals to perform synchronous training on the self interconnection channels.
3. The channel synchronization control method of the multi-CPU as claimed in claim 1, wherein before the step of transmitting the first synchronization signal to the master processor and each of the slave processors through the synchronization training controller, respectively, the method further comprises:
controlling the primary processor to send a synchronization trigger signal to the synchronization training controller;
triggering the synchronous training controller to perform logic operation by adopting the synchronous trigger signal;
and when the operation result of the logic operation is synchronous operation, generating a first synchronous signal.
4. The method according to claim 3, wherein the calculation of the logical operation is specifically:
respectively acquiring the logic value output by each slave stage processor;
if the logic values output by the secondary processors are the same, taking the logic values output by the secondary processors as secondary operation values, otherwise, acquiring historical logic values as secondary operation values, wherein the historical logic values are the same logic values output by each secondary processor at the previous time;
carrying out exclusive OR operation by adopting the slave operation numerical value and the synchronous trigger signal to obtain an operation numerical value;
when the operation value is the same as a preset value and the operation value is kept unchanged within a preset time, the operation result of the logic operation is synchronous operation;
otherwise, the operation result of the logic operation is asynchronous operation.
5. The method according to claim 1, wherein the preset duration specifically is: and the slave processor adopts the first synchronization signal to synchronously train the interconnection channel of the slave processor, or the master processor adopts the first synchronization signal to synchronously train the interconnection channel of the master processor according to the second bit width.
6. The method as claimed in claim 1, wherein said step-wise decreasing the first bit width to a second bit width comprises:
judging whether the bit width value of the first bit width is an even number or not;
and if the bit width value of the first bit width is an even number, taking the bit width corresponding to half of the bit width value of the first bit width as a second bit width.
7. The channel synchronization control method of the multi-CPU as claimed in claim 6, wherein the method further comprises:
and if the bit width value of the first bit width is not an even number, triggering the synchronous training controller to send an out-of-step alarm signal to the primary processor.
8. An apparatus for controlling channel synchronization of a multi-CPU, the apparatus involving a synchronous training controller, and a master processor and a plurality of slave processors respectively communicating with the synchronous training controller, the apparatus comprising:
a sending module, configured to send a first synchronization signal to the master processor and each slave processor through the synchronization training controller, so that each slave processor performs synchronization training on its own interconnect channel by using the first synchronization signal, and the master processor performs synchronization training on its own interconnect channel by using the first synchronization signal according to a first bit width, where the first bit width is a current bit width of the interconnect channel of the master processor;
and the training module is used for gradually reducing the first bit width to a second bit width if the synchronous training of the interconnection channel of the master processor is unsuccessful or the synchronous training of the interconnection channel of any slave processor is unsuccessful, and repeatedly controlling the synchronous training controller to respectively send a second synchronous signal to the master processor and each slave processor so as to trigger the master processor to adopt the second synchronous signal, synchronously train the interconnection channel of the slave processor according to the second bit width, and trigger each slave processor to adopt the second synchronous signal to synchronously train the interconnection channel of the slave processor until the synchronous training of the interconnection channel of the master processor is successful and the synchronous training of the interconnection channel of each slave processor is successful.
9. An electronic device, comprising: memory, processor and computer program stored on the memory and executable on the processor, characterized in that the processor implements the method of channel synchronization control of a multi-CPU according to any one of claims 1 to 7 when executing the program.
10. A computer-readable storage medium storing computer-executable instructions for causing a computer to perform the method for channel synchronization control of a multi-CPU according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210068178.4A CN114546905A (en) | 2022-01-20 | 2022-01-20 | Channel synchronization control method and device for multi-channel CPU |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210068178.4A CN114546905A (en) | 2022-01-20 | 2022-01-20 | Channel synchronization control method and device for multi-channel CPU |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114546905A true CN114546905A (en) | 2022-05-27 |
Family
ID=81671104
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210068178.4A Pending CN114546905A (en) | 2022-01-20 | 2022-01-20 | Channel synchronization control method and device for multi-channel CPU |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114546905A (en) |
Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ATE152532T1 (en) * | 1989-04-07 | 1997-05-15 | Digital Equipment Corp | TWO-WAY COMPUTER CONNECTION SYSTEM CONTROLLING A PACKET MEMORY WITH FOUR CONNECTION POINTS |
| WO2007020274A2 (en) * | 2005-08-19 | 2007-02-22 | International Business Machines Corporation | System and method for communicating instructions and data between a processor and external devices |
| WO2010138006A1 (en) * | 2009-05-29 | 2010-12-02 | Motorola, Inc | Method and system for training sequence synchronization in a digital communication network |
| US20130061005A1 (en) * | 2011-09-02 | 2013-03-07 | Mark A. Overby | Method for power optimized multi-processor synchronization |
| WO2015035877A1 (en) * | 2013-09-16 | 2015-03-19 | 杨惠芳 | Method for optimizing collaboration between multiple controllers |
| CN104462006A (en) * | 2015-01-05 | 2015-03-25 | 华为技术有限公司 | Method and device for synchronizing configuration between multiple processor cores in system-level chip |
| US20150339256A1 (en) * | 2014-05-21 | 2015-11-26 | Kalray | Inter-processor synchronization system |
| CN106464482A (en) * | 2014-03-31 | 2017-02-22 | 三星电子株式会社 | Method and apparatus to enable low power synchronization for large bandwidth wireless LAN systems |
| CN110134636A (en) * | 2018-02-09 | 2019-08-16 | 中兴通讯股份有限公司 | Model training method, server and computer readable storage medium |
| CN110321316A (en) * | 2019-06-19 | 2019-10-11 | 西安思丹德信息技术有限公司 | A kind of multi-channel synchronous data acquisition adaptive training control device and method |
| CN111198714A (en) * | 2018-11-16 | 2020-05-26 | 上海寒武纪信息科技有限公司 | Retraining method and related product |
| CN111241204A (en) * | 2020-02-14 | 2020-06-05 | 苏州浪潮智能科技有限公司 | Gradient data synchronization method, device, equipment and storage medium |
| CN111510411A (en) * | 2019-11-25 | 2020-08-07 | 南京中科晶上通信技术有限公司 | Carrier phase synchronization processing method, device, terminal and storage medium |
| CN112434317A (en) * | 2020-11-24 | 2021-03-02 | 深圳前海微众银行股份有限公司 | Data processing method, device, equipment and storage medium |
| CN112543349A (en) * | 2020-11-27 | 2021-03-23 | 西安空间无线电技术研究所 | Multi-port high-speed data synchronous transmission method |
| CN113821469A (en) * | 2021-09-23 | 2021-12-21 | 深圳市元征科技股份有限公司 | Multiprocessor synchronization method, device, terminal equipment and storage medium |
-
2022
- 2022-01-20 CN CN202210068178.4A patent/CN114546905A/en active Pending
Patent Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ATE152532T1 (en) * | 1989-04-07 | 1997-05-15 | Digital Equipment Corp | TWO-WAY COMPUTER CONNECTION SYSTEM CONTROLLING A PACKET MEMORY WITH FOUR CONNECTION POINTS |
| WO2007020274A2 (en) * | 2005-08-19 | 2007-02-22 | International Business Machines Corporation | System and method for communicating instructions and data between a processor and external devices |
| WO2010138006A1 (en) * | 2009-05-29 | 2010-12-02 | Motorola, Inc | Method and system for training sequence synchronization in a digital communication network |
| US20130061005A1 (en) * | 2011-09-02 | 2013-03-07 | Mark A. Overby | Method for power optimized multi-processor synchronization |
| WO2015035877A1 (en) * | 2013-09-16 | 2015-03-19 | 杨惠芳 | Method for optimizing collaboration between multiple controllers |
| CN106464482A (en) * | 2014-03-31 | 2017-02-22 | 三星电子株式会社 | Method and apparatus to enable low power synchronization for large bandwidth wireless LAN systems |
| US20150339256A1 (en) * | 2014-05-21 | 2015-11-26 | Kalray | Inter-processor synchronization system |
| CN104462006A (en) * | 2015-01-05 | 2015-03-25 | 华为技术有限公司 | Method and device for synchronizing configuration between multiple processor cores in system-level chip |
| CN110134636A (en) * | 2018-02-09 | 2019-08-16 | 中兴通讯股份有限公司 | Model training method, server and computer readable storage medium |
| CN111198714A (en) * | 2018-11-16 | 2020-05-26 | 上海寒武纪信息科技有限公司 | Retraining method and related product |
| CN110321316A (en) * | 2019-06-19 | 2019-10-11 | 西安思丹德信息技术有限公司 | A kind of multi-channel synchronous data acquisition adaptive training control device and method |
| CN111510411A (en) * | 2019-11-25 | 2020-08-07 | 南京中科晶上通信技术有限公司 | Carrier phase synchronization processing method, device, terminal and storage medium |
| CN111241204A (en) * | 2020-02-14 | 2020-06-05 | 苏州浪潮智能科技有限公司 | Gradient data synchronization method, device, equipment and storage medium |
| CN112434317A (en) * | 2020-11-24 | 2021-03-02 | 深圳前海微众银行股份有限公司 | Data processing method, device, equipment and storage medium |
| CN112543349A (en) * | 2020-11-27 | 2021-03-23 | 西安空间无线电技术研究所 | Multi-port high-speed data synchronous transmission method |
| CN113821469A (en) * | 2021-09-23 | 2021-12-21 | 深圳市元征科技股份有限公司 | Multiprocessor synchronization method, device, terminal equipment and storage medium |
Non-Patent Citations (2)
| Title |
|---|
| 李伟;李洋;陈帆;: "基于共享存储器的密码多核处理器核间通信机制研究与设计", 微电子学与计算机, no. 01 * |
| 李伟;李洋;陈帆;: "基于共享存储器的密码多核处理器核间通信机制研究与设计", 微电子学与计算机, no. 01, 5 January 2016 (2016-01-05) * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5371746A (en) | Program debugging system for a distributed data processing system | |
| US8949497B2 (en) | Method and apparatus for interleaving bursts of high-speed serial interconnect link training with bus data transactions | |
| US9043804B2 (en) | Parallel computer system and program | |
| KR20180121531A (en) | Adaptive Peripheral Component Interconnects for Optimal Performance and Power Savings | |
| KR20020018309A (en) | Cpu scheduling method | |
| CN111625267B (en) | Program online upgrading system and method based on UWB communication | |
| JP2008065640A (en) | Simulation apparatus and method for controlling its simulation | |
| US20210223816A1 (en) | Clock skew correction method, device and system | |
| US20120203943A1 (en) | Radio communication device and method for controlling rf-bb state in the same | |
| CN102637139A (en) | Method, device and single panel for feeding watchdog by embedded system | |
| CN112698978A (en) | Fault tolerance method and device based on distributed graph processing network | |
| TW201020711A (en) | Voltage stabilization for clock signal frequency locking | |
| CN114546905A (en) | Channel synchronization control method and device for multi-channel CPU | |
| CN106625674B (en) | A kind of command processing method and robot for robot | |
| CN110032532B (en) | Master-slave serial port communication method based on timing interrupt triggering | |
| CN116886247B (en) | Baud rate self-adaption method and device based on UART communication, UART system and medium | |
| CN116743317B (en) | Data transmission method based on universal chip interconnection standard | |
| US8732262B2 (en) | Rate adaptive auto-negotiation | |
| CN108897248A (en) | A kind of self―tuning control and mobile robot | |
| CN105406984B (en) | A kind of system and method for realizing masterslave switchover backboard clock | |
| CN111736508B (en) | Acquisition control method and device for state management of inter-hole acoustic wave acquisition device | |
| WO2022178731A1 (en) | Operating method and apparatus for accelerator | |
| CN115981860A (en) | Task submitting and inspecting method, device, medium and program product | |
| CN113472841B (en) | Implementation method and device for terminating remote procedure call request | |
| CN114327631B (en) | Data sampling and storage method in encoder, single chip microcomputer and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |