WO2006127813A2

WO2006127813A2 - Methods for signal to noise improvement in bulk mems accelerometer chips and other mems devices

Info

Publication number: WO2006127813A2
Application number: PCT/US2006/020083
Authority: WO
Inventors: Henry C. Abbink; Gabriel M. Kuhn; Howard Ge; Daryl Sakaida
Original assignee: Northrop Grumman Corporation
Priority date: 2005-05-25
Filing date: 2006-05-24
Publication date: 2006-11-30
Also published as: WO2006127813A3

Abstract

A fabrication method for reducing parasitic capacitance in a semiconductor device, the semiconductor device having a guard layer (120, 125) separated from a proof mass layer (130) by a bond line (305) , and an electrode (210) separated by a signal gap (320) from a proof mass paddle 205) , by applying a nitride layer (507) on a wafer area for the electrode/proof (210) mass paddle (205) , oxidizing a wafer area for the guard/proof mass layer to form an oxide layer (509) on the surface; and etching the nitride layer (507) on the wafer area of the electrode/proof (210) mass paddle (205) .

Description

METHODS FOR SIGNAL TO NOISE IMPROVEMENT IN BULK MEMS ACCELEROMETER CHIPS AND OTHER MEMS DEVICES

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of Provisional Application No. 60/684,282, filed May 25, 2005, herein incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention.

[0002] The invention relates generally to Micro-Electro-Mechanical Systems

(MEMS). More particularly, the invention relates to a method for parasitic capacitance reduction in bulk MEMS accelerometers and other MEMS devices.

2. Description of Related Art.

[0003] Micro-Electro-Mechanical Systems (MEMS) is the integration of mechanical elements, sensors, actuators, and electronics on a common silicon substrate through microfabrication technology. The electronics in a MEMS device are fabricated using Integrated Circuit (IC) technology (CMOS, Bipolar, or BICMOS processes), while the micromechanical components are fabricated using "micromachining" techniques that selectively etch away or add new layers to the silicon wafer to form mechanical and electromechanical devices.

[0004] MEMS devices are widely used in automotives, navigation systems, chemical and biological sensors, microoptics, accelerometers, pressure sensors and other devices. A common approach to fabrication of MEMS devices is the so-called bulk MEMS process. This process consists of processing two or three silicon wafers with patterns machined by Deep Reactive Ion Etching (DRIE) to form the structure used in each layer, and then bonding these layers together by a process called direct bonding to form a hermetic cavity.

[0005] An example of a MEMS structure is the Silicon Accelerometer (SiAC™)

Sensor 100, shown in Figure 1. The sensor 100 has a first outside layer 110, a second outside layer 115, a first guard layer 120, a second guard layer 125, and a proof mass layer 130. The proof mass layer 130 is sandwiched between the first and second guard layers 120 and 125, which are sandwiched between the first and second outside layers 110 and 115. The sensor 100 also has a via 135 in each of layers 110 and 115 to facilitate a path or opening for circuit connection. The sensor 100 is fabricated from two silicon-on-insulator (SOI) wafers and one prime silicon wafer. A first SOI wafer contains the first outside layer 110 and the first guard layer 120, while a second SOI wafer contains the second outside layer 115 and a second guard layer 125. The prime silicon wafer provides the proof mass layer 130.

[0006] On the surface of each wafer layer 110-130 is a layer of oxide, typically

1 micron thick. When the guard layers 120 and 125 are bonded to the proof mass layer, a 2 micron layer of oxide is formed between the guard layers 120 and 125 and the proof mass layer 130. A 2 micron layer of oxide exists between the guard layers 120 and 125 and the outside layers 110 and 115, respectively in the SOI layers.

[0007] One technique to bond the SOI wafers to the proof mass layer 130 is by a process called direct bonding. The first SOI wafer containing the first outside layer 110 and the first guard layer 120 is bonded to one side of the proof mass layer 130 and a second SOI wafer containing the second outside layer 115 and the first guard layer 125 is bonded to the other side of the proof mass layer 130. Before bonding, the SOI wafers and the proof mass layer 130 are preferably cleaned and activated. Activation is done by either chemical or plasma surface activation. The SOI wafers and the proof mass layer 130 are properly aligned and then each SOI wafer is coupled to one side of the proof mass layer 130. Van Der Waals forces will cause the SOI wafers and the proof mass layer 130 to bond to each other. Since the Van Der Waals forces are relatively weak, the SOI wafers and the proof mass layer 130 may be annealed at an elevated temperature. This temperature depends on the activation process. Older processes used temperatures in excess of 1000°C. With newer plasma processes, 400-700°C may suffice. It can be envisioned that other methods or techniques can be used to bond the layers 110-130 together and achieve the same objective of the present invention. Figure 2 is an exploded view of the silicon accelerometer sensor 100 of

Figure 1. The exploded drawing shows the internal components of sensor 100. Contained within the proof mass layer 130 is a proof mass paddle 205 that is coupled to the proof mass layer 130 by silicon hinges. On opposite sides of the paddle 205 are electrodes. Figures 2 and 3 show electrodes 210 contained within the guard layers 120 and 125 and parallel to one another. This configuration forms a capacitor between each electrode 210 and the paddle 205. In operation, the capacitance is used to determine the gap between the paddle 205 and each electrode 210. An electronic circuit supplies the proper voltage pulses to force the paddle to null, defined as the paddle position where both capacitances are equal. [0009] Figure 3 is a side view of a silicon accelerometer sensor 100. The sensor 100 has an internal cavity 315 enclosed by layers 110-130. The internal cavity 315 houses the paddle 205 and electrodes 210, leaving a signal gap 320 between them. The sensor 100 also has an oxide PM-G bond line 305 formed between the proof mass layer 130 and first and second guard layers 120 and 125. Similarly, the sensor 100 has a G-E bond line 310 formed between the guard layers 120 and 125 and the outside wafer layers 110 and 115, respectively.

[0010] Figures 4-11 are graphic illustrations of prior art guard wafer area fabrication steps and Figures 12-19 are graphic illustrations of prior art electrode wafer area fabrication steps.

[0011] In Figure 4, a substrate wafer area 403 for the guard 120 or 125 is covered with a photoresist layer 405. Similarly, in Figure 12, a substrate wafer area 453 for the electrode 210 is covered with a photoresist layer 405. Substrate wafer areas 403 and 453 have a thickness h. The thickness of the photoresist layers 405 is preferably 5 microns. Referring to Figures 5 and 13, the wafer areas 453 and 403 are exposed to a photomask. After the photoresist 405 is developed, the openings 463 are formed. The openings 463 are preferably 5-10 microns in diameter.

[0012] Next, silicon nitride (SiN) 407 is deposited on the photoresist layers 405 as shown in Figures 6 and 14. Preferably, the thickness of the nitride layer 407 is about 1000 A. In Figure 14, the nitride 407 is also deposited in the openings 463.

[0013] Then, the wafer areas 403 and 453 are placed in photoresist solvent. The photoresist 405 dissolves and the nitride 407 deposited on the photoresist 405 breaks up and washes away. This process is well known as "lift off." As shown in Figures 7 and 15, only nitride 407 deposited in the openings 463 remains. This nitride 407 is used to form standoffs 465 between the electrode 210 and the paddle 205. The standoffs 465 are used to partially center the paddle 205 between the electrodes 210 so that there is a gap 320 between them even if the silicon accelerometer sensor 100 is turned off.

[0014] The wafer areas 403 and 453 are then oxidized to grow approximately

1 micron of silicon dioxide (SiO₂) layer 409 as shown in Figures 8 and 16. The region underneath the nitride deposits do not oxidize. Only the exposed surfaces of the wafer areas 403 and 453 oxidize. The growth of Silicon Dioxide layer 409 by oxidation, consumes the silicon wafer areas 403 and 453. The amount of wafer areas 403 and 453 consumed is directly proportional to the thickness of the oxide grown. For example, 1 micron of oxide grown consumes 0.45 microns of the Silicon wafer area 403 and 453; hence, the thickness of the wafer area 403 and 453 decreases by 0.45 microns except the wafer areas where silicon nitride 407 is deposited. Since Silicon Dioxide does not form above the nitride deposits 407, the result is the formation of standoffs 465 in the oxide layer 409.

[0015] Referring to Figures 9 and 17, photoresist layers 411 is deposited on top of oxide layers 409, and in the case of the electrode 210, the photoresist layer 411 is also deposited on the standoffs 465. In Figures 10 and 18, the photoresist 411 is patterned, using photolithography, to protect the oxide layer 409 that will form the direct wafer bonds, and exposes the oxide layer 409 in the wafer area 453 that will form the electrodes 210. [0016] The oxide layer 409 is etched in Figure 19, using an oxide etch solution, to remove the oxide layer 409. As shown in Figure 11 the oxide in the wafer area 403 that will form the guard bond area 305 remains intact.

[0017] It is understood by a person skilled in the art that yet another layer of photoresist can be placed on guard layers 120 or 125 and the electrode areas 210, and patterned by photolithography to open regions that form a cavity 315 by DRIE.

[0018] There are a number of disadvantages with this prior art fabrication technique.

First, the nitride 407 has been used in semiconductor memory devices because it traps charge. However, this feature is undesirable for silicon accelerometer sensors 100 because the proof mass layer 130 is preferably kept at virtual ground. Second, the nitride 407 is thin and brittle. It can break off and cause internal leakage paths or interference with the motion of the paddle 205.

[0019] Third, less than optimum signal capacitance is obtained from the resulting prior art sensor design 100. Since the growth of each micron of oxide 409 consumes about 0.45 microns of the silicon wafer area 403 or 453, and the design oxide thickness for the outside layers 110 and 115, proof mass layer 130, the guard 120 or 125 and the electrode 210 is about 1 micron each, then the signal gap 320 is approximately 2 microns and the paddle travel gap is 1.45 microns. However, if 1.45 microns is all the travel that is needed, then the signal capacitance of prior art sensor 100 can be increased if the signal gap 320 was reduced to 1.45μ or even less..

[0020] In the current electronic scheme, the electrodes 210 are driven by op amps, therefore, the capacitance between the electrodes 210 and the outside layers 110 or 115 is not an issue. However, the proof mass layer 130 is at virtual ground. The capacitance between the proof mass layer 130 and the guard layers 120 and 125 becomes a parasitic capacitance to the signal capacitance. T he ratio of signal capacitance to parasitic capacitance is a factor in determining the signal to noise ratio of the accelerometer. It is preferable if the paddle-to-electrode capacitance (P- E) is increased, while the proof mass-to-guard (PM-G) capacitance is decreased.

[0021] To decrease the PM-G capacitance, the width of the bond line 305 between the proof mass 130 and guard 120 or 125 might be decreased. Typically, the prior art width used for bond line 305 is 400 microns. However, as the width of the bond line 305 is decreased, the bond strength is decreased, and the ruggedness and reliability of the chip may become compromised. Therefore, there is a limit to the reduction of bond line width.

[0022] With an increasing demand for improved MEMS devices, there remains a continuing need in the art for a method that reduces parasitic PM-G capacitance in bulk MEMS accelerometers and other MEMS devices without compromising their reliability.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The exact nature of this invention, as well as the objects and advantages thereof, will become readily apparent from consideration of the following specification in conjunction with the accompanying drawings in which like reference numerals designate like parts throughout the figures thereof and wherein:

[0024] Figure 1 is a perspective view of a prior art silicon accelerometer sensor.

[0025] Figure 2 is an exploded view of the silicon accelerometer sensor of Figure 1.

[0026] Figure 3 is a side view of the silicon accelerometer sensor of Figure 1. [0027] Figures 4-11 are graphic illustrations of prior art guard wafer area fabrication steps. [0028] Figures 12-19 are graphic illustrations of prior art electrode wafer area fabrication steps. [0029] Figures 20-27 are graphic illustrations of guard wafer area fabrication steps, according to one embodiment of the present invention. [0030] Figures 28-35 are graphic illustrations of electrode wafer area fabrication steps, according to one embodiment of the present invention. [0031] Figure 36 is an exemplary flow chart depicting a method for reducing parasitic capacitance, according to one embodiment of the present invention. [0032] Figures 37-46 are graphic illustrations of guard wafer area fabrication steps, according to one embodiment of the present invention. [0033] Figures 47-56 are graphic illustrations of electrode wafer area fabrication steps, according to one embodiment of the present invention. [0034] Figure 57 is a flow chart depicting a method for reducing parasitic capacitance, according to one embodiment of the present invention.

SUMMARY OF THE INVENTION

[0035] A method for fabricating a MEMS cell with reduced parasitic capacitance.

The MEMS cell has a guard layer separated from a proof mass layer by a bond line, and an electrode separated by a signal gap from a proof mass paddle. The method includes applying a first photoresist layer on the wafer area for the electrode and the wafer area for the guard, exposing the first photoresist layer on the wafer area for the electrode and the wafer area for the guard with a photomask to remove the first photoresist layer from the wafer area for the electrode, applying a first nitride layer on a wafer area for the electrode and on the first photoresist layer applied to the surface of the wafer area for the guard, removing the first photoresist layer from the wafer area for the guard, oxidizing a wafer area for the guard to form a first oxide layer on the surface, and etching the first nitride layer on the wafer area of the electrode. The first nitride layer shields the wafer area for the electrode from oxidation to prevent a decrease in the signal gap during assembly, while the first oxide layer increases the bond line thickness between the guard layer and the proof mass layer to reduce parasitic capacitance during assembly.

[0036] In one embodiment, the method includes etching the first oxide layer on the wafer area for the guard before the step of etching the first nitride layer, and oxidizing the wafer area for the guard to form a second oxide layer on the surface. The second oxide layer increases the bond line thickness between the guard layer and the proof mass layer and decreases the thickness of the wafer area for the guard.

[0037] In another embodiment, the method for reducing parasitic capacitance can also be used to fabricate the proof mass paddle and the proof mass layer in the same manner as the electrode and guard, respectively.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] Figures 20-27 are graphic illustrations of guard wafer area fabrication steps, and Figures 28-35 are graphic illustrations of electrode wafer area fabrication steps, according to one embodiment of the present invention. Since process steps for the top and bottom SOI wafers are identical, the process is described only for the top wafer. Figure 36 is an exemplary flow chart depicting a method for reducing parasitic capacitance, according to one embodiment of the present invention.

[0039] In Figure 20, a substrate wafer area 503 for the guard 120 or 125 is covered with a photoresist layer 505. While in Figure 28, the substrate wafer area 553 for the electrode 210 is also covered with the photoresist layer 505 (605). Substrate wafer areas 503 and 553 have a thickness h. The thickness of the photoresist layer 505 is preferably 5 microns. Referring to Figures 21 and 29, the photoresist layer 505 is exposed to a photomask, and the photoresist layer 505 developed such that the photoresist 505 is removed from the wafer area for the electrode 553 (610). While the photoresist layer 505 of the electrode 210 is removed, the photoresist 505 on the guard area 503 remains, as shown in Figure 21.

[0040] Next, a layer of silicon nitride (SiN) 507 is deposited on the photoresist layer

505 of the guard 120 or 125, as shown in Figure 22. Since the photoresist layer of the electrode 210 is removed, the nitride layer 507 deposits on the wafer 553 of the electrode 210, as shown in Figure 30. Preferably, the thickness of the nitride layer 507 is about IOOOA (615).

[0041] Then, the wafer areas 503 and 553 are placed in photoresist solvent. For the guard area 503, the photoresist 505 dissolves and the nitride 507 deposited on the photoresist 505 breaks up and washes away by a process known to a person skilled in the art as "lift off. As shown in Figures 23 and 31, only nitride 507 deposited in the wafer area 553 of the electrode 210 remains (620).

[0042] The wafer areas 503 and 553 are then oxidized to grow approximately

1 micron of silicon dioxide (SiO₂) layer 509, as shown in Figures 24 and 32. The region underneath the nitride deposit 507 does not oxidize. Only the exposed surfaces of the wafer area 503 oxidize. Therefore, no oxide 509 grows on the wafer area 553 of the electrode 210. The growth of the silicon dioxide layer 509 by oxidation, consumes the silicon wafer area 503 of the guard 120 or 125. The amount of Silicon wafer area 503 consumed is directly proportional to the thickness of the oxide grown. For example, 1 micron of oxide grown consumes 0.45 microns of the Silicon wafer area 503; hence, the thickness of the wafer decreases by 0.45 microns (625).

[0043] Referring to Figures 25 and 33, a photoresist layer 511 is deposited on top of the oxide layer 509 for the guard 120 or 125, and on top of the nitride layer 507 for wafer area 553 the electrode 210, respectively (630). The wafer is patterned, using a photomask. As shown in Fig. 26, the photoresist protects the oxide layer 509 that will form the direct wafer bonds in wafer area 503, and exposes the silicon nitride layer 507 in the wafer area 553 that will form the electrodes 210 (635), as shown in Fig. 34.

[0044] The nitride layer 507 is etched from the electrode area 553 in Figure 35, using selective etching, such as wet or plasma techniques, to remove the nitride layer 507 (640). There would be no standoff formed; however, if standoffs are desired for preventing atomic bonding, then tiny dots of a dissimilar refractory metal, like Tungsten (W), with a 0.05 to 0.1 micron thickness would suffice. As shown in Figure 27, the oxide in the region 503 that will form the guard bond area 305 remains intact. It is understood by a person skilled in the art that yet another layer of photoresist can be placed on guard areas 503 and electrode areas 553, and patterned by photolithography to open regions that form a cavity 315 by DRIE (645). [0045] In one embodiment of this invention, if the SOI wafers are processed as above and no change is made to the proof mass process (i.e. processed per prior art), and if the design oxide thickness for the guard layers 120 and 125 and proof mass layer 130 is about 1 micron each, then the signal gap 320 would be approximately 1.55 microns (0.55 micron from the electrode 210 and 1 micron from proof mass paddle 205). The gap 320 from the electrode 210 is the difference in thickness between the guard 120 or 125 and the electrode 210. The result is a 29% improvement in the ratio of signal to parasitic capacitance ratio over the prior art design.

[0046] In the embodiment above, the signal capacitance can be increased by increasing the oxide thickness for the guard 120 or 125 and applying minimum oxidation of the proof mass layer 130, just sufficient to support direct bonding of the wafers, less than 500 A. If about 2 microns of oxide is grown on the guard layer then about 0.9 microns of the guard silicon wafer area 503 will be consumed. Hence, the bond line thickness 305 would remain at about 2 microns, while the signal gap 320 would be about 1.1 microns (1.1 microns from the electrode and 0 microns from the proof mass paddle 205). Accordingly, by using this method embodying the present invention, an 82% increase in signal capacitance over the prior art design would result.

[0047] In another embodiment of this invention, the process illustrated in Figure 36 is applied to both sides of the proof mass layer 130 in addition to the application to the guard layers 120 and 125. In this case, the outer bond area of the proof mass layer 130 is treated as the guard 120 and 125 while the paddle 205 is treated as the electrode 210. This embodiment enables signal capacitance to be increased without decreasing parasitic capacitance. Thus, if the design oxide thickness for guard layers 120 and 125 and for both sides of proof mass layer 130 is 1 micron, the signal gap would be 1.1 microns. The result is an 82% improvement in the ratio of signal parasitic capacitance over the prior art design.

[0048] The signal capacitance can be increased by increasing the oxide thickness for the guard 120 or 125 and the proof mass layer 130 to about 2 microns each. Hence, the bond line thickness 305 would increase to about 4 microns, while the signal gap 320 would be about 2.2 microns (1.1 microns from the electrode and 1.1 microns from the proof mass paddle 205). To keep the signal gap 320 at about 2 microns, the guard layers 120 or 125 and the proof mass layer 130 can be oxidized to have about 1.8 microns of oxide layer 509. As a result, a 44% reduction in parasitic capacitance would occur.

[0049] In order to further increase the oxide thickness for the guard 120 or 125, while keeping the signal gap 320 small, it is preferable to remove silicon from the bond area before bond oxide is grown. The silicon etching process has to be done without destroying the planarity and atomically roughening the surface where silicon is removed. One approach is to using wet etching or reactive ion etching without affecting the direct wafer bondability. Another approach is to oxidize the Silicon wafer area 703 with the nitride layer 707 in place, and then etch the oxide off. This is explained further in the following steps. Figures 37-46 are graphic illustrations of guard wafer area fabrication steps, and Figures 47-56 are graphic illustrations of electrode wafer area fabrication steps, according to another embodiment of the present invention. Figure 57 is a flow chart depicting a method for reducing parasitic capacitance, according to another embodiment of the present invention.

[0050] In Figure 37 and 47 show a substrate wafer area 703 for the guard 120 or 125 and substrate wafer area 753 for the electrode 210 covered with a photoresist layer 705. Substrate wafer areas 703 and 753 have a thickness h. The thickness of the photoresist layer 705 is preferably 5 microns. Referring to Figures 38 and 48, the wafer areas 703 and 753 are exposed to a photomask, and the photoresist layer 705 is developed such that the photoresist 705 is removed in wafer area 753 for electrode 210 (810). The photoresist 705 of wafer area 705 for the guard 120 or 125 remains, as shown in Figure 38.

[0051] Next, a layer of silicon nitride (SiN) 707 is deposited on the photoresist layer

705 of the guard area 120 or 125, as shown in Figure 39. Since the photoresist layer 705 of the electrode 210 is removed, the nitride 757 deposits on the wafer area 753 of the electrode 210, as shown in Figure 49. Preferably, the thickness of the nitride layer 707 is about IOOOA (815).

[0052] Then, the wafer curtaining areas 703 and 753 is placed in photoresist solvent.

For the guard areas 120 or 125, the photoresist 705 dissolves and the nitride 707 deposited on the photoresist 705 breaks up and washes away (820). As shown in Figures 40 and 50, only nitride 707 deposited in the wafer area 753 of the electrode 210 remains.

[0053] The wafer curtaining area 703 and 753 is placed in an oxidation furnace to reduce the thickness of the wafer area 703 by growing, for example, about 1 micron of silicon dioxide (SiO₂) layer 709, as shown in Figures 41 while the region underneath the nitride deposits 757 does not oxidize. Only the exposed surfaces of the wafer guard area 703 oxidize. Therefore, no oxide 709 grows on the wafer area 753 of the electrode 210. The growth of the Silicon Dioxide layer 709 by oxidation, consumes the Silicon wafer area 703 of the guard 120 or 125. The amount of Silicon wafer area 703 consumed is directly proportional to the thickness of the oxide grown. For example, 1 micron of oxide grown consumes 0.45 microns of the Silicon wafer area 703; hence, the thickness of the Silicon wafer decreases by 0.45 microns.

[0054] Referring to Figures 42 and 52, the oxide layer 709 is etched, using for example standard etching techniques well known in the art, to remove the oxide layer 709 (830). Since the oxide layer 709 consumed about 0.45 microns of the Silicon wafer area 703, the remaining wafer thickness will be (h — 0.45) microns. The standard oxide etches will not affect the silicon nitride layer 707 on the wafer area 753 of the electrode 210. A person skilled in the art would appreciate that steps 825 and 830 in Figure 57, used for reducing the thickness of the wafer area 703, can be replaced by either DRlE of the wafer area 703 or by wet etching.

[0055] The wafer areas 703 and 753 are further oxidized to grow about 2 microns of oxide layer 713, as shown in Figures 43 and 53 (835). The region underneath the nitride layer 707 does not oxidize, while those exposed surfaces of the wafer area 703 oxidize. The growth of oxide layer 713 consumes the wafer area 703 of the guard 120 or 125. Since about 2 microns of oxide 713 is grown, 0.9 microns of the Silicon wafer area 703 is consumed. Relative to the initial wafer thickness h, the current thickness of the wafer area 703 will be 1.35 microns less, while the oxide layer 713 extends 0.65 microns further from the initial wafer thickness h. [0056] Referring to Figures 44 and 54, photoresist layer 711 is deposited on top of the oxide layer 713 for the guard 120 or 125, and on top of the nitride layer 707 for the electrode 210 (840). Figures 45 and 55 shows the result of patterning the wafer areas with a photomask and developing. The guard wafer area 703 remains coated with photoresist 711 to protect the oxide layer 713 that will form the direct wafer bonds, and photoresist 711 in the wafer area 753 the for electrode 210 is removed (835). As shown in Figure 56, the nitride layer 707 is etched using selective etching, such as wet or plasma techniques, to remove the nitride layer 707 (850), while the photoresist 711 for the guards 120 or 125 protects the oxide layer 713 from the etching process (850) as shown in Fig. 46. Finally, the electrode 210 and the guard layers 120 and 125 are patterned using standard photolithography, then DRIE is used to form, for example, the structures shown in Figure 2 (855).

[0057] One advantage of the present embodiment is that the thickness of the silicon wafer area 703 is reduced before thermal bond oxide is grown. This allows a thick oxide layer (for example, 2 microns) to be grown for parasitic capacitance reduction, while keeping the signal gap 320 small.

[0058] By way of illustration, the parasitic capacitance can be increased by performing oxidation and etching twice for the guard 120 or 125, and processing the proof mass layer per prior art fabrication methods. If about 1 micron of oxide is grown and then etched away, followed by 2 microns of oxide growth, then about 1.35 microns of the guard silicon wafer area 703 will be consumed. The proof mass layer 130 will contribute 1 micron to the bond line 305 and 1 micron to the signal gap 320. Hence, the bond line thickness 305 would increase to 3 microns, thereby decreasing parasitic capacitance by 33%. The signal gap 320 would be about 1.65 microns (0.65 microns from the electrode and 1 micron from the proof mass paddle 205). Accordingly, by using the method embodying the present invention, a 21% increase in signal capacitance over the prior art design would result. The ratio of signal capacitance to parasitic capacitance would increase by about 82%.

[0059] In another embodiment, the ration of signal capacitance to parasitic capacitance can be increased by performing the method embodying the present invention, illustrated in Figure 57 for the guard 120 or 125 and illustrated in Figure 36 on both sides of the proof mass layer 130. On the guard layer 120 or 125, 0.9 microns of oxide can be removed by growing 2 microns of oxide (825) and etching it away (830), or by DRIE, or by wet etching to remove 0.9 microns of silicon. Subsequently, 2 microns of oxide would be grown (835). On the proof mass layer 130, 2 microns of oxide are grown in the bond area 305. The result would be a bond line thickness 305 of about 4 microns that causes a reduction of parasitic capacitance by a factor of 2. The signal gap 320 would be about 1.3 microns that causes a 54% increase of signal capacitance. Overall. The ration of signal capacitance to parasitic capacitance would increase by about 208%.

[0060] The improvement in signal capacitance to parasitic capacitance ration depends on what minimum P-E gap can be used and what oxide thickness is grown. The amount of silicon recess before oxidation would have to be adjusted to end up with the correct gap 320 after oxidation.

Claims

CLAIMSWhat Is Claimed Is:

1. A fabrication method for reducing parasitic capacitance in a semiconductor device having a guard layer separated from a proof mass layer by a bond line, and an electrode separated by a signal gap from the proof mass paddle, the method comprising the steps of: applying a first nitride layer on a wafer area for the electrode, the first nitride layer shielding the wafer area for the electrode from oxidation; oxidizing a wafer area for the guard to form a first oxide layer, the first oxide layer increasing the bond line thickness between the guard layer and the proof mass layer; and etching the first nitride layer on the wafer area of the electrode to remove the nitride layer.

2. The method of claim 1, further comprises the steps of: before the step of applying the first nitride layer, applying a first photoresist layer on the wafer area for the electrode and the wafer area for the guard; and exposing the first photoresist layer on the wafer area for the electrode and the wafer area for the guard with a photomask to remove the first photoresist layer from the wafer area for the electrode.

3. The method of claim 2, further comprises the step of removing the first photoresist layer from the wafer area for the guard after the step of applying a first nitride layer but before the step of oxidizing the wafer area for the guard.

4. The method of claim 1, further comprises the steps of: etching the first oxide layer on the wafer area for the guard before the step of etching the first nitride layer; and oxidizing the wafer area for the guard to form a second oxide layer on the surface, the second oxide layer increasing the bond line thickness between the guard layer and the proof mass layer and decreasing the thickness of the wafer area for the guard.

5. The method of claim 1, further comprises the steps of: applying a second nitride layer on a wafer area for the proof mass paddle, the second nitride layer shielding the wafer area for the proof mass paddle from oxidation; oxidizing a wafer area for the proof mass paddle to form a third oxide layer on the surface, the third oxide layer increasing the bond line thickness between the guard layer and the proof mass layer; and etching the second nitride layer on the wafer area of the proof mass paddle.

6. The method of claim 5, further comprises the steps of: before the step of applying the second nitride layer, applying a second photoresist layer on the wafer area for the proof mass paddle and the wafer area for the proof mass layer; and exposing the second photoresist layer on the wafer area for the proof mass paddle and the wafer area for the proof mass layer with a photomask to remove the second photoresist layer from the wafer area for the proof mass paddle.

7. The method of claim 6, further comprises the step of removing the second photoresist layer from the wafer area for the proof mass layer after the step of applying a second nitride layer but before the step of oxidizing the wafer area for the proof mass layer.

8. The method of claim 5, further comprises the steps of: etching the third oxide layer on the wafer area for the proof mass layer before the step of etching the second nitride layer; and oxidizing the wafer area for the proof mass layer to form a fourth oxide layer on the surface, the fourth oxide layer increases the bond line thickness between the guard layer and the proof mass layer and decreases the thickness of the wafer area for the proof mass layer.

9. The method of claims 1 or 5, wherein the semiconductor device is a MEMS device.

10. The method of claims 1 or 5, wherein the first oxide layer and the third oxide layer have a thickness of about 1 micron.

11. The method of claims 1 or 5, wherein the second oxide layer and the fourth oxide layer have a thickness of about 2 microns.

12. The method of claims 1 or 5, wherein the first nitride layer and the second nitride layer have a thickness of about 1000 A.

13. A fabrication method for reducing parasitic capacitance in a MEMS device, the MEMS device having a guard layer separated from a proof mass layer by a bond line, and an electrode separated by a signal gap from a proof mass paddle, the method comprising the steps of: applying a first nitride layer on a wafer area for the proof mass paddle, the first nitride layer shielding the wafer area for the proof mass paddle from oxidation; oxidizing a wafer area for the proof mass layer to form a first oxide layer on the surface, the oxide layer increasing the bond line thickness between the guard layer and the proof mass layer; and etching the first nitride layer on the wafer area of the proof mass paddle.

14. The method of claim 13, further comprises the steps of: before the step of applying the first nitride layer, applying a first photoresist layer on the wafer area for the proof mass paddle and the wafer area for the proof mass layer; and exposing the first photoresist layer on the wafer area for the proof mass paddle and the wafer area for the proof mass layer with a photomask to remove the first photoresist layer from the wafer area for the proof mass paddle.

15. The method of claim 14, further comprising the step of removing the first photoresist layer from the wafer area for the proof mass layer after the step of applying a first nitride layer but before the step of oxidizing the wafer area for the proof mass layer.

16. The method of claim 13, further comprising the steps of: etching the first oxide layer on the wafer area for the proof mass layer before the step of etching the first nitride layer; and oxidizing the wafer area for the proof mass layer to form a second oxide layer on the surface, the second oxide layer increasing the bond line thickness between the guard layer and the proof mass layer and decreasing the thickness of the wafer area for the proof mass layer.

17. The method of claim 13, further comprises the steps of: applying a second nitride layer on a wafer area for the electrode, the second nitride layer shielding the wafer area for the electrode from oxidation to prevent a decrease in the signal gap during assembly; oxidizing a wafer area for the guard to form a third oxide layer on the surface, the third oxide layer increasing the bond line thickness between the guard layer and the proof mass layer; and etching the second nitride layer on the wafer area of the electrode.

18. The method of Claim 17, further comprises the steps of: before the step of applying the second nitride layer, applying a second photoresist layer on the wafer area for the electrode and the wafer area for the guard; and exposing the second photoresist layer on the wafer area for the electrode and the wafer area for the guard with a photomask to remove the second photoresist layer from the wafer area for the electrode.

19. The method of Claim 18, further comprises the step of removing the second photoresist layer from the wafer area for the guard after the step of applying a second nitride layer but before the step of oxidizing the wafer area for the guard.

20. The method of Claim 17, further comprises the steps of: etching the third oxide layer on the wafer area for the guard before the step of etching the guard; and oxidizing the wafer area for the guard to form a fourth oxide layer on the surface, the fourth oxide layer increasing the bond line thickness between the guard layer and the proof mass layer and decreasing the thickness of the wafer area for the guard.

21. The method of Claims 13 or 17, wherein the first oxide layer and the third oxide layer have a thickness of about 1 micron.

22. The method of Claims 13 or 17, wherein the second oxide layer and the fourth oxide layer have a thickness of about 2 microns.

23. The method of Claims 13 or 17, wherein the first nitride layer and the second nitride layer have a thickness of about 1000 A.

24. A method for fabricating a MEMS cell with reduced parasitic capacitance, the MEMS cell having a guard layer separated from a proof mass layer by a bond line, and an electrode separated by a signal gap from a proof mass paddle, the method comprising the steps of: applying a First photoresist layer on the wafer area for the electrode and the wafer area for the guard; exposing the first photoresist layer on the wafer area for the electrode and the wafer area for the guard with a photomask to remove the first photoresist layer from the wafer area for the electrode; applying a first nitride layer on a wafer area for the electrode and on the first photoresist layer applied to the surface of the wafer area for the guard, the first nitride layer shielding the wafer area for the electrode from oxidation; removing the first photoresist layer from the wafer area for the guard; oxidizing a wafer area for the guard to form a first oxide layer on the surface, the first oxide layer increasing the bond line thickness between the guard layer and the proof mass layer; etching the first nitride layer on the wafer area of the electrode.

25. The method of Claim 24, further comprising the steps of: etching the first oxide layer on the wafer area for the guard before the step of etching the first nitride layer; and oxidizing the wafer area for the guard to form a second oxide layer on the surface, the second oxide layer increasing the bond line thickness between the guard layer and the proof mass layer and decreasing the thickness of the wafer area for the guard.

26. The method of Claim 24, further comprising the steps of: applying a second photoresist layer on the wafer area for the proof mass paddle and the wafer area for the proof mass layer; and removing the second photoresist layer from the wafer area for the proof mass layer; exposing the second photoresist layer on the wafer area for the proof mass paddle and the wafer area for the proof mass layer with a photomask to remove the second photoresist layer from the wafer area for the proof mass paddle; applying a second nitride layer on a wafer area for the proof mass paddle and on the second photoresist layer applied to the surface of the wafer area for the proof mass layer, the second nitride layer shielding the wafer area for the proof mass paddle from oxidation; oxidizing a wafer area for the proof mass layer to form a third oxide layer on the surface, the third oxide layer increasing the bond line thickness between the guard layer and the proof mass layer; and etching the second nitride layer on the wafer area of the proof mass paddle.

27. The method of Claim 26, further comprising the steps of: etching the third oxide layer on the wafer area for the proof mass layer before the step of etching the second nitride layer; and oxidizing the wafer area for the proof mass layer to form a fourth oxide layer on the surface, the fourth oxide layer increases the bond line thickness between the guard layer and the proof mass layer and decreases the thickness of the wafer area for the proof mass layer.

28. The method of Claims 24 or 26, wherein the first oxide layer and the third oxide layer have a thickness of about 1 micron.

29. The method of Claims 24 or 26, wherein the second oxide layer and the fourth oxide layer have a thickness of about 2 microns.

30. The method of Claims 24 or 26, wherein the first nitride layer and the second nitride layer have a thickness of about 1000 A.