WO2006121409A1 - Procede et dispositif pour l'emission-reception de signaux xdsl et hpna dans un reseau - Google Patents

Procede et dispositif pour l'emission-reception de signaux xdsl et hpna dans un reseau Download PDF

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Publication number
WO2006121409A1
WO2006121409A1 PCT/SG2005/000141 SG2005000141W WO2006121409A1 WO 2006121409 A1 WO2006121409 A1 WO 2006121409A1 SG 2005000141 W SG2005000141 W SG 2005000141W WO 2006121409 A1 WO2006121409 A1 WO 2006121409A1
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Prior art keywords
signal
sampling rate
adsl
bits per
per sample
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PCT/SG2005/000141
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English (en)
Inventor
Juraj Povazanec
Biju Sukumaran
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Infineon Technologies Ag
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Priority to PCT/SG2005/000141 priority Critical patent/WO2006121409A1/fr
Publication of WO2006121409A1 publication Critical patent/WO2006121409A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/0008—Modulated-carrier systems arrangements for allowing a transmitter or receiver to use more than one type of modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems

Definitions

  • the invention relates to a method and apparatus for receiving and transmitting frequency division multiplexed signals comprising a DMT (Discrete Multi Tone) modulated signal and a HPNA (Home Phone Networking Association) signal. Particularly, but not exclusively, the invention relates to a method and apparatus for receiving and transmitting a ADSL (Asymmetric Digital Subscriber Line) signal frequency division multiplexed with a HPNA signal.
  • ADSL Asymmetric Digital Subscriber Line
  • Digital Subscriber Line (DSL) technology is a family of technologies for connecting an Internet Service Provider (ISP) to a home PC or network.
  • ISP Internet Service Provider
  • DSL Digital Subscriber Line
  • VDSL Very high rate DSL
  • SHDSL Symmetric High bit-rate DSL
  • ADSL ITU-T G.992.x
  • DMT Discrete Multi Tone
  • HPNA Home Phone Networking Association
  • HPNA Home Phone Networking Association
  • FIG 1 shows a typical arrangement in the home incorporating both ADSL and HPNA.
  • the home gateway or modem accesses the Wide Area Network (WAN) via ADSL technology (section 101 ) and the various home devices are all interconnected via HPNA technology (section 103).
  • the ADSL and HPNA use the same phone line.
  • HPNA and ADSL occupy different frequency bands, ADSL occupying between around a few tens of kHZ and around 2MHz (i.e. needing a minimum sampling rate up to around 4 MHz) and HPNA occupying between around 4MHz and 10MHz (i.e. needing a minimum sampling rate of up to around 20 MHz).
  • Incoming ADSL signals are from the WAN so are typically quite noisy. So, the ADSL chip is very concerned with precision of the signal. So, ADSL has a high number of bits per sample (i.e. higher precision) but operates at a lower frequency compared with HPNA.
  • HPNA is concerned with internal signals (i.e. those from another device within the home) so the signals are relatively noise-free. However, it is important that the transmission speed is high. So, HPNA has a lower number of bits per sample (i.e. lower precision) than HPNA but operates at a higher frequency (i.e. higher transmission speed) than ADSL.
  • the ADSL chip 203 and the HPNA chip 205 are both connected to the same phone line 201.
  • Incoming HPNA data on the phone line 201 goes through analogue to digital converter (ADC) 205a, filter 205b, FDQAM demodulator 205c, constellation decoder 205d, descrambler 205e, deframer 205f, controller 205g and into the Ethernet port via Ethernet MAC and PHY.
  • ADC analogue to digital converter
  • filter 205b filters 205b
  • FDQAM demodulator 205c FDQAM demodulator 205c
  • constellation decoder 205d descrambler 205e
  • deframer 205f deframer 205f
  • controller 205g and into the Ethernet port via Ethernet MAC and PHY.
  • outgoing HPNA data goes from the Ethernet port into controller 205g, framer 205h, scrambler 205i, constellation encoder 205j, FDQAM modulator 205k, filter 205
  • the component parts of the HPNA chip are well known.
  • the filters 205a and 205m select the appropriate frequency band.
  • the FDQAM (Frequency Divided Quadrature Amplitude Modulation) modulator 205k QAM modulates the signal onto a signal whose energy is concentrated around two different frequencies, the idea being that, even if one of the two frequency signals is not recoverable, the other one can still be successfully received.
  • the FDQAM demodulator 205c demodulates the incoming signal around the two frequencies.
  • the constellation decoder 205d and the constellation encoder 205j decode and encode the QAM constellation, as is usual for QAM modulated signals.
  • the descrambler 205e unscrambles the incoming signal and the deframer 205f removes the frame format from the incoming data, so that it is ready to go to the Ethernet port.
  • the framer 205h converts the outgoing data into frames and the scrambler 205i scrambles the outgoing signal.
  • ADSL chip 203 incoming ADSL data on the phone line 201 goes through ADC 203a, filter 203b, FFT processor 203c, decoder 203d, descrambler 203e, deframer 203f, controller 203g and into the Ethernet port via Ethernet MAC and PHY.
  • outgoing ADSL data goes from the Ethernet port into controller 203g, framer 203h, scrambler 203i, encoder 203j, IFFT processor 203k, filter 203b, DAC 203I and into the phone line 201.
  • Filter 203b additionally comprises an equalizer and echo canceller since the ADSL signals are external, noisy signals.
  • the FDQAM demodulator 205c of the HPNA chip is replaced with an FFT (Fast Fourier Transform) processor since the ADSL operates at many frequencies rather than just two frequencies as with HPNA.
  • the FDQAM modulator 205k of the HPNA chip is replaced with an IFFT (Inverse Fast Fourier Transform) processor.
  • the constellation decoder 203d and the constellation encoder 203j include a Viterbi decoder and a Trellis encoder respectively, in order to reduce errors in the ADSL signal.
  • Module 203e includes a descrambler, a de-interleaver and an RS decoder and the module 203i includes a scrambler, an interleaver and an RS encoder, for similar reasons.
  • the ADSL and HPNA can coexist on the same phone line using frequency division multiplexing and this is easy for ADSL and HPNA because they use completely different, non-overlapping frequency bands.
  • the arrangement of Figure 2 does the splitting of the incoming signal (from a single frequency division multiplexed signal on the phone line into separate HPNA and ADSL signals) and the combining of the outgoing signal (from separate HPNA and ADSL signals into a single frequency division multiplexed signal for the phone line) immediately after the phone line port before the ADC and DAC on each chip. This is typically performed by a transformer (or another passive circuit) to combine/split the analogue signals.
  • each ADC and DAC tend to operate with high frequency signals with a low number of bits per sample. So, in actual fact, in each ADC there is included a downsampler (not shown) on the downstream side which converts the high frequency, low precision signals from the ADC to lower frequency, higher precision signals suitable for digital signal processing. Similarly, in each DAC there is included an upsampler (not shown) on the upstream side which converts the low frequency, high precision signals for the digital signal processing into higher frequency, lower precision signals for the DAC and ultimately for the phone line.
  • the known arrangement shown in Figure 2 would be similar for all DMT modulated signals, not only ADSL.
  • apparatus connectable to a phone line for receiving and transmitting frequency division multiplexed signals comprising a ADSL (Asymmetric Digital Subscriber Line) signal and a HPNA (Home Phone Networking Association) signal
  • the apparatus comprising: a receiver comprising: an analogue to digital converter for converting an analogue signal received on the phone line to a digital signal at sampling rate R and having N bits per sample; a first decimator for reducing the sampling rate of the digital signal from R to R' and increasing the number of bits per sample from N to N 1 , R 1 being a suitable sampling rate for HPNA signals and N 1 being a suitable number of bits per sample for HPNA signals; and a second decimator for reducing the sampling rate of the digital signal from R' to R" and increasing the number of bits per sample from N 1 to N", R" being a suitable sampling rate for ADSL signals and N" being a suitable number of bits per sample for ADSL signals; and a transmitter comprising: a first interpolator for receiving
  • the apparatus makes use of the decimators and interpolators so that a single analogue to digital converter and a single digital to analogue converter may be used for both the ADSL and the HPNA signals, even though the two signals have different required sampling rates and different required number of bits per sample. This reduces architecture complexity and cost, particularly as DACs and ADCs are often more costly than other components.
  • the apparatus further comprises a HPNA receiver for receiving the digital signal at sampling rate R' and having N 1 bits per sample from the first decimator.
  • the HPNA receiver effectively splits off the signal after it has been downsampled by the first decimator but not yet downsampled by the second decimator.
  • the apparatus may further comprise HPNA processing components connected to the HPNA receiver, for processing the received HPNA signal.
  • the HPNA processing components for processing the received HPNA signal may include one or more of: a filter, a demodulator, a decoder, a descrambler and a deframer.
  • the apparatus further comprises a ADSL receiver for receiving the digital signal at sampling rate R" and having N" bits per sample from the second decimator.
  • the apparatus may further comprise ADSL processing components connected to the ADSL receiver, for processing the received ADSL signal.
  • the ADSL processing components for processing the received ADSL signal may include one or more of: a filter, a demodulator, a decoder, a descrambler and a deframer.
  • the apparatus may comprise processing components for processing the HPNA signal to be transmitted. These processing components may include one or more of: a framer, a scrambler, an encoder, a modulator and a filter.
  • the apparatus may comprise processing components for processing the ADSL signal to be transmitted. These processing components may include one or more of: a framer, a scrambler, an encoder, a modulator and a filter. It is possible for one or all of the processing components for transmitted signals to be combined so that a single set of processing components can deal with both the HPNA signals to be transmitted and the ADSL signals to be transmitted. This will reduce architecture complexity.
  • the first decimator may comprise a plurality of sub-decimators.
  • the second decimator may comprise a plurality of sub-decimators. This may be preferable if a large reduction in sampling rate is required in one or both decimators. It may then be more straightforward to perform the downsampling in a series of steps, for example reducing the sampling rate to half at each step, each step being performed by one of the sub-decimators.
  • the first interpolator may comprise a plurality of sub-interpolators.
  • the second interpolator may comprise a plurality of sub-interpolators. This may be preferable if a large increase in sampling rate is required in one or both interpolators. It may then be more straightforward to perform the upsampling in a series of steps, for example multiplying the sampling rate by two at each step, each step being performed by one of the sub-interpolators.
  • the minimum sampling rate of the HPNA signals is 20 MHz and the minimum sampling rate of the ADSL signals is 4.4 MHz.
  • a semiconductor chip comprising the apparatus described above.
  • a modem for connecting to a phone line comprising such a semiconductor chip.
  • a modem for connecting to a phone line comprising the apparatus described above.
  • apparatus connectable to a phone line
  • the apparatus comprising: an analogue to digital converter for converting analogue signals received on the phone line to digital signals; a splitting filter for downsampling the digital signals received from the analogue to digital converter; components for processing received signals; components for processing signals to be transmitted; a joining filter for upsampling digital signals to be transmitted; and a digital to analogue converter for converting digital signals to analogue signals for transmitting on the phone line
  • the apparatus is operable in one of two modes, in the first mode, the apparatus being arranged to receive and transmit VDSL signals along the phone line and, in the second mode, the apparatus being arranged to receive and transmit frequency division multiplexed signals, comprising ADSL signals and HPNA signals, along the phone line.
  • VDSL typically requires much more processing power than ADSL. So the apparatus requires high processing power for the first mode VDSL operation. Thus, when the apparatus is switched to the second mode, there is sufficient processing power to handle both the ADSL and HPNA. In the second mode, the apparatus performs the splitting of the received ADSL and HPNA signals and the combining of the ADSL and HPNA signals to be transmitted, in the digital domain i.e. upstream of the digital to analogue converter for transmission and downstream of the analogue to digital converter for receiving.
  • the splitting filter comprises: a first decimator for reducing the sampling rate of the digital signal to R' and increasing the number of bits per sample to N', R' being a suitable sampling rate for HPNA signals and N' being a suitable number of bits per sample for HPNA signals; and a second decimator for reducing the sampling rate of the digital signal from R 1 to R" and increasing the number of bits per sample from N' to N", R" being a suitable sampling rate for ADSL signals and N" being a suitable number of bits per sample for ADSL signals.
  • the incoming VDSL signals do not need to be downsampled at all, because of the high operating frequency of VDSL.
  • the incoming digital signal is downsampled at the first step which isolates the HPNA part of the signal. Then, the digital signal is downsampled at the second step which isolates the ADSL part of the signal.
  • the first and/or second decimators may comprise a plurality of sub-decimators. This will be advantageous if a big reduction in sampling rate is required, as it may be more straightforward to perform the downsampling in a series of steps.
  • the splitting filter may further comprise a HPNA receiver for receiving the digital signal at sampling rate R' and having N' bits per sample from the first decimator. This receiver may be used to split off the HPNA part of the signal and will thus only be useful when the apparatus is operating in the second mode.
  • the splitting filter may further comprise a receiver for receiving the digital signal at sampling rate R" and having N" bits per sample from the second decimator. The receiver may be arranged to receive ADSL signals.
  • the joining filter comprises: a first interpolator for receiving ADSL signals at sampling rate r" having n" bits per sample, for increasing the sampling rate of the signal from r" to r' and decreasing the number of bits per sample from n" to n'; an adder for combining the signal at sampling rate r' having n' bits per sample with a HPNA signal, when the apparatus is operating the second mode; and a second interpolator for increasing the sampling rate of the digital signal to r and decreasing the number of bits per sample to n.
  • the outgoing ADSL signal is upsampled at the first step (in the first interpolator) which produces a signal having a sampling rate and a number of bits per sample that is similar to that of HPNA. Then the upsampled signal and the HPNA signal are combined in the adder. Then, the resulting digital signal is upsampled at the second step (in the second interpolator).
  • the first and/or second interpolators may comprise a plurality of sub- interpolators. This will be advantageous if a big increase in sampling rate is required, as it may be more straightforward to perform the upsampling in a series of steps.
  • the components for processing received signals may include one or more of: a filter, a demodulator, a decoder, a descrambler and a deframer.
  • the components for processing signals to be transmitted may include one or more of: a framer, a scrambler, an encoder, a modulator and a filter.
  • a semiconductor chip comprising the apparatus of the second aspect of the invention.
  • a modem for connecting to the phone line the modem comprising such a semiconductor chip.
  • a modem for connecting to the phone line the modem comprising the apparatus of the second aspect of the invention.
  • a method for receiving and processing a frequency division multiplexed signal comprising a ADSL (Asymmetric Digital Subscriber Line) signal and a HPNA (Home Phone Networking Association) signal
  • the method comprising the steps of: receiving the frequency division multiplexed signal from a phone line; converting the received signal to a digital signal at a sampling rate R having N bits per sample; reducing the sampling rate of the digital signal from R to R' while increasing the number of bits per sample from N to N 1 , R 1 being a suitable sampling rate for HPNA signals and N' being a suitable number of bits per sample for HPNA signals; processing the digital signal having a sampling rate of R' and having N' bits per sample; reducing the sampling rate of the digital signal from R' to R" while increasing the number of bits per sample from N' to N", R" being a suitable sampling rate for ADSL signals and N" being a suitable number of bits per sample for ADSL signals; and processing the digital signal having a sampling rate of R" and having N
  • the method converts the received analogue signal to a digital signal before splitting the signal.
  • the step of reducing the sampling rate of the digital signal from R to R' preferably comprises a decimator reducing the sampling rate of the digital signal from R to R'.
  • the step of reducing the sampling rate of the digital signal from R to R' may comprise reducing the sampling rate of the digital signal from R to a sampling rate intermediate between R and R' and reducing the sampling rate of the digital signal from the sampling rate intermediate between R and R' to R'.
  • the decimator comprises a plurality of sub-decimators. This may be advantageous if a large reduction in sampling rate is required in the decimator. It may then be more straightforward to perform the downsampling in a series of steps, for example reducing the sampling rate to half at each step, each step being performed by one of the sub-decimators.
  • the step of reducing the sampling rate of the digital signal from R' to R" preferably comprises a decimator reducing the sampling rate of the digital signal from R' to R".
  • the step of reducing the sampling rate of the digital signal from R' to R" may comprise reducing the sampling rate of the digital signal from R' to a sampling rate intermediate between R' and R" and reducing the sampling rate of the digital signal from the sampling rate intermediate between R' and R" to R".
  • the decimator comprises a plurality of sub-decimators. This may be advantageous if a large reduction in sampling rate is required in the decimator. It may then be more straightforward to perform the downsampling in a series of steps, for example reducing the sampling rate to half at each step, each step being performed by one of the sub-decimators.
  • the digital signal having a sampling rate of R' and having N' bits per sample is the HPNA signal derived from the frequency division multiplexed signal received on the phone line.
  • the step of processing the digital signal having a sampling rate of R' and having N' bits per sample may comprise HPNA components processing the digital signal.
  • the step of processing the digital signal having a sampling rate of R' and having N' bits per sample may comprise one or more of the steps of: filtering the signal, demodulating the signal, decoding the signal, descrambling the signal and deframing the signal.
  • the digital signal having a sampling rate of R" and having N" bits per sample is the ADSL signal derived from the frequency division multiplexed signal received on the phone line.
  • the step of processing the digital signal having a sampling rate of R" and having N" bits per sample may comprise ADSL components processing the digital signal.
  • the step of processing the digital signal having a sampling rate of R" and having N" bits per sample may comprise one or more of the steps of: filtering the signal, demodulating the signal, decoding the signal, descrambling the signal and deframing the signal
  • the step of converting the received signal to a digital signal preferably comprises an analogue to digital converter converting the received signal to a digital signal.
  • the minimum sampling rate of the HPNA signals is 20 MHz and the minimum sampling rate of the ADSL signals is 4.4 MHz.
  • R 70 MHz
  • N" 13.
  • a method for receiving and processing a frequency division multiplexed signal comprising a HPNA (Home Phone Networking Association) signal and an ADSL (Asymmetric Digital Subscriber Line) signal, the method comprising the steps of: receiving the frequency division multiplexed signal from a phone line; then converting the received signal to a digital signal; then splitting the HPNA signal and the ADSL signal by downsampling the digital signal in at least two steps, a first step isolating the HPNA signal, a second step isolating the ADSL signal.
  • HPNA Home Phone Networking Association
  • ADSL Asymmetric Digital Subscriber Line
  • a method for processing and transmitting a frequency division multiplexed signal comprising a ADSL (Asymmetric Digital Subscriber Line) signal and a HPNA (Home Phone Networking Association) signal
  • the method comprising the steps of: processing a ADSL signal to be transmitted, the ADSL signal having a sampling rate of R" and having N" bits per sample; increasing the sampling rate of the ADSL signal from R" to R 1 while decreasing the number of bits per sample from N" to N'; processing a HPNA signal to be transmitted; combining the HPNA signal and the digital signal having sampling rate R' and N' bits per sample, into a single digital signal; increasing the sampling rate of the single digital signal to R while decreasing the number of bits per sample to N; converting the digital signal having sampling rate R and having N bits per sample into an analogue frequency division multiplexed signal; and transmitting the frequency division multiplexed signal along a phone line.
  • ADSL Asymmetric Digital Subscriber Line
  • HPNA Home Phone Networking Association
  • the method combines the two signals in the digital domain i.e. before converting to an analogue signal to be transmitted over the phone line. This means that a single digital to analogue conversion step may be used.
  • the step of increasing the sampling rate of the ADSL signal from R" to R' preferably comprises an interpolator increasing the sampling rate of the ADSL signal from R" to R'.
  • the step of increasing the sampling rate of the ADSL signal from R" to R' may comprise increasing the sampling rate of the signal from R" to a sampling rate intermediate between R" and R' arid increasing the sampling rate of the signal from the sampling rate intermediate between R" and R' to R'.
  • the interpolator comprises a plurality of sub-interpolators. This may be advantageous if a large increase in sampling rate is required in the interpolator. It may then be more straightforward to perform the upsampling in a series of steps, for example increasing the sampling rate to twice at each step, each step being performed by one of the sub-interpolators.
  • the step of increasing the sampling rate of the single digital signal to R preferably comprises an interpolator increasing the sampling rate of the single digital signal to R.
  • the step of increasing the sampling rate of the single digital signal to R may comprise increasing the sampling rate of the signal to a sampling rate less than R then increasing the sampling rate of the signal from the sampling rate less than R to R.
  • the interpolator comprises a plurality of sub-interpolators. This may be advantageous if a large increase in sampling rate is required in the interpolator. It may then be more straightforward to perform the upsampling in a series of steps, for example increasing the sampling rate to twice at each step, each step being performed by one of the sub-interpolators.
  • the step of processing the ADSL signal to be transmitted may comprise ADSL components processing the signal.
  • the step of processing the ADSL signal may comprise one or more of the steps of: framing the signal, scrambling the signal, encoding the signal, modulating the signal and filtering the signal.
  • the step of processing the HPNA signal to be transmitted may comprise HPNA components processing the signal.
  • the step of processing the HPNA signal may comprise one or more of the steps of: framing the signal, scrambling the signal, encoding the signal, modulating the signal and filtering the signal.
  • the step of converting the digital signal having sampling rate R and having N bits per sample into an analogue frequency division multiplexed signal preferably comprises a digital to analogue converter converting the digital signal having sampling rate R and having N bits per sample into an analogue frequency division multiplexed signal.
  • the minimum sampling rate of the HPNA signals is 20 MHz and the minimum sampling rate of the ADSL signals is 4.4 MHz.
  • a method for processing and transmitting a frequency division multiplexed signal comprising a HPNA (Home Phone Networking Association) signal and an ADSL (Asymmetric Digital Subscriber Line) signal
  • the method comprising the steps of: combining the HPNA signal and the ADSL signal by upsampling the ADSL signal, combining the upsampled ADSL signal with the HPNA signal and upsampling the combined signal; converting the combined digital signal to an analogue frequency division multiplexed signal; then transmitting the frequency division multiplexed signal along a phone line.
  • HPNA Home Phone Networking Association
  • ADSL Asymmetric Digital Subscriber Line
  • a semiconductor chip for carrying out one or more of the methods described above.
  • a modem for connecting to a phone line for carrying out one or more of the methods described above.
  • Figure 1 is a diagram of a typical home network of ADSL and HPNA sharing the same phone line; and Figure 2 is a diagram of known modem architecture for handling ADSL and
  • Figure 3 is a diagram of modem architecture according to a first embodiment of the invention.
  • Figure 4 is a schematic representation of downsampling used with an ADC
  • Figure 5 shows operation of the splitting filter of Figure 3
  • Figure 6 is a schematic representation of upsampling used with a DAC
  • Figure 7 shows operation of the joining filter of Figure 3
  • Figure 8 is a diagram of modem architecture according to a second embodiment of the invention.
  • Figure 3 shows a solution according to a first embodiment of the invention for implementing ADSL and HPNA alongside one another in a modem or home gateway. Between the filters and the Ethernet port, the arrangement is the same as the Figure 2 arrangement, but, in the arrangement of Figure 3, a single ADC and DAC are used for both the ADSL and the HPNA. In other words, the splitting/combining point (for splitting the two incoming signals on the phone line or for combining the two outgoing signals for the phone line) is shifted to the digital domain behind the ADC and DAC.
  • the HPNA portion includes filter 205b, FDQAM demodulator 205c, constellation decoder 205d, descrambler 205e, deframer 205f and controller 205g for the signal incoming from the phone line to the Ethernet port and controller 205g, framer 205h, scrambler 205i, constellation encoder 205j, FDQAM modulator 205k and filter 205I for the signal outgoing from the Ethernet port to the phone line.
  • the ADSL portion includes filter 203b, FFT processor 203c, decoder 203d (including Viterbi decoder), descrambler 203e (including de-interleaver and RS decoder), deframer 203f and controller 203g for the signal incoming from the phone line to the Ethernet port and controller 203g, framer 203h, scrambler 203i (including interleaver and RS encoder), encoder 203j (including Trellis encoder), IFFT processor 203k and filter 203b for the signal outgoing from the Ethernet port to the phone line.
  • a single ADC 301 and DAC 305 are used for both the HPNA and ADSL. This is advantageous because the ADC and DAC are often the most costly parts of a modem.
  • a splitting filter 303 is used downstream of the ADC and a joining filter 307 is used upstream of the DAC. Operation of the ADC 301 , in conjunction with the splitting filter 303 is described in more detail below with reference to Figure 4 and 5 and operation of the DAC 305, in conjunction with the joining filter 307, is described in more detail below with reference to Figures 6 and 7.
  • FIG. 4 is a schematic diagram showing downsampling which is necessary with an ADC.
  • the downsampling is done in three stages (although any number of stages might be envisaged).
  • the 35 MHz, 8 bits per sample signal from the ADC 401 is incoming to first downsampler 403, which decimates the signal to produce a 17 MHz signal with 10 bits per sample.
  • This signal is incoming to the second downsampler 405 which decimates the signal further to produce a 8.8 MHz signal with 12 bits per sample.
  • third downsampler 407 which decimates the signal further to produce a 4.4 MHz signal with 13 bits per sample.
  • the sampling frequency is reduced (in this case to about half of the previous frequency) but the precision (i.e. bits per sample) is increased.
  • This downsampling may be used with each ADC in Figure 2.
  • ADSL the frequency will be reduced sufficiently to the required ADSL frequency and the bit resolution will be increased sufficiently to the required ADSL precision.
  • HPNA the frequency will be reduced sufficiently to the required HPNA frequency (which is higher than the ADSL frequency) and the number of bits per sample will be increased sufficiently to the required HPNA precision (which is lower than the ADSL precision).
  • Figure 5 shows operation of the splitting filter 303.
  • the splitting filter makes use of the decimation as described with reference to Figure 4 so that HPNA and ADSL can both use the single ADC 301 in Figure 3.
  • the ADSL minimum sampling rate is 4.4 MHz and the bit resolution is 13 bits and the HPNA minimum sampling rate is 20 MHz and the bit resolution is 9 bits.
  • the signal from the ADC 301 is at 70 MHz with a bit resolution of 7 bits. This is a typical high frequency, low precision signal required in an ADC or DAC. That signal is incoming to first downsampler 501 in the splitting filter 303, which decimates the signal to a sampling rate of 23 MHz with 9 bits per sample. (A single downsampler 501 is shown but several individual downsamplers may, in fact, be necessary or preferred.) This signal is a good signal for the HPNA i.e. has appropriate frequency and bit resolution, so the HPNA signal is split off here to HPNA receiver 503. The HPNA signal can then be processed by filter 205b, FDQAM modulator 205c and so on, as shown in Figure 3.
  • the signal will need to be decimated further for the ADSL, however.
  • the signal is fed into second downsampler 505 which decimates the signal to a sampling rate of 4.4 MHz with 13 bits per sample. (A single downsampler 505 is shown but several individual downsamplers may, in fact, be necessary or preferred.)
  • This signal is now a good signal for the ADSL i.e. has appropriate frequency and bit resolution, so is fed into ADSL receiver 507.
  • the ADSL signal can then be processed by filter 203b, FFT processor 203c and so on, as shown in Figure 3.
  • the arrangement makes use of the fact that most high precision ADCs are built from lower precision but high speed ADCs, using known techniques like Sigma-Delta, and then use decimation to gain the required precision.
  • the arrangement also makes use of the fact that, as the speed is decreased to ADSL speed (and the precision increased) downstream of the ADC, at some intermediate point, the signal has a speed (and precision) that is appropriate for HPNA, so the HPNA signal can be fed off here, avoiding the need for completely separate HPNA architecture.
  • FIG. 6 is a schematic diagram showing upsampling which is necessary with a DAC.
  • the upsampling is done in three stages (although any number of stages might be envisaged).
  • a 4.4 MHz sample with 13 bit resolution is output from the application and is fed into first upsampler 601 , which interpolates the signal to produce a 8.8 MHz signal with 11 bits per sample.
  • This signal is incoming to the second upsampler 603 which interpolates the signal further to produce a 17 MHz signal with 9 bits per sample.
  • third upsampler 605 which interpolates the signal further to produce a 35 MHz signal with 6 bits per sample.
  • This signal is sufficiently high speed, but low precision, for the DAC 607.
  • the sampling frequency is increased (in this case to about twice the previous frequency) but the precision (i.e. bits per sample) is decreased.
  • This upsampling may be used with each DAC in Figure 2.
  • ADSL the frequency will be increased sufficiently from the ADSL frequency to the DAC frequency, with a corresponding decrease in precision.
  • HPNA the frequency will be increased sufficiently from the HPNA frequency (which is already higher than the ADSL), with a corresponding decrease in precision.
  • Figure 7 shows operation of the joining filter 303.
  • the joining filter makes use of the interpolation as described with reference to Figure 6 so that HPNA and ADSL can both use the single DAC 305 in Figure 3.
  • the ADSL minimum sampling rate is 4.4 MHz and the bit resolution is 13 bits and the HPNA minimum sampling rate is 20 MHz and the bit resolution is 9 bits.
  • the signal from the ADSL application 701 is at 4.4 MHz with a bit resolution of 13 bits. That signal is fed into first upsampler 703 in the joining filter 307, which interpolates the signal to a sampling rate of 23 MHz with 10 bits per sample. (A single upsampler 703 is shown but several individual upsamplers may, in fact, be necessary or preferred.) This signal is of a similar rate and precision to the signal from the HPNA application 705, which is also at 23 MHz but with a bit resolution 9 bits. The two signals need to be combined so that they can be both transmitted along the single phone line, so they are both fed into added 707 which combines the two signals into a single signal of 23 MHz with 11 bits per sample.
  • This signal is still not high enough frequency for the DAC so is fed into a second upsampler 709 which interpolates the signal to a sampling rate of 70 MHz with 7 bits per sample. (A single upsampler 709 is shown but several individual upsamplers may, in fact, be necessary or preferred.)
  • This signal is now a typical high frequency, but low precision, signal required in a ADC or DAC so can be fed into the DAC 305 and from there to the phone line.
  • the arrangement makes use of the fact that most high precision DACs are built from lower precision but high speed DACs, using known techniques like Sigma-Delta, and use interpolation to gain the required frequency for the DAC.
  • the arrangement also makes use of the fact that, as the ADSL signal rate is increased (and the precision decreased) upstream of the DAC, at some intermediate point, the signal has a speed (and precision) that is appropriate for HPNA, so the HPNA signal and interpolated ADSL signal can be combined here which avoids the need for completely separate HPNA architecture.
  • FIG. 8 shows a solution according to a second embodiment of the invention for implementing ADSL and HPNA alongside one another in an existing modem which is also operable to work with high processing power VDSL.
  • VDSL the processing power required is high so the existing VDSL architecture in a modem or home gateway, when switched to be used with ADSL would have sufficient spare processing power to incorporate the HPNA in accordance with invention.
  • This allows a single architecture to be multi-purpose without many changes being required and also makes use of the excess processing capability of a VDSL gateway when it is switched to the less demanding ADSL.
  • the modem could operate with VDSL in a first state and could be switched to a second state operating with ADSL and HPNA.
  • the architecture of Figure 8 comprises ADC 801a, splitting filter 801 b, filter 801c, a combined FFT processor (with FDQAM demodulator) and IFFT processor (with FDQAM demodulator) 801 d, a combined encoder (constellation and Trellis) and decoder (constellation and Viterbi) 801 e, a combined scrambler (incorporating interleaver and RS encoder) and descrambler (incorporating de-interleaver and RS decoder) 801f, a combined framer and deframer 801 g and a controller 801 h for the Ethernet port.
  • the architecture of Figure 8 comprises the controller 801 h for the Ethernet port, the combined framer and deframer 801 g, the combined scrambler (incorporating interleaver and RS encoder) and descrambler (incorporating de-interleaver and RS decoder) 801 f, the combined encoder (constellation and Trellis) and decoder (constellation and Viterbi) 801e, the combined FFT processor (with FDQAM demodulator) and IFFT processor (with FDQAM demodulator) 801 d, a filter incorporating an equalizer and echo canceller 801 i, a joining filter 801j and DAC 801 k.
  • the modem operates with VDSL in the usual way and that operation need not be described further.
  • the modem takes advantage of the high VDSL processing power to operate with both ADSL and HPNA.
  • the ADC 801a and splitting filter 801b operate in just the same way as described with reference to Figures 4 and 5.
  • the DAC 801 k and joining filter 801j operate in just the same way as described with reference to Figure 6 and 7.
  • the additional change is that the remaining components, 801c to 801 i are used for both the ADSL and the HPNA.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Telephonic Communication Services (AREA)

Abstract

Dispositif et procédé pour l'émission-réception de signaux FDM à signal ADSL et HPNA. Le dispositif comprend un récepteur et un émetteur. Le récepteur comporte un convertisseur A/N, un premier décimateur réduisant le taux d'échantillonnage du signal numérique en un débit approprié aux signaux HPNA et augmentant le nombre de bits par échantillon jusqu'à un nombre approprié aux signaux HPNA, et un second décimateur réduisant le taux d'échantillonnage du signal numérique en un débit approprié aux signaux ADSL et augmentant le nombre de bits par échantillon jusqu'à un nombre approprié aux signaux ADSL. L'émetteur comprend un premier interpolateur augmentant le taux d'échantillonnage d'un signal ADSL et diminuant le nombre de bits par échantillon de signal ADSL, un additionneur combinant le signal ADSL non échantillonné avec un signal HPNA, un second interpolateur augmentant le taux d'échantillonnage du signal combiné et diminuant le nombre de bits par échantillon du signal combiné et un convertisseur N/A..
PCT/SG2005/000141 2005-05-06 2005-05-06 Procede et dispositif pour l'emission-reception de signaux xdsl et hpna dans un reseau WO2006121409A1 (fr)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001058125A2 (fr) * 2000-02-06 2001-08-09 Coppergate Communications Ltd. Systeme de telecommunications a ligne d'abonne numerique
EP1189420A2 (fr) * 2000-09-13 2002-03-20 Texas Instruments Inc. Modem pour ligne d'abonné numérique compatible avec un réseau domestique

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001058125A2 (fr) * 2000-02-06 2001-08-09 Coppergate Communications Ltd. Systeme de telecommunications a ligne d'abonne numerique
EP1189420A2 (fr) * 2000-09-13 2002-03-20 Texas Instruments Inc. Modem pour ligne d'abonné numérique compatible avec un réseau domestique

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MEHR I ET AL: "A 12-bit integrated analog front-end for broadband wireline networks", PROCEEDINGS OF THE IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE. (CICC 2001). SAN DIEGO, CA, MAY 6 - 9, 2001, IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE.CICC, NEW YORK, NY : IEEE, US, vol. CONF. 23, 6 May 2001 (2001-05-06), pages 119 - 122, XP010546861, ISBN: 0-7803-6591-7 *

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