WO2006109011A3 - Memory management and video processing - Google Patents
Memory management and video processing Download PDFInfo
- Publication number
- WO2006109011A3 WO2006109011A3 PCT/GB2006/001003 GB2006001003W WO2006109011A3 WO 2006109011 A3 WO2006109011 A3 WO 2006109011A3 GB 2006001003 W GB2006001003 W GB 2006001003W WO 2006109011 A3 WO2006109011 A3 WO 2006109011A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- switch
- programs
- shaders
- controller
- render
- Prior art date
Links
- 239000011159 matrix material Substances 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/60—Memory management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T15/00—3D [Three Dimensional] image rendering
- G06T15/50—Lighting effects
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Graphics (AREA)
- Image Generation (AREA)
- Image Processing (AREA)
Abstract
A method of using a matrix switch and render target controller as a mechanism to provide a convenient and organised way of handling render targets. The method comprises of a software or hardware switch that can be used to connect shaders together to enable more complex shaders to be run without exceeding the graphics card maximum pixel shader instructions. The switch can be used to connect render targets into programs and to image processors that can use the render target's contents as a controller for other programs. The render target switch and its controller create a unified video memory architecture, which can be used as a connection point between programs and shaders running on the GPU and CPU and may also incorporate a hi speed buss.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0507252A GB2425030A (en) | 2005-04-09 | 2005-04-09 | Managed network render targets for routing graphical information |
GBGB0507252.5 | 2005-04-09 |
Publications (3)
Publication Number | Publication Date |
---|---|
WO2006109011A2 WO2006109011A2 (en) | 2006-10-19 |
WO2006109011A3 true WO2006109011A3 (en) | 2007-02-15 |
WO2006109011B1 WO2006109011B1 (en) | 2007-04-12 |
Family
ID=34610900
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/GB2006/001003 WO2006109011A2 (en) | 2005-04-09 | 2006-03-17 | Memory management and video processing |
Country Status (2)
Country | Link |
---|---|
GB (1) | GB2425030A (en) |
WO (1) | WO2006109011A2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7710417B2 (en) | 2007-01-15 | 2010-05-04 | Microsoft Corporation | Spatial binning of particles on a GPU |
US8432405B2 (en) | 2008-06-26 | 2013-04-30 | Microsoft Corporation | Dynamically transitioning between hardware-accelerated and software rendering |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1383080A1 (en) * | 2002-07-16 | 2004-01-21 | Microsoft Corporation | Intermediate buffers in a graphics system |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69224084T2 (en) * | 1991-01-15 | 1998-07-23 | Koninkl Philips Electronics Nv | Computer arrangement with multiple buffer data cache and method therefor |
US5798770A (en) * | 1995-03-24 | 1998-08-25 | 3Dlabs Inc. Ltd. | Graphics rendering system with reconfigurable pipeline sequence |
US6067090A (en) * | 1998-02-04 | 2000-05-23 | Intel Corporation | Data skew management of multiple 3-D graphic operand requests |
US6989836B2 (en) * | 2002-04-05 | 2006-01-24 | Sun Microsystems, Inc. | Acceleration of graphics for remote display using redirection of rendering and compression |
-
2005
- 2005-04-09 GB GB0507252A patent/GB2425030A/en not_active Withdrawn
-
2006
- 2006-03-17 WO PCT/GB2006/001003 patent/WO2006109011A2/en active Application Filing
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1383080A1 (en) * | 2002-07-16 | 2004-01-21 | Microsoft Corporation | Intermediate buffers in a graphics system |
Non-Patent Citations (4)
Title |
---|
DUODUO LIAO ET AL: "The design and application of high-resolution 3D stereoscopic graphics display on PC", 8TH INTERNATIONAL CONFERENCE IN CENTRAL EUROPE ON COMPUTER GRAPHICS, VISUALIZATION AND INTERACTIVE DIGITAL MEDIA'2000. UNDER THE AUSPICES OF THE LORD MAYOR OF THE CITY OF PILSEN IN COOPERATION WITH EUROGRAPHOCS AND IFIP WG 5.10. WSCG'2000. CONFERENCE, vol. 3, 2000, pages 70 - 76 vol.3, XP002402183, ISBN: 80-7082-614-6 * |
JIN YOUNG HONG ET AL: "High speed processing of biomedical images using programmable gpu", IMAGE PROCESSING, 2004. ICIP '04. 2004 INTERNATIONAL CONFERENCE ON SINGAPORE 24-27 OCT. 2004, PISCATAWAY, NJ, USA,IEEE, 24 October 2004 (2004-10-24), pages 2455 - 2458, XP010786284, ISBN: 0-7803-8554-3 * |
OWENS, J. D. ET AL: "A Survey of General-Purpose Computation on Graphics Hardware"", EUROGRAPHICS 2005, STATE OF THE ART REPORTS, August 2005 (2005-08-01), pages 21 - 51, XP002402184 * |
PEERCY M S ET AL: "INTERACTIVE MULTI-PASS PROGRAMMABLE SHADING", COMPUTER GRAPHICS. SIGGRAPH 2000 CONFERENCE PROCEEDINGS. NEW ORLEANS, LA, JULY 23 - 28, 2000, COMPUTER GRAPHICS PROCEEDINGS. SIGGRAPH, NEW YORK, NY : ACM, US, 23 July 2000 (2000-07-23), pages 425 - 432, XP001003583, ISBN: 1-58113-208-5 * |
Also Published As
Publication number | Publication date |
---|---|
WO2006109011B1 (en) | 2007-04-12 |
GB0507252D0 (en) | 2005-05-18 |
GB2425030A (en) | 2006-10-11 |
WO2006109011A2 (en) | 2006-10-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ES2959308T3 (en) | Reduced screen bandwidth with multiple resolutions | |
MY142776A (en) | Systems and methods for providing intermediate targets in a graphics system | |
EP2296116A3 (en) | A graphics processing architecture employing a unified shader | |
WO2011109613A3 (en) | Method, system, and apparatus for processing video and/or graphics data using multiple processors without losing state information | |
GB2600346A (en) | Video upsampling using one or more neural networks | |
WO2007056476A3 (en) | Device providing a secure work environment and utilizing a virtual interface | |
WO2008082641A3 (en) | Multi-mode parallel graphics processing systems and methods | |
WO2008060961A3 (en) | Pixel cache for 3d graphics circuitry | |
CO5450258A1 (en) | SYSTEMS AND METHODS TO PROVIDE A CONTROLLABLE TEXTURE SAMPLE | |
WO2008021310A3 (en) | Applying graphical characteristics to graphical objects in a wagering game machine | |
EP1736871A3 (en) | System for executing code during operating system initialization | |
WO2006119078A3 (en) | Transparency-conserving method to generate and blend images | |
EP2133784A3 (en) | Control method of device in storage system for virtualization | |
WO2010017113A3 (en) | Gpu scene composition and animation | |
WO2007001774A3 (en) | Non-destructive processing of digital image data | |
WO2008036231A3 (en) | Multiple parallel processor computer graphics system | |
IN2013MN00405A (en) | ||
EP1591909A3 (en) | Task-oriented processing as an auxiliary to primary computing environments | |
WO2007140338A3 (en) | Graphics processor with arithmetic and elementary function units | |
WO2007109395A3 (en) | Data processor having dynamic control of instruction prefetch buffer depth and method therefor | |
WO2010009175A3 (en) | Programming apis for an extensible avatar system | |
MX340266B (en) | Graphics processing for high dynamic range video. | |
WO2007037843A3 (en) | Method and apparatus for sharing memory in a multiprocessor system | |
WO2010077751A3 (en) | Coprocessor unit with shared instruction stream | |
WO2006123342A3 (en) | System and method for detecting changes in an environment |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWW | Wipo information: withdrawn in national office |
Country of ref document: DE |
|
NENP | Non-entry into the national phase |
Ref country code: RU |
|
WWW | Wipo information: withdrawn in national office |
Country of ref document: RU |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 06710123 Country of ref document: EP Kind code of ref document: A2 |