Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L25/00—Baseband systems
  • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
  • H04L25/06—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
  • H04L25/061—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of DC offset
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
  • H03D1/00—Demodulation of amplitude-modulated oscillations
  • H03D1/02—Details
  • H03D1/04—Modifications of demodulators to reduce interference by undesired signals
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
  • H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
  • H03D3/007—Demodulation of angle-, frequency- or phase- modulated oscillations by converting the oscillations into two quadrature related signals
  • H03D3/008—Compensating DC offsets
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03G—CONTROL OF AMPLIFICATION
  • H03G3/00—Gain control in amplifiers or frequency changers
  • H03G3/20—Automatic control
  • H03G3/30—Automatic control in amplifiers having semiconductor devices
  • H03G3/3052—Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver
  • H03G3/3068—Circuits generating control signals for both R.F. and I.F. stages
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/06—Receivers
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/06—Receivers
  • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/06—Receivers
  • H04B1/16—Circuits
  • H04B1/30—Circuits for homodyne or synchrodyne receivers

Definitions

• FIG. 8 are graphs of the signals passing through the RF circuitry of FIG. 2 with the
• I/Q quadrature mixers 216 for each of the two quadrature paths are employed to convert the RF signal to a low or zero Intermediate Frequency (zero IF) by mixing the received signal with the output of a lowband oscillator (LO) 215.
• LO lowband oscillator
• a baseband analog gain control stage such as a high dynamic range Post Mixer Amplifier (PMA) 218 is used to provide much of the desired receiver dynamic range to minimize the cost and the power consumption of the RF receiver 106.
• PMA Post Mixer Amplifier
• the baseband DC offset correction system architecture and digital correction algorithm 230 overcomes the difficulties of prior art correction systems by employing a two step calibration procedure which is performed during the receiver warmup process.
• This mixed signal control algorithm is able to quickly and accurately compensate for large DC offset steps which occur as a result of large baseband gain changes.
• the feedback loop includes a digital loop filter 410 which is typically implemented using a leaky integrator first order loop filter structure.
• the closed loop bandwidth is set by appropriately setting the gain (K) of the loop filter 410.
• the DC correction D/A converter 232 applies the correction value at the PMA 218 output in a closed loop fashion.
• the "DC Calibration Step 1 Enable” signal is set high to short to ground the input of the PMA. This allows the DC correction algorithm to calibrate out only those offsets due to the elements located at and after the PMA stage 220 (e.g., PMA, IF amplifier 414, IF filter 416, biquads 418, output buffer 420, comparator, and DC correction DAC 232 stages) signaling the multiplexer 412 to couple the input of the PMA 218 to ground.
• the PMA stage 220 e.g., PMA, IF amplifier 414, IF filter 416, biquads 418, output buffer 420, comparator, and DC correction DAC 232 stages
• the shorting to ground at the PMA 412 input is removed by signaling the multiplexer 412 to directly connect the mixer output to the PMA input.
• a second closed loop DC offset correction warmup step is performed to quickly calibrate out those additional offsets located at the PMA input due to LO 215 leakage as well as mixer 216 related static offsets.
• the result of this second closed loop correction step is loaded from the loop filter 410 into the integ_out register 425 at the completion of this second closed loop correction step.
• the load_integ_out signal generated by an external controller unit is used to load the integ_out register 425 when a pulse is present on this signal.
• cal_offset reflects those other offsets located in the baseband signal except for those at the PMA 218 input.
• Gain control is achieved in this PMA 218 by steering current away from virtual ground of the operational amplifier 510 to differential virtual ground in 3dB steps.
• the biggest contributor to DC offset is mismatch in input differential stage of the operational amplifier 510. Since the gain control is achieved through attenuation in front of the amplifier 510, the topology 512, 514 provides nearly constant DC offset over the whole AGC 226 range.
• signal "DCOC" is logic 1
• PMA 218 inputs are AC shorted and a common mode voltage is fed into the input of the PMA 218 to calculate static offset of the lineup over the AGC 226 range.

Landscapes

• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Power Engineering (AREA)
• Circuits Of Receivers In General (AREA)
• Control Of Amplification And Gain Control (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Publications (2)

Family

ID=37070476

Family Applications (1)

Country Status (5)

Families Citing this family (23)

Citations (3)

Family Cites Families (17)

• 2005
  • 2005-04-04 US US11/099,138 patent/US7899431B2/en active Active
• 2006
  • 2006-02-28 KR KR1020077022679A patent/KR101241064B1/ko not_active Expired - Fee Related
  • 2006-02-28 JP JP2008504060A patent/JP2008535377A/ja active Pending
  • 2006-02-28 WO PCT/US2006/007120 patent/WO2006107466A2/en not_active Ceased
  • 2006-02-28 EP EP06736439.8A patent/EP1869855B8/en not_active Not-in-force

Patent Citations (3)

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events