WO2006103563A3 - Method and apparatus for reducing system inactivity during time data float delay and external memory write - Google Patents

Method and apparatus for reducing system inactivity during time data float delay and external memory write Download PDF

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Publication number
WO2006103563A3
WO2006103563A3 PCT/IB2006/000957 IB2006000957W WO2006103563A3 WO 2006103563 A3 WO2006103563 A3 WO 2006103563A3 IB 2006000957 W IB2006000957 W IB 2006000957W WO 2006103563 A3 WO2006103563 A3 WO 2006103563A3
Authority
WO
WIPO (PCT)
Prior art keywords
external
data
bus
time data
external memory
Prior art date
Application number
PCT/IB2006/000957
Other languages
French (fr)
Other versions
WO2006103563A8 (en
WO2006103563A2 (en
Inventor
Eric Matulik
Nicolas Rescanieres
Anne Lafage
Original Assignee
Atmel Corp
Eric Matulik
Nicolas Rescanieres
Anne Lafage
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/128,109 external-priority patent/US7269704B2/en
Application filed by Atmel Corp, Eric Matulik, Nicolas Rescanieres, Anne Lafage filed Critical Atmel Corp
Priority to JP2008503620A priority Critical patent/JP2008535075A/en
Priority to EP06727521A priority patent/EP1866777A4/en
Publication of WO2006103563A2 publication Critical patent/WO2006103563A2/en
Publication of WO2006103563A3 publication Critical patent/WO2006103563A3/en
Publication of WO2006103563A8 publication Critical patent/WO2006103563A8/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)

Abstract

The invention comprises a system for reducing inactive periods in an integrated circuit. The integrated circuit (600) is coupled to an external peripheral by an external data bus (640). The integrated circuit (600) has a processor (605) coupled to an internal data bus (645). An external bus circuit (620) is coupled to the internal (645) and external data busses (640). The bus interface circuit (620) is configured to receive read and write signals for data request data, and then transmits a wait signal until data from the external periphera is available on the internal data bus (645), which indicates the external (640) and internal data busses (645) are unavailable. After the processor (605) receives or transmits the data, the bus interface circuit (620) stops transmitting the wait signal and transmits a busy signal, which indicates the internal data bus (645) is available and the external data bus (640) is unavailable.
PCT/IB2006/000957 2005-03-30 2006-03-24 Method and apparatus for reducing system inactivity during time data float delay and external memory write WO2006103563A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008503620A JP2008535075A (en) 2005-03-30 2006-03-24 Method and apparatus for reducing system inactivity during data float delay time and external memory write
EP06727521A EP1866777A4 (en) 2005-03-30 2006-03-24 Method and apparatus for reducing system inactivity during time data float delay and external memory write

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR0503089 2005-03-30
FR0503089 2005-03-30
US11/128,109 2005-05-11
US11/128,109 US7269704B2 (en) 2005-03-30 2005-05-11 Method and apparatus for reducing system inactivity during time data float delay and external memory write

Publications (3)

Publication Number Publication Date
WO2006103563A2 WO2006103563A2 (en) 2006-10-05
WO2006103563A3 true WO2006103563A3 (en) 2007-04-26
WO2006103563A8 WO2006103563A8 (en) 2009-09-11

Family

ID=37053751

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2006/000957 WO2006103563A2 (en) 2005-03-30 2006-03-24 Method and apparatus for reducing system inactivity during time data float delay and external memory write

Country Status (3)

Country Link
EP (1) EP1866777A4 (en)
KR (1) KR20070122227A (en)
WO (1) WO2006103563A2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5651138A (en) * 1994-08-31 1997-07-22 Motorola, Inc. Data processor with controlled burst memory accesses and method therefor
US5822779A (en) * 1992-12-11 1998-10-13 National Semiconductor Corporation Microprocessor-based data processing apparatus that commences a next overlapping cycle when a ready signal is detected not to be active
US5850541A (en) * 1994-11-21 1998-12-15 Nec Corporation Data processing apparatus having a clock control unit for decreasing power consumption of a central processing unit
US6097218A (en) * 1996-12-20 2000-08-01 Lsi Logic Corporation Method and device for isolating noise sensitive circuitry from switching current noise on semiconductor substrate

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6356987B1 (en) * 1999-03-10 2002-03-12 Atmel Corporation Microprocessing device having programmable wait states

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5822779A (en) * 1992-12-11 1998-10-13 National Semiconductor Corporation Microprocessor-based data processing apparatus that commences a next overlapping cycle when a ready signal is detected not to be active
US5651138A (en) * 1994-08-31 1997-07-22 Motorola, Inc. Data processor with controlled burst memory accesses and method therefor
US5850541A (en) * 1994-11-21 1998-12-15 Nec Corporation Data processing apparatus having a clock control unit for decreasing power consumption of a central processing unit
US6097218A (en) * 1996-12-20 2000-08-01 Lsi Logic Corporation Method and device for isolating noise sensitive circuitry from switching current noise on semiconductor substrate

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1866777A4 *

Also Published As

Publication number Publication date
KR20070122227A (en) 2007-12-28
WO2006103563A8 (en) 2009-09-11
EP1866777A4 (en) 2008-03-26
WO2006103563A2 (en) 2006-10-05
EP1866777A2 (en) 2007-12-19

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