EP1866777A4 - Method and apparatus for reducing system inactivity during time data float delay and external memory write - Google Patents
Method and apparatus for reducing system inactivity during time data float delay and external memory writeInfo
- Publication number
- EP1866777A4 EP1866777A4 EP06727521A EP06727521A EP1866777A4 EP 1866777 A4 EP1866777 A4 EP 1866777A4 EP 06727521 A EP06727521 A EP 06727521A EP 06727521 A EP06727521 A EP 06727521A EP 1866777 A4 EP1866777 A4 EP 1866777A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- time data
- external memory
- during time
- memory write
- reducing system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Human Computer Interaction (AREA)
- Information Transfer Systems (AREA)
- Bus Control (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0503089 | 2005-03-30 | ||
US11/128,109 US7269704B2 (en) | 2005-03-30 | 2005-05-11 | Method and apparatus for reducing system inactivity during time data float delay and external memory write |
PCT/IB2006/000957 WO2006103563A2 (en) | 2005-03-30 | 2006-03-24 | Method and apparatus for reducing system inactivity during time data float delay and external memory write |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1866777A2 EP1866777A2 (en) | 2007-12-19 |
EP1866777A4 true EP1866777A4 (en) | 2008-03-26 |
Family
ID=37053751
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP06727521A Withdrawn EP1866777A4 (en) | 2005-03-30 | 2006-03-24 | Method and apparatus for reducing system inactivity during time data float delay and external memory write |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP1866777A4 (en) |
KR (1) | KR20070122227A (en) |
WO (1) | WO2006103563A2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000054165A1 (en) * | 1999-03-10 | 2000-09-14 | Atmel Corporation | Microprocessing device having programmable wait states |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0601715A1 (en) * | 1992-12-11 | 1994-06-15 | National Semiconductor Corporation | Bus of CPU core optimized for accessing on-chip memory devices |
US5651138A (en) * | 1994-08-31 | 1997-07-22 | Motorola, Inc. | Data processor with controlled burst memory accesses and method therefor |
JPH08147161A (en) * | 1994-11-21 | 1996-06-07 | Nec Corp | Data processor |
US6097218A (en) * | 1996-12-20 | 2000-08-01 | Lsi Logic Corporation | Method and device for isolating noise sensitive circuitry from switching current noise on semiconductor substrate |
-
2006
- 2006-03-24 WO PCT/IB2006/000957 patent/WO2006103563A2/en active Application Filing
- 2006-03-24 KR KR1020077025203A patent/KR20070122227A/en not_active Application Discontinuation
- 2006-03-24 EP EP06727521A patent/EP1866777A4/en not_active Withdrawn
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000054165A1 (en) * | 1999-03-10 | 2000-09-14 | Atmel Corporation | Microprocessing device having programmable wait states |
Also Published As
Publication number | Publication date |
---|---|
WO2006103563A3 (en) | 2007-04-26 |
EP1866777A2 (en) | 2007-12-19 |
WO2006103563A8 (en) | 2009-09-11 |
WO2006103563A2 (en) | 2006-10-05 |
KR20070122227A (en) | 2007-12-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20071012 |
|
AK | Designated contracting states |
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|
A4 | Supplementary search report drawn up and despatched |
Effective date: 20080226 |
|
DAX | Request for extension of the european patent (deleted) | ||
RBV | Designated contracting states (corrected) |
Designated state(s): DE FI FR GB IT |
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REG | Reference to a national code |
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17Q | First examination report despatched |
Effective date: 20080905 |
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GRAP | Despatch of communication of intention to grant a patent |
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GRAS | Grant fee paid |
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STAA | Information on the status of an ep patent application or granted ep patent |
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18W | Application withdrawn |
Effective date: 20091104 |
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