EP1866777A4 - Method and apparatus for reducing system inactivity during time data float delay and external memory write - Google Patents

Method and apparatus for reducing system inactivity during time data float delay and external memory write

Info

Publication number
EP1866777A4
EP1866777A4 EP06727521A EP06727521A EP1866777A4 EP 1866777 A4 EP1866777 A4 EP 1866777A4 EP 06727521 A EP06727521 A EP 06727521A EP 06727521 A EP06727521 A EP 06727521A EP 1866777 A4 EP1866777 A4 EP 1866777A4
Authority
EP
European Patent Office
Prior art keywords
time data
external memory
during time
memory write
reducing system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06727521A
Other languages
German (de)
French (fr)
Other versions
EP1866777A2 (en
Inventor
Eric Matulik
Nicolas Rescanieres
Anne Lafage
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/128,109 external-priority patent/US7269704B2/en
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of EP1866777A2 publication Critical patent/EP1866777A2/en
Publication of EP1866777A4 publication Critical patent/EP1866777A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4027Coupling between buses using bus bridges
    • G06F13/405Coupling between buses using bus bridges where the bridge performs a synchronising function
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
EP06727521A 2005-03-30 2006-03-24 Method and apparatus for reducing system inactivity during time data float delay and external memory write Withdrawn EP1866777A4 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0503089 2005-03-30
US11/128,109 US7269704B2 (en) 2005-03-30 2005-05-11 Method and apparatus for reducing system inactivity during time data float delay and external memory write
PCT/IB2006/000957 WO2006103563A2 (en) 2005-03-30 2006-03-24 Method and apparatus for reducing system inactivity during time data float delay and external memory write

Publications (2)

Publication Number Publication Date
EP1866777A2 EP1866777A2 (en) 2007-12-19
EP1866777A4 true EP1866777A4 (en) 2008-03-26

Family

ID=37053751

Family Applications (1)

Application Number Title Priority Date Filing Date
EP06727521A Withdrawn EP1866777A4 (en) 2005-03-30 2006-03-24 Method and apparatus for reducing system inactivity during time data float delay and external memory write

Country Status (3)

Country Link
EP (1) EP1866777A4 (en)
KR (1) KR20070122227A (en)
WO (1) WO2006103563A2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000054165A1 (en) * 1999-03-10 2000-09-14 Atmel Corporation Microprocessing device having programmable wait states

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0601715A1 (en) * 1992-12-11 1994-06-15 National Semiconductor Corporation Bus of CPU core optimized for accessing on-chip memory devices
US5651138A (en) * 1994-08-31 1997-07-22 Motorola, Inc. Data processor with controlled burst memory accesses and method therefor
JPH08147161A (en) * 1994-11-21 1996-06-07 Nec Corp Data processor
US6097218A (en) * 1996-12-20 2000-08-01 Lsi Logic Corporation Method and device for isolating noise sensitive circuitry from switching current noise on semiconductor substrate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000054165A1 (en) * 1999-03-10 2000-09-14 Atmel Corporation Microprocessing device having programmable wait states

Also Published As

Publication number Publication date
WO2006103563A3 (en) 2007-04-26
EP1866777A2 (en) 2007-12-19
WO2006103563A8 (en) 2009-09-11
WO2006103563A2 (en) 2006-10-05
KR20070122227A (en) 2007-12-28

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