WO2006094162A2 - Method for etching having a controlled distribution of process results - Google Patents
Method for etching having a controlled distribution of process results Download PDFInfo
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- WO2006094162A2 WO2006094162A2 PCT/US2006/007525 US2006007525W WO2006094162A2 WO 2006094162 A2 WO2006094162 A2 WO 2006094162A2 US 2006007525 W US2006007525 W US 2006007525W WO 2006094162 A2 WO2006094162 A2 WO 2006094162A2
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- substrate
- etching
- distribution
- processing chamber
- etch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/20—Positioning, supporting, modifying or maintaining the physical state of objects being observed or treated
- H01J2237/2001—Maintaining constant desired temperature
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/334—Etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
- H01L21/67109—Apparatus for thermal treatment mainly by convection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67248—Temperature monitoring
Definitions
- Embodiments of the present invention generally relate to a method of etching. More specifically, the invention relates to a method for etching having a controlled distribution of process results.
- the former approach reduces the photoresist dimension below what is possible lithographically by lateral etching of the photoresist, while the latter approach relies on etch by-products redeposited on the sidewalls during the hard mask etch to passivate and control the amount of lateral etching relative to vertical etching.
- Sidewall passivation by etch by- products is not limited only to the hard mask etch step, but also occurs during the gate main etch, soft landing, and over etch steps.
- Embodiments of the invention generally provide methods for etching a substrate.
- the method for etching a substrate includes determining a substrate temperature target profile that corresponds to a uniform deposition rate of etch by-products on a substrate, preferentially regulating a temperature of a first portion of a substrate support relative to a second portion of the substrate support to obtain the substrate temperature target profile on the substrate, and etching the substrate on the preferentially regulated substrate support.
- the method includes providing a first process control knob to effect a first process condition, wherein the first process condition is represented by a first distribution of process results; providing a second process control knob to effect a second process condition, wherein the second process condition is represented by a second distribution of process results; setting both of the first and second process control knobs to a predetermined setting to produce a third distribution of process results, wherein the third distribution of process results is different from the first and second distributions of process results; and, etching a substrate disposed on a substrate support in a processing chamber having the first and second process control knobs set to the predetermined setting, wherein the first process control knob selects locations of gas injection into the processing chamber, and the second process control knob selects a temperature profile of the substrate support.
- the method includes providing a substrate in a processing chamber having a selectable distribution of species within the processing chamber and a substrate support with lateral temperature control, wherein a temperature profile induced by the substrate support and a selection of species distribution comprise a control parameter set, etching a first layer of material using a first control parameter set, and etching a second layer of material using a second control parameter set, wherein the first and second control parameter sets are different.
- Figures 1A-B are a schematic of the gate etch process
- Figure 2 is a graph illustrating a relationship between average CD bias, substrate temperature and calculated sticking coefficient
- Figure 3 is a graph illustrating a relationship between process mass fraction and normalized distance
- Figure 4 is a graph illustrating a relationship between etch by-product flux and substrate radius
- Figure 5 is a graph illustrating a relationship between CD bias and substrate radius
- Figure 6 is a schematic diagram of an exemplary semiconductor substrate processing chamber in accordance with one embodiment of the invention.
- Figures 7-9 are a flow diagrams of embodiments of etch processes that may be practiced in the chamber of Figure 6, or other suitable processing chamber;
- Figures 10A-F illustrate one embodiment of a sequence for fabricating a structure that may be etched using the method of Figure 7, Figure 8 and/or the method of Figure 9;
- Figures 11 A-B illustrate one embodiment of a sequence for fabricating a structure that may be etched using the method of Figure 7, Figure
- FIG. 1A-B A schematic of the gate etch process is shown in Figures 1A-B. We have experimentally observed a strong dependence of gate etch CD bias on the substrate temperature, and now disclose this relationship, and demonstrate the dependence of the gate etch by-product sticking coefficient on substrate temperature which has enabled the control of process result distribution across a substrate.
- the rate of this redeposition of etch by-products is expected to follow both the gas phase concentration of by-products and the sticking coefficient of those by-products.
- Sticking coefficients have been used in gas-surface reaction mechanisms to describe the probability of an incident gas phase species 102 adsorbing to a surface (shown as a gate structure 100) and they are typically approximated as the ratio of the number of species that are reactiveiy adsorbed on a surface to the total number of incident species. Analysis of the dependence of the sticking coefficient on surface temperature has been used to describe impurity levels during the epitaxial growth of silicon films and the step coverage deposition behavior of silicon dioxide on substrates.
- P is the partial pressure of the etch by-products
- N A is the Avogadro number
- M is the molecular weight of the adsorbing species
- R is the universal gas constant
- T is the temperature
- E eff is the difference between the energies for desorption and the surface reaction.
- Eq. (1) Two important etch process parameters that can be extracted directly from Eq. (1) are the flux of species to the surface and the substrate temperature. Both of these tunable recipe parameters are likely to have a significant impact on the sticking coefficient of passivating species on the gate sidewalls, and hence, the gate CD bias after etching.
- the obvious complication in using Eq. (1) is the R a a s term, which is not easily determined and has some temperature dependence itself. For this analysis, the R ads term will be used as a fitting parameter and will be further explained later.
- patterned substrates with a poly-silicon gate stack were generated.
- the photomask used to pattern the substrates was designed for the 90 nm technology node.
- Etch experiments were carried out in an Applied Materials Centura ® DPS ® Etch system configured with a DPS Il Silicon Etch chamber.
- the substrates were etched using a four step process (breakthrough, main etch, soft landing, and over etch) using standard gate etch chemistries.
- Pre and post etch CD's were measured on an Applied Materials VeraSEM ® Metrology system, (new naming convention)
- the one sigma error bars on the CD bias averages in Figure 2 are a measure of the within substrate CD bias nonuniformity.
- the degree of nonuniformity is consistent for all three substrate temperatures, with the observed linewidths at the edge regions typically being smaller than those in the center region.
- Measurements of within substrate temperature uniformities have indicated that the substrate temperature range is less than ⁇ 1 0 C for conditions similar to these runs, suggesting that the observed within substrate linewidth nonuniformity in these cases is due to something in addition to the substrate temperature.
- Figure 5 shows three cases: a substrate at uniform temperature, an optimized condition with a dual-zone ESC, and an intentionally mistuned process to demonstrate the ability to control CD bias across the substrate. Whereas smaller gate linewidths at the substrate edge are observed in Figure 5 for the uniform substrate temperature condition, a marked improvement in center to edge CD bias uniformity can be achieved when the temperature of the ESC is divided into two zones, where the outer zone is at a lower temperature than the inner zone.
- the range of CD bias for the ESC at uniform temperature is 15.3 nm
- the range of CD bias for the dual zone ESC is 9.5 nm, an improvement of 37.9%.
- the third case shows the condition of an exaggerated center to edge substrate temperature difference, which results in the CD bias being intentionally tuned toward positive values to demonstrate the ability to control CD bias with substrate temperature.
- the CD bias being intentionally tuned toward positive values to demonstrate the ability to control CD bias with substrate temperature.
- more by-products absorb on the sidewalls and result in an inverse effect where the edge linewidths become larger than those of the substrate center.
- the etch processes described herein may be performed in any suitably adapted plasma etch chamber, for example, a HART etch reactor, a HART TS etch reactor, a Decoupled Plasma Source (DPS), DPS-II, or DPS Plus, or DPS DT etch reactor of a CENTURA ® etch system, all of which are available from Applied Materials, Inc. of Santa Clara, California. Plasma etch chambers from other manufacturers may also be adapted to perform the invention.
- the DPS reactor uses a 13.56 MHz inductive plasma source to generate and sustain a high density plasma and a 13.56 MHz source bias power to bias a substrate.
- the decoupled nature of the plasma and bias sources allows independent control of ion energy and ion density.
- the DPS reactor provides a wide process window over changes in source and bias power, pressure, and etchant gas chemistries and uses an endpoint system to determine an end of the processing.
- FIG. 6 depicts a schematic diagram of an exemplary etch reactor 600 that may illustratively be used to practice the invention.
- the particular embodiment of the etch reactor 600 shown herein is provided for illustrative purposes and should not be used to limit the scope of the invention.
- Etch reactor 600 generally includes a process chamber 610, a gas panel 638 and a controller 640.
- the process chamber 610 includes a conductive body (wall) 630 and a ceiling 620 that enclose a process volume. Process gasses are provided to the process volume of the chamber 610 from the gas panel 638.
- the controller 640 includes a central processing unit (CPU) 644, a memory 642, and support circuits 646.
- the controller 640 is coupled to and controls components of the etch reactor 600, processes performed in the chamber 610, as well as may facilitate an optional data exchange with databases of an integrated circuit fab.
- the ceiling 620 is a substantially flat member.
- Other embodiments of the process chamber 610 may have other types of ceilings, e.g., a dome-shaped ceiling.
- Above the ceiling 620 is disposed an antenna 612 comprising one or more inductive coil elements (two co-axial coil elements are illustratively shown).
- the antenna 612 is coupled to a matching network and radio-frequency (RF) plasma power source 618. Power is applied to the antenna 612 and inductively coupled to a plasma formed in the chamber 100 during processing.
- the chamber 100 may alternatively utilize capacitive plasma coupling using a power source 684, as described further below.
- the gas panel 638 is coupled to one or more nozzles so that the flow through into the chamber may be controlled to control the distribution of species within the chamber.
- the one or more nozzles are configured and/or arranged to effect at least one of the process gas flow location, flow orientation of the process gas or species distribution within the chamber.
- a nozzle 608 having at least two outlet ports 604, 606 is provided coupled to the ceiling 620 of the chamber body 610.
- the outlet ports 604, 606 configured to respectively induce a direct and indirect orientation of gas flow into the chamber.
- the first outlet port 604 may provide a direct gas flow orientation, i.e., produce a gas flow entering the chamber oriented substantially normal to the surface.
- the second outlet port 606 may provide an indirect gas flow orientation, i.e., produce a gas flow entering the chamber oriented substantially parallel to the surface, or in another embodiment, directed at an incidence angle of less than or equal to 60 degrees relative to a plane of the substrate. It is contemplated that one or more of the outlet ports 604, 606 may be disposed in other regions of the chamber and that the outlet ports 604, 606 may be disposed on separate nozzles 608 ⁇ i.e., one port per nozzle).
- a pedestal assembly 616 is disposed in the interior volume 606 of the processing chamber 600 below the nozzle 608.
- the pedestal assembly 616 holds the substrate 614 during processing.
- the pedestal assembly 616 generally includes a plurality of lift pins (not shown) disposed therethrough that are configured to lift the substrate from the pedestal assembly 616 and facilitate exchange of the substrate 614 with a robot (not shown) in a conventional manner.
- the pedestal assembly 616 includes a mounting plate 662, a base 664 and an electrostatic chuck 666.
- the mounting plate 662 is coupled to the bottom 612 of the chamber body 630 and includes passages for routing utilities, such as fluids, power lines and sensor leads, among others, to the base 664 and chuck 666.
- At least one of the electrostatic chuck 666 or base 664 includes at least one optional embedded heater 676, at least one optional embedded isolator 674, and a plurality of conduits fluidly coupled to a fluid source 672 that provides a temperature regulating fluid therethrough.
- one heater 676 is illustratively shown in the electrostatic chuck 666 coupled to a power supply 678 while two conduits 668, 670 separated by one annular isolator 674 are shown in the base 664.
- the conduits 668, 670 and heater 676 may be utilized to control the temperature of the pedestal assembly 616, thereby heating and/or cooling the electrostatic chuck 666, thereby controlling, at least in part, the temperature of a substrate 614 disposed on the electrostatic chuck 666.
- the two separate cooling passages 668, 670 formed in the base 664 define at least two independently controllable temperature zones. It is contemplated that additional cooling passages and/or the layout of the passages may be arranged to define additional temperature control zones.
- the second cooling passage 668 is arranged radially inward of the second cooling passage 670 such that the temperature control zones are concentric. It is contemplated that the passages 668, 670 may radially orientated, or have other geometric configurations.
- the cooling passages 668, 670 may be coupled to a single source 672 of a temperature controlled heat transfer fluid, or may be respectively coupled to a separate heat transfer fluid source.
- the isolator 674 is formed from a material having a different coefficient of thermal conductivity than the material of the adjacent regions of the base 664. In one embodiment, the isolator 674 has a smaller coefficient of thermal conductivity than the base 664. In the embodiment depicted in Figure 6, the base 664 is formed from aluminum or other metallic material. In a further embodiment, the isolator 674 may be formed from a material having an anisotropic (i.e. direction-dependent coefficient of thermal conductivity). The isolator 674 functions to locally change the rate of heat transfer between the pedestal assembly 616 through the base 664 to the conduits 668, 670 relative to the rate of heat transfer though neighboring portions of the base 664 not having an isolator in the heat transfer path. An isolator 674 is laterally disposed between the first and second cooling passages 668, 670 to provide enhanced thermal isolation between the temperature control zones defined through the pedestal assembly 616.
- the isolator 674 is disposed between the conduits 668, 670, thereby hindering lateral heat transfer and promoting lateral temperature control zones across the pedestal assembly 616.
- the temperature profile of the electrostatic chuck 666, and the substrate 614 seated thereon may be controlled.
- the isolator 674 is depicted in Figure 6 shaped as an annular ring, the shape of the isolator 674 may take any number of forms.
- An optional thermally conductive paste or adhesive may be disposed on between the base 664 and the electrostatic chuck 666.
- the conductive paste facilitates heat exchange between the electrostatic chuck 666 and the base 664.
- the adhesive mechanically bonds the electrostatic chuck 666 to base 664.
- the pedestal assembly 616 may include a hardware (e.g., clamps, screws, and the like) adapted for fastening the electrostatic chuck 666 to the base 664.
- the temperature of the electrostatic chuck 666 and the base 664 is monitored using a plurality of sensors.
- a first temperature sensor 690 and a second temperature sensor 692 are shown in a radially spaced orientation such that the first temperature sensor 690 may provide the controller 650 with a metric indicative of the temperature of a center region of the pedestal assembly 616 while the second temperature sensor 692 provide the controller 640 with a metric indicative of the temperature of a perimeter region of the pedestal assembly 616.
- the electrostatic chuck 666 is disposed on the base 664 and is circumscribed by a cover ring 648.
- the electrostatic chuck 666 may be fabricated from aluminum, ceramic or other materials suitable for supporting the substrate 614 during processing. In one embodiment, the electrostatic chuck 666 is ceramic. Alternatively, the electrostatic chuck 666 may be replaced by a vacuum chuck, mechanical chuck, or other suitable substrate support.
- the electrostatic chuck 666 is generally formed from ceramic or similar dielectric material and comprises at least one clamping electrode 680 controlled using a chucking power source 682.
- the electrode 680 may optionally be coupled to one or more RF power sources for maintaining a plasma formed from process and/or other gases within the processing chamber 600.
- the electrode 680 is coupled to an RF power source and matching circuit 684 capable of producing an RF signal suitable for maintaining a plasma formed from the process gases within the chamber.
- the electrostatic chuck 666 may also include a plurality of gas passages (not shown), such as grooves, that are formed in a substrate supporting surface of the chuck and fluidly coupled to a source (also not shown) of a heat transfer (or backside) gas.
- the backside gas e.g., helium (He)
- He helium
- the substrate supporting surface of the electrostatic chuck is provided with a coating resistant to the chemistries and temperatures used during processing the substrates.
- Figures 7-9 are a flow diagrams of embodiments of etch processes 700, 800, 900 that may be practiced in the chamber 100, or other suitable processing chamber. Each process may be utilized to fabricate structures depicted in Figures 10A-F and 11A-B. Although the processes 700, 800, 900 are illustrated for forming a gate structure in Figures 10A-F and a shallow trench isolation (STI) structure in Figures 11A-C, the processes may also be beneficially utilized to etch other structures. The processes 700, 800, 900 may be utilized to control the lateral distribution of etch process results.
- STI shallow trench isolation
- the processes 700, 800, 900 may be utilized to produce a substantially uniform center to edge distribution of etch process results, wherein the process results include at least one of etch depth, CD bias, microloading, sidewall profile, passivation, etch rate, step coverage, feature taper angles and undercutting, among others.
- the process 700 of Figure 7 begins at step 702 by determining a substrate temperature target profile that corresponds to a uniform deposition rate of etch by-products on a substrate.
- a temperature of a first portion of a substrate support is preferentially regulated relative to a second portion of the substrate support to obtain the substrate temperature target profile on the substrate.
- the substrate is etched on the preferentially regulated substrate support.
- the process 800 of Figure 8 begins at step 802 by providing a first process control knob to effect a first process condition, wherein the first process condition is represented by a first distribution of process results.
- a second process control knob to effect a second process condition is provided, wherein the second process condition is represented by a second distribution of process results.
- both of the first and second process control knobs are set to a predetermined setting to produce a third distribution of process results, wherein the third distribution of process results is different from the first and second distributions of process results.
- a substrate disposed on a substrate support in a processing chamber having the first and second process control knobs set to the predetermined setting is etched, wherein the first process control knob selects locations of gas injection into the processing chamber, and the second process control knob selects a temperature profile of the substrate support.
- the process 900 of Figure 900 begins at step 902 by providing a substrate in a processing chamber having a selectable distribution of species within the processing chamber and a substrate support with lateral temperature control, wherein a temperature profile induced by the substrate support and a selection of species distribution comprise a control parameter set.
- a first layer of material is etched using a first control parameter set.
- etching a second layer of material is etched using a second control parameter set, wherein the first and second control parameter sets are different. It is contemplated that the method 900 may be practiced during incremental etching of a single layer, wherein each incremental etch step is treated as a layer etching step.
- the etching methods 700, 800, 900 may be utilized to fabricate a gate structure, as illustrated in the sequence of Figures 10A-F. It is contemplated that the setting and/or adjustment of control knobs, species distribution, process gas flow orientation, process gas injection position and temperature profile of the substrate and/or substrate support may be implemented during the etching of any one of the layers of the films stack 1000 or between etching respective layers.
- a film stack 1000 includes a photoresist layer 1002, a BARC layer 1004, a hardmask layer 1006, a gate electrode layer 1008 and a gate dielectric layer disposed on a substrate 1014.
- the gate dielectric layer may include a high-k layer 1010 and an optional underlying polysilicon layer 1012.
- the substrate 1014 may be any one of semiconductor substrates, silicon substrates, glass substrates and the like.
- the layers that comprise the film stack 1000 may be formed using one or more suitable conventional deposition techniques, such as atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), and the like.
- the film stack 300 may be deposited using the respective processing modules of CENTURA ® , PRODUCER ® , ENDURA ® and other semiconductor substrate processing systems available from Applied Materials, Inc. of Santa Clara, California, among other module manufacturers.
- portions of the BARC layer 1004 are exposed through one or more openings 1016 formed in the patterned photoresist layer 1002.
- the film stack is etched through the openings 1016 to define the gate structure.
- Etching of the film stack 1000 includes first etching the BARC layer 1004.
- the BARC 1004 layer is typically an organic material utilized to facilitate patterning the photoresist layer 1002.
- the flow of process gases into the processing chamber may be split about equally between the first outlet port 604 and the second outlet port 606 to control the distribution of species within the processing chamber.
- etching of the BARC layer 1004 may range from providing 100 percent of the flow from the outlet port 604 to providing 100 percent of the flow from the outlet port 606, including entire range of port 604 to port 606 flow ratios defined therebetween.
- the opening 1016 is utilized to etch the hard mask layer 1006 as shown in Figure 10C.
- the hard mask layer 1006 may be SiO 2 , SiO 3 , SiON or other suitable material. During etching of the hard mask layer 1006, at least about 50 percent of the process gas flow entering the processing chamber may be provided from the outlet port 606. In other embodiments, the hard mask layer etch may utilize substantially equal flow distribution between the outlet ports 604, 606, or a ratio of about 25:75 between the ports 604, 606. In another embodiment, the process gas flow is preferentially provided from the outlet port 606. Once the hard mask layer 1006 has been etched, the gate electrode layer 1008 is etched as shown in Figure 10D.
- the gate electrode layer 1008 may comprise a polysilicon layer or a metal layer disposed on a polysilicon layer.
- the polysilicon layer may be ⁇ -Si or c-Si.
- Suitable metal layers for use in the gate electrode layer 1008 include tungsten (W), tungsten nitride (WN), tungsten suicide (WSi), tungsten polysilicon (W/poly), tungsten alloy, tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), titanium nitride (TiN), alone or combinations thereof.
- Etching of the gate dielectric layer 1008 may be segmented into main, soft landing and over etch steps.
- the main and soft landing steps may flow process gases preferentially through the outlet port 604, while the over etch step provides substantially equal flow between the outlet ports 604, 606.
- the over etch step may preferentially flow process gases through the outlet port 606.
- Process gases suitable for etching the gate electrode layer 1008 generally include at least one of HBr, BCI 3 , HCI, chlorine gas (Cl 2 ), nitrogen trifluoride (NF 3 ), sulfur hexafluoride gas (SF 6 ), and carbon and fluorine containing gas, such as CF 4 , CHF 3 , C 4 F 8 , among others.
- the chamber pressure regulated between about 2mTorr to about 100mTorr.
- RF source power may be applied to maintain a plasma formed from the process gas in the range of about 100 Watts to about 1500 Watts.
- the gate dielectric layer is etched. Suitable examples of gate dielectric layer materials include, but not limited to, an oxide layer, a nitrogen-containing layer, a composite of oxide and nitrogen-containing layer, at least one or more oxide layers sandwiching a nitrogen-containing layer, among others.
- the gate dielectric layer material is a high-k material (high-k materials have dielectric constants greater than 4.0).
- high-k materials include hafnium dioxide (HfO 2 ), zirconium dioxide (ZrO 2 ), hafnium silicon oxide (HfSiO 2 ), zirconium silicon oxide (ZrSiO 2 ), tantalum dioxide (TaO 2 ), aluminum oxide, aluminum doped hafnium dioxide, bismuth strontium titanium (BST), and platinum zirconium titanium (PZT) 1 among others.
- the gate dielectric layer is shown as a high-k layer 1010 and a polysilicon layer 1012.
- the polysilicon layer 1012 may be etched as discussed above.
- the high-k layer 1010 may be etched by exposing the layer 1010 to a plasma comprising carbon monoxide and a halogen containing gas.
- the photoresist layer 1002 may be removed as shown in Figure 1OF, using a stripping process, such as by exposure to an oxygen-containing plasma.
- the etching methods 700, 800, 900 may also be utilized to fabricate a a shallow trench isolation (STI) structure, as illustrated in the sequence of Figures 11A-C.
- STI shallow trench isolation
- control knobs, species distribution, process gas flow orientation, process gas injection position and temperature profile of the substrate and/or substrate support may be implemented during the etching of any one of the layers of the films stack or between etching respective layers.
- the film stack 1100 is provided that includes a photoresist layer 1102, and a polysilicon layer 1104 disposed on a substrate 1106.
- the substrate 1106 may be any one of semiconductor substrates, silicon substrates, glass substrates and the like.
- portions of the polysilicon layer 1104 are exposed through one or more openings 1108 formed in the patterned photoresist layer 1102.
- the film stack is etched through the openings 1108 to define the shallow trench isolation (STI) structure.
- STI shallow trench isolation
- the polysilicon layer 1104 is etched using a halogen-containing gas, such as Cl 2 , BCI 3 , HCI, HBr, CF 4 and the like, as shown in Figure 11 B.
- the etching of the polysilicon layer may be performed cyclically with passivation deposition steps.
- the etching of the polysilicon layer include main etch, soft landing and over etch steps, wherein the methods 700, 800, 900 may be performed at least at any one of the etch steps as discussed above.
- the photoresist layer 1102 may be removed as shown in Figure 11 C, using a stripping process, such as by exposure to an oxygen-containing plasma.
- an etch process has been provided that enables the control of the distribution of process results laterally across the surface of a substrate.
- the inventive process enables complimentary process control attributed to be adjusted to obtain substantially uniform center to edge distribution of etch depth, CD bias, microloading, sidewall profile, passivation, etch rate, step coverage, feature taper angles and undercutting and the like.
Abstract
Description
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN200680006797XA CN101133682B (en) | 2005-03-03 | 2006-03-02 | Method for etching having a controlled distribution of process results |
DE112006000327T DE112006000327T5 (en) | 2005-03-03 | 2006-03-02 | Device for controlling the temperature of a substrate |
JP2007558240A JP2008532324A (en) | 2005-03-03 | 2006-03-02 | Etching method with controlled processing result distribution |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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US65869805P | 2005-03-03 | 2005-03-03 | |
US60/658,698 | 2005-03-03 | ||
US11/246,012 US8075729B2 (en) | 2004-10-07 | 2005-10-07 | Method and apparatus for controlling temperature of a substrate |
US11/246,012 | 2005-10-07 |
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WO2006094162A2 true WO2006094162A2 (en) | 2006-09-08 |
WO2006094162A3 WO2006094162A3 (en) | 2007-10-18 |
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PCT/US2006/007525 WO2006094162A2 (en) | 2005-03-03 | 2006-03-02 | Method for etching having a controlled distribution of process results |
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KR (1) | KR100899244B1 (en) |
DE (1) | DE112006000327T5 (en) |
WO (1) | WO2006094162A2 (en) |
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WO2020167944A1 (en) * | 2019-02-15 | 2020-08-20 | Lam Research Corporation | Trim and deposition profile control with multi-zone heated substrate support for multi-patterning processes |
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US8486726B2 (en) * | 2009-12-02 | 2013-07-16 | Veeco Instruments Inc. | Method for improving performance of a substrate carrier |
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US20030155079A1 (en) * | 1999-11-15 | 2003-08-21 | Andrew D. Bailey | Plasma processing system with dynamic gas distribution control |
US20030230551A1 (en) * | 2002-06-14 | 2003-12-18 | Akira Kagoshima | Etching system and etching method |
US20040061449A1 (en) * | 2002-02-27 | 2004-04-01 | Masatsugu Arai | Plasma processing apparatus |
US20040185670A1 (en) * | 2003-03-17 | 2004-09-23 | Tokyo Electron Limited | Processing system and method for treating a substrate |
US20040195216A1 (en) * | 2001-08-29 | 2004-10-07 | Strang Eric J. | Apparatus and method for plasma processing |
US20040261721A1 (en) * | 2003-06-30 | 2004-12-30 | Steger Robert J. | Substrate support having dynamic temperature control |
-
2006
- 2006-03-02 WO PCT/US2006/007525 patent/WO2006094162A2/en active Application Filing
- 2006-03-02 DE DE112006000327T patent/DE112006000327T5/en not_active Ceased
- 2006-03-02 KR KR1020077021429A patent/KR100899244B1/en not_active IP Right Cessation
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US20030155079A1 (en) * | 1999-11-15 | 2003-08-21 | Andrew D. Bailey | Plasma processing system with dynamic gas distribution control |
US20040195216A1 (en) * | 2001-08-29 | 2004-10-07 | Strang Eric J. | Apparatus and method for plasma processing |
US20040061449A1 (en) * | 2002-02-27 | 2004-04-01 | Masatsugu Arai | Plasma processing apparatus |
US20030230551A1 (en) * | 2002-06-14 | 2003-12-18 | Akira Kagoshima | Etching system and etching method |
US20040185670A1 (en) * | 2003-03-17 | 2004-09-23 | Tokyo Electron Limited | Processing system and method for treating a substrate |
US20040261721A1 (en) * | 2003-06-30 | 2004-12-30 | Steger Robert J. | Substrate support having dynamic temperature control |
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WO2020167944A1 (en) * | 2019-02-15 | 2020-08-20 | Lam Research Corporation | Trim and deposition profile control with multi-zone heated substrate support for multi-patterning processes |
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DE112006000327T5 (en) | 2007-12-27 |
KR20070117602A (en) | 2007-12-12 |
WO2006094162A3 (en) | 2007-10-18 |
KR100899244B1 (en) | 2009-05-27 |
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