KR20070117602A - Method for etching having a controlled distribution of process results - Google Patents

Abstract

Embodiments of the invention generally provide methods for etching a substrate. In one embodiment, the method includes determining a substrate temperature target profile that corresponds to a uniform deposition rate of etch by-products on a substrate, preferentially regulating a temperature of a first portion of a substrate support relative to a second portion of the substrate support to obtain the substrate temperature target profile on the substrate, and etching the substrate on the preferentially regulated substrate support. In another embodiment, the method includes providing a substrate in a processing chamber having a selectable distribution of species within the processing chamber and a substrate support with lateral temperature control, wherein a temperature profile induced by the substrate support and a selection of species distribution comprise a control parameter set, etching a first layer of material and etching a second layer of material respectively different control parameter sets.

Description

METHOD FOR ETCHING HAVING A CONTROLLED DISTRIBUTION OF PROCESS RESULTS

Embodiments of the present invention generally relate to etching methods. More specifically, the present invention relates to a method for etching with a controlled distribution of process results.

In the manufacture of integrated circuits, precise control of various process parameters is required to achieve consistent results within the substrate, as well as results reproducible from substrate to substrate. During the process, changes in temperature and temperature gradients for the substrate can be fatal to material deposition, etch rate, step coverage, feature taper angles, and other parameters of the semiconductor devices. Thus, creating a temperature distribution of a predetermined pattern for the substrate is one of the important requirements for achieving high yields.

The 2003 edition of the International Technology Roadmap for Semiconductors describes that reducing the transistor gate critical dimension (CD) is an important challenge for future etching technologies. Thus, because gate CD contributes greatly to the device's ultimate performance, much work has been done to study the gate etch process parameters that affect the performance of controlling CD. Several different strategies for gate CD control have been disclosed, which include photoresist trimming and control of gate hard mask etch chemistries. The former method reduces the photoresist dimension below that lithographically possible by side etching of the photoresist, while the latter method during hard mask etching to passivate and control the amount of side etching compared to the vertical etching. The etch byproducts redeposited on the sidewalls. Sidewall passivation by etch byproducts is not limited to the hard mask etch step, but also occurs during the gate main etch, soft landing, and over etch steps.

The redeposition rate of etch byproducts is expected to follow the gas phase concentration of the byproducts and the sticking coefficient of those byproducts. The adhesion coefficients were used in gas-surface reaction mechanisms describing the probability of incident gas phase species absorbed on the surface, and the ratio of the number of species absorbed on the surface to the total number of incident species As is usually approximated.

However, conventional substrate pedestals have insufficient means for controlling the substrate temperature distribution over the diameter of the substrate. The inability to control substrate temperature uniformity adversely affects process uniformity, device yield, and overall quality of processed substrates within and between single substrates.

Thus, there is a need for a technique of an improved method for etching a substrate.

Embodiments of the present invention generally provide methods for etching a substrate. In one embodiment, a method for etching a substrate includes determining a substrate temperature target profile corresponding to a uniform deposition rate of etch byproducts on the substrate; Regulating the temperature of the first portion of the substrate support relative to the second portion of the substrate support to obtain a substrate temperature target profile on the substrate; And etching the substrate on the preferentially adjusted substrate support.

In another embodiment, the method includes providing a first process control knob that affects a first process condition, wherein the first process condition is represented by a first distribution of process results; Providing a second process control knob that affects a second process condition, wherein the second process condition is represented by a second distribution of process results; Setting the first and second process control knobs to a predetermined setting to form a third distribution of process results, wherein the third distribution of the process results is dependent upon the first and second distributions of the process results. Different; And etching a substrate disposed on a substrate support in a processing chamber having the first and second process control knobs set to the predetermined setting, the first process control knob adjusting positions of gas injection into the processing chamber. The second process control knob selects a temperature profile of the substrate support.

In another embodiment, the method includes providing a substrate in the processing chamber having a selectable distribution of species in the processing chamber, and a substrate support having side temperature control—temperature profile and species distribution induced by the substrate support The selection of includes a control parameter set; Etching the first layer of material using the first set of control parameters; And etching the second layer of material using the second set of control parameters, wherein the first and second set of control parameters are different.

In a way that the foregoing features of the invention can be understood in detail, a more specific description of the invention can be made with reference to the embodiments, briefly summarized above, some of which are illustrated in the accompanying drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may be applicable to other equally effective embodiments.

1A-1B are conceptual diagrams of a gate etch process.

2 is a graph showing the relationship between average CD deviation, substrate temperature and calculated adhesion coefficients.

3 is a graph showing the relationship between process mass rate and normalized distance.

4 is a graph showing the relationship between etch byproduct flux and substrate radius.

5 is a graph showing the relationship between CD deviation and substrate radius.

6 is a conceptual diagram of an exemplary semiconductor substrate processing chamber in accordance with an embodiment of the present invention.

7-9 are flow diagrams of embodiments of etching processes that may be performed in the chamber of FIG. 6, or other suitable processing chamber.

10A-10F illustrate one embodiment of a sequence for making a structure that can be etched using the method of FIGS. 7, 8, and / or 9.

11A-11B illustrate one embodiment of a sequence for making a structure that can be etched using the method of FIGS. 7, 8, and / or 9.

For ease of understanding, the same reference numerals have been used where possible to refer to the same elements that are common to the figures. In addition, it is contemplated that elements and features of one embodiment may be preferably included in other embodiments without further citation.

A conceptual diagram of the gate etching process is shown in FIGS. 1A-1B. Applicant has experimentally observed the strong dependence of gate etch CD bias on substrate temperature, and now discloses the relationship, and the gate etch byproduct adhesion coefficient to substrate temperature that enables control of the process result distribution on the substrate. Prove your dependencies.

The redeposition rate of etch byproducts is expected to follow the gas phase of the byproducts and the coefficient of adhesion of those byproducts. Attachment coefficients have been used in gas-surface reaction mechanisms that describe the probability of incident gas phase species 102 absorbed on a surface (shown as gate structure 100), typically on the surface for the total number of incident species. It is approximated as the ratio of the number of species absorbed reactively. Analysis of the dependence of the adhesion coefficient on the surface temperature was used to describe the impurity levels during the epitaxial growth of the silicon films, and the step coverage deposition characteristics of silicon dioxide on the substrates. Both models relate the adhesion coefficient to the competition between absorption, desorption, and reaction rates for gas phase species on the surface. Thus, negative values of the adhesion coefficient can be interpreted as etch yields. Using Bennet's equation combined with the Langmuir absorption theory, the temperature dependence of s * can be expressed as:

(1)

(One)

Where P is the partial pressure of the etch byproducts, N _A is the avogadro number, M is the molecular weight of the absorbing species, R is the universal gas constant, T is the temperature, and E _eff is the energy between absorption and surface reactions. It is the difference. Etch byproducts assume that the etch byproducts are redeposited equally on any surface point regardless of previous history, so that surface coverage can be ignored. This assumption is valid because the observed thicknesses of passivating layers during the gate etch are typically larger than the thickness of a single monolayer.

Two important etching process parameters that can be extracted directly from equation (1) are the flux of the species to the surface and the surface temperature. These adjustable recipe parameters will greatly affect the adhesion coefficient of the passivating species on the gate sidewalls and thus the gate CD deviation after etching. The apparent complexity in using equation (1) is the R _ads term, which is not readily determined and has some temperature dependency on its own. For this analysis, the R _ads term is used as a fitting parameter and is further described later.

To test the influence of the longitudinal flux and substrate temperature on the gate etch process, patterned substrates with poly-silicon gate stacks are formed. The photomask used to pattern the substrates is designed for a 90 nm technology node. Etching experiments are performed with an Applied Materials Centura® DPS® Etch system consisting of a DPS II silicon etch chamber. The substrates are etched using a four step process (breakthrough, main etch, soft landing, and over etch) using standard gate etch chemistries. Pre and post etch CDs are measured on the VeraSEM® Metrology system from Applied Materials. (New naming convention)

The effect of substrate temperature on the mean CD deviation, where the CD deviation is defined as post etch CD-pre etch CD, can be clearly understood in FIG. 2. The data results in an average gate line width in which the increasing substrate temperature is narrower, which is consistent with the theory that there are fewer passivating species on the gate sidewall at higher temperatures. The best fit curve for the adhesion coefficient shown in FIG. 2 closely follows the mean CD deviation data, calculated using Equation (1), E _eff is assumed to be 0.250 eV, and R _ads = 9E13 atoms / cm ² s . To ensure that the value of the fitting parameter R _ads is valid, an independent calculation of R _ads can be made using the CD deviation data as shown in equation (2):

(2)

(2)

In fact, the average value for R _ads obtained by equation (2) is in good agreement with the value obtained through the fitting procedure for the temperature range under consideration. The relationship between the mean CD deviation and substrate temperature of these three runs represents an average rate of change of -0.8607 nm / ° C. The corresponding percentage change in adhesion coefficient s * is -0.2% / ° C. The calculated range of adhesion coefficients shown in FIG. 2 is also consistent with the values obtained for the CF ₂ radicals incident on the powered Si electrode.

One sigma error bar on the CD deviation means of FIG. 2 is a measure of the internal substrate CD deviation nonuniformity. The degree of nonuniformity is consistent with the line widths observed in the edge regions, which are typically smaller than those of the central region, for all three substrate temperatures. Measurements of internal substrate temperature nonuniformities indicate that the substrate temperature range is less than ± 1 ° C. for conditions similar to these implementations, and that the internal substrate linewidth nonuniformity observed in these cases is due to something along with the substrate temperature. Suggest.

Previous work has demonstrated that a reduction in CD bias at the substrate edge can be caused by a decrease in byproduct concentration in this region of the substrate. This concentration gradient is formed by more efficient removal of etch byproducts at the substrate edge compared to the substrate center. As a result, the local absorptivity at the substrate edge is reduced directly adjacent to the absorption point, i.e., the gate sidewall, for a given substrate temperature. This local partial pressure of the passivating species can be controlled in part by the location of the feed gas injection into the chamber. 3 shows simulation results comparing three different gas injection means. If gas is injected into the top of the chamber in a direction perpendicular to the substrate surface (labeled central gas supply in FIG. 3), the density of the precursor species actually decreases at the center due to an increase in gas velocity as a result of increased convective flow. do. In contrast, when gas is injected into the top of the chamber in a direction parallel to the substrate surface (labeled side gas supply in FIG. 3), the flow to the substrate surface is more diffuse and a more uniform distribution of precursor species is achieved. .

Using the relationship between substrate temperature and adhesion coefficient as well as the recognition of the etch byproduct distribution in the etch chamber, the internal substrate CD deviation uniformity can be optimized by introducing multiple temperature regions into the electrostatic chuck (ESC). The corresponding radical requirements for the radical distribution and adhesion coefficient of the etch byproducts for a typical gate etch process are shown in FIG. 4. Since the change in adhesion coefficient with temperature is approximately linear for small temperature changes, the predicted temperature profile is very similar to the local gas phase species concentration. Thus, the desired substrate temperature is required to be lower relative to the edge region of the substrate to compensate for the reduction of passivating species induced by pumping. As a result, this local substrate surface temperature decrease increases the adhesion coefficient of the paving species to maintain a constant and uniform flux of absorbing species to the substrate surface and thus maintain uniform gate line widths.

5 shows three cases: a substrate of uniform temperature, an optimization condition with dual-region ESC, and a deliberately mistuned process to demonstrate the ability to control CD deviation for the substrate. While smaller gate line widths at the substrate edge are observed in FIG. 5 for uniform substrate temperature conditions, a significant improvement in the center for edge CD deviation uniformity can be achieved when the temperature of the ESC is divided into two regions. Wherein the outer region is at a lower temperature than the inner region. At uniform temperatures the CD bias for ESC ranges from 15.3 nm, the CD deviation for dual region ESC ranges from 9.5 nm, an improvement of 37.9%. The third case represents an exaggerated center condition for the edge substrate temperature difference and generates a CD deviation that is intentionally adjusted towards positive values to demonstrate the ability to control the CD bias through the substrate temperature. Let's do it. At the lowest substrate temperatures, more byproducts are absorbed in the sidewalls and adversely affect, and the edge line widths are larger than those at the substrate center.

In summary, the uniform absorption theory has been shown to be used to help explain the observed trend of CD deviation uniformity during the transistor gate etching process. In particular, the temperature dependence of the adhesion coefficient of the etch byproducts is important. Thus, as found in DPS II Silicon Etch chambers, ESCs with multiple independently controllable temperature regions are most desirable for critical etching applications such as gate etching. Similar phenomena appear to occur during other etching applications where sidewall passivation is critical for CD performance, such as etching aluminum lines, or dielectric etching of contacts and vias.

Etching processes described herein are all available from, for example, HART etch reactor, HART TS etch reactor, Decoupled Plasma Source (DPS), DPS-II, or DPS Plus, all available from Applied Materials, Inc. Or a DPS DT etch reactor in a CENTURA® etch system. Plasma etch chambers from other manufacturers may be applied to carry out the present invention. The DPS reactor uses 13.56 MHz source bias power to bias the 13.56 MHz flowable plasma source and substrate to create and maintain high density plasma. The decoupling properties of the plasma and bias sources allow independent control of ion energy and ion density. The DPS reactor provides a wide process window for changes in source and bias power, pressure, and etchant gas chemistries, and uses an endpoint system to determine the end of the process.

6 shows a conceptual diagram of an exemplary etch reactor 600 that may be used illustratively to practice the present invention. Certain embodiments of the etch reactor 600 are provided for illustrative purposes only and should not be used to limit the scope of the invention.

Etch reactor 600 generally includes a processing chamber 610, a gas panel 638, and a controller 640. The processing chamber 610 includes a sealing 620 and a conductive body (wall) 630 surrounding the processing volume. Process gases are provided from the gas panel 638 to the processing volume of the chamber 610.

The controller 640 includes a central processing unit (CPU) 644, a memory 642, and support circuits 646. The controller 640 is coupled to the components of the etch reactor 600, controls the components of the etch reactor 600 and the processes performed in the chamber 610, and optionally exchanges data with databases of integrated circuit taps. Can be facilitated.

In the illustrated embodiment, the seal 620 is a substantially planar member. Other embodiments of the processing chamber 610 may have other types of seals, such as dome-shaped seals, for example. The seal 620 described above is disposed in an antenna 612 that includes one or more inductive coil elements (two coaxial coil elements are shown by way of example). Antenna 612 is coupled to a matching network and a radio frequency (RF) plasma power source 618. Power is applied to the antenna 612 and inductively coupled to the plasma formed in the chamber 100 during processing. Chamber 100 may optionally utilize capacitive plasma coupling using power source 684, as further described below.

Gas panel 638 is coupled to one or more nozzles such that flow through the chamber can be controlled to control the distribution of species in the chamber. One or more nozzles are configured and / or arranged to affect at least one of the process gas flow location, the flow orientation of the process gas, or the species distribution in the chamber.

In one embodiment, a nozzle 608 having at least two outlet ports 604, 606 is provided coupled to the sealing 620 of the chamber body 610. The outlet ports 604, 606 are configured to direct the direct and indirect orientations of the gas flow into the chamber, respectively. For example, the first outlet port 604 can provide a direct gas flow orientation, that is, form a gas flow entering a chamber that is oriented substantially perpendicular to the surface. The second outlet port 606 may provide an indirect gas flow orientation, ie, form a gas flow entering the chamber that is oriented substantially parallel to the surface, or in another embodiment, relative to the plane of the substrate It can be derived at an angle of incidence equal to or less than 60 °. One or more outlet ports 604, 606 may be disposed in other regions of the chamber, and outlet ports 604, 606 may be disposed in separate nozzles 608 (ie, one port per nozzle). ).

The pedestal assembly 616 is disposed in the interior volume 606 of the processing chamber 600 under the nozzle 608. Pedestal assembly 616 holds substrate 614 during processing. The pedestal assembly 616 generally includes a plurality of through-placed lift pins (not shown) configured to lift the substrate from the pedestal assembly 616, and in a conventional manner the substrate through a robot (not shown). 614 facilitates replacement.

In one embodiment, pedestal assembly 616 includes mounting plate 662, base 664, and electrostatic chuck 666. Mounting plate 662 is coupled to bottom 612 of chamber body 630 and, among other things, base 664 and electrostatic chuck 666 for routing utilities such as fluids, power lines, and sensor leads. Paths).

At least one of the electrostatic chuck 666 or the base 664 is at least one optional embedded heater 676, at least one optional embedded insulator 674, and a fluid source 672 that provides a penetrating temperature regulating fluid. It includes a plurality of conduits fluidly coupled to. In the embodiment shown in FIG. 6, one heater 676 is illustratively shown in an electrostatic chuck 666 coupled to a power source 678 and two conduits separated by one annular insulator 674. 668 and 670 are shown in base 664. Conduits 668, 670 and heater 676 can be used to control the temperature of pedestal assembly 616, thereby controlling the heating and / or cooling of electrostatic chuck 666, thereby It may be used to at least partially control the temperature of the substrate 614 disposed at 666.

Two separate cooling passages 668, 670 formed in the base 664 define at least two independently controllable temperature regions. It is contemplated that additional cooling passages and / or layout of the passages may be arranged to define additional temperature control regions. In one embodiment, the second cooling passage 668 is disposed inwardly in the radius of the second cooling passage 670 such that the temperature control regions are concentric. The passages 668, 670 may be radially oriented or may have other geometric configurations. Cooling passages 668 and 670 may be coupled to a single source 672 of temperature controlled heat transfer fluid or may be coupled to a separate heat transfer fluid source, respectively.

Insulator 674 is formed from a material having a different thermal conductivity coefficient from that of adjacent regions of base 664. In one embodiment, insulator 674 has a smaller thermal conductivity coefficient than base 664. In the embodiment shown in FIG. 6, base 664 is formed from aluminum or other metallic material. In further embodiments, insulator 674 may be formed from a material having anisotropy (ie, direction-dependent thermal conductivity coefficient). The insulator 674 is between the pedestal assembly 616 through the base 664 to the conduits 668, 670 as compared to the heat transfer rate through the adjacent portions of the base 664 having no insulator in the heat transfer path. Acts to locally change the heat transfer rate. Insulator 674 is laterally disposed between the first and second cooling passages 668, 670 to provide improved thermal insulation between defined temperature control regions through pedestal assembly 616.

In the embodiment shown in FIG. 6, an insulator 674 is disposed between the conduits 668, 670, thus preventing lateral heat transfer and promoting lateral temperature control regions relative to the pedestal assembly 616. Let's do it. Thus, by controlling the number, shape, size, location and heat transfer coefficient of the inserts, the temperature profile of the electrostatic chuck 666 and the substrate 614 seated thereon can be controlled. Although the insulator 674 is shown in FIG. 6 shaped as an annular ring, the shape of the insulator 674 can take any number of forms.

An optional thermally conductive paste or adhesive (not shown) may be disposed between the base 664 and the electrostatic chuck 666. The conductive paste promotes heat exchange between the electrostatic chuck 666 and the base 664. In one exemplary embodiment, the adhesive mechanically couples the electrostatic chuck 666 to the base 664. Optionally (not shown), pedestal assembly 616 may include hardware (eg, clamps, screws, etc.) configured to couple electrostatic chuck 666 to base 664.

The temperature of the electrostatic chuck 666 and base 664 is monitored using a number of sensors. In the embodiment shown in FIG. 6, the first temperature sensor 690 can provide the controller 650 with an indicator indicating the temperature of the central region of the pedestal assembly 616, and the second temperature sensor 692. The first temperature sensor 690 and the second temperature sensor 692 are in a radially spaced orientation so that the controller 650 can provide an indicator indicating the temperature of the peripheral region of the pedestal assembly 616. Shown.

The electrostatic chuck 666 is disposed on the base 664 and surrounded by the cover ring 648. The electrostatic chuck 666 may be made of aluminum, ceramic, or other materials suitable for supporting the substrate 614 during processing. In one embodiment, the electrostatic chuck 666 is ceramic. Optionally, the electrostatic chuck 666 can be replaced with a vacuum chuck, mechanical chuck, or other suitable substrate support.

The electrostatic chuck 666 is generally formed from a ceramic or similar dielectric material and includes at least one clamping electrode 680 controlled using a chucking power source 682. Electrode 680 (or other electrode disposed in chuck 666 or base 664) is selectively coupled to one or more RF power sources for maintaining plasma formed from the process and / or other gases in processing chamber 600. Can be. In the embodiment shown in FIG. 6, electrode 680 is coupled to an RF power source and matching circuit 684 that can generate a suitable RF signal to maintain a plasma formed from the process gases in the chamber.

The electrostatic chuck 666 may include a plurality of gas passages (not shown), such as grooves formed on a substrate support surface of the electrostatic chuck and fluidly coupled to a source of heat transfer (or back) gas (not shown). . In operation, backside gas (eg, helium He) is provided at a controlled pressure into the gas passages to enhance heat transfer between the electrostatic chuck 666 and the substrate 614. Typically, at least the substrate support surface of the electrostatic chuck is provided with a coating that is resistant to the temperatures and chemicals used during processing of the substrates.

7-9 are flow diagrams of embodiments of etching processes 700, 800, 900 that may be performed in chamber 100, or other suitable processing chamber. Each process can be used to fabricate the structures shown in FIGS. 10A-10F and 11A-11B. Processes 700, 800, 900 are shown to form the gate structure of FIGS. 10A-10F and the shallow trench insulator (STI) of FIGS. 11A-11C, although the processes may be preferably used to etch other structures. Processes 700, 800, 900 can be used to control the lateral distribution of the etching process results. For example, processes 700, 800, 900 can be used to form a substantially uniform center for the edge distribution of the etch process results, where the process results are, among others, etch depth, CD deviation, microloading. At least one of sidewall profile, passivation, etch rate, step coverage, feature taper angles, and undercutting.

The process 700 of FIG. 7 begins at step 702 by determining a substrate temperature target profile corresponding to a uniform deposition rate of etch byproducts on the substrate. In step 704, the temperature of the first portion of the substrate support is preferentially adjusted relative to the second portion of the substrate support to obtain a substrate temperature target profile on the substrate. In step 706, the substrate is preferentially etched onto the adjusted substrate support.

Process 800 of FIG. 8 begins at step 802 by providing a first process control knob to affect the first process condition, where the first process condition is represented by a first distribution of process results. In step 804, a second process control knob is provided that affects the second process condition, where the second process condition is represented by a second distribution of process results. In step 806, both the first and second process control knobs are set to predetermined settings to form a third distribution of process results, where the third distribution of process results is the first and second distribution of process results. Is different from In step 808, the substrate disposed in the substrate support in the processing chamber having the first and second process control knobs set to predetermined settings is etched, where the first process control knob is adapted to position the positions of gas injection into the processing chamber. The second process control knob selects a temperature profile of the substrate support.

The process 900 of FIG. 9 begins at step 902 by providing a substrate to a processing chamber having a selectable distribution of species in the substrate support and processing chamber through side temperature control, where selection of the substrate support and species distribution is performed. The temperature profile derived by means of the control parameter set. In step 904, the first layer of material is etched using the first set of control parameters. In step 906, the second material layer to be etched is etched using the second set of control parameters, where the first and second set of control parameters are different. It is contemplated that the method 900 may be performed during a single layer incremental etch, where each incremental etch step is treated as a layer etch step.

Etching methods 700, 800, 900 may be used to fabricate the gate structure, as shown in the sequence of FIGS. 10A-10F. Setting and / or adjusting the control knobs, the species distribution, the process gas flow orientation, the process gas injection position, and the temperature profile of the substrate and / or substrate support during etching of any one of the layers of the film stack 1000, Or may be practiced between etching the respective layers.

Referring to FIG. 10A, a film stack including a photoresist layer 1002, a BARC layer 1004, a hardmask layer 1006, a gate electrode layer 1008, and a gate dielectric layer disposed on a substrate 1014 ( 1000). The gate dielectric layer may include a high-k layer 1010 and an optional lower polysilicon layer 1012. Substrate 1014 may be any one of semiconductor substrates, silicon substrates, glass substrates, and the like. The layers comprising the film stack 1000 utilize one or more suitable conventional deposition techniques, such as atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), and the like. Can be formed. The film stack 300 is deposited using different semiconductor substrate processing systems and respective processing modules from CENTURA®, PRODUCER®, ENDURA® available from Applied Materials, Inc. of Santa Clara, California, among other module manufacturers. Can be. In the embodiment shown in FIG. 10A, portions of BARC layer 1004 are exposed through one or more openings 1016 formed in patterned photoresist layer 1002. The film stack is etched through the openings 1016 to define the gate structure.

Etching the film stack 1000 includes first etching the BARC layer 1004. BARC layer 1004 is typically an organic material used to facilitate the patterning of photoresist layer 1002. During etching of the BARC layer 1004, the flow of process gases into the process chamber is approximately equal between the first outlet port 604 and the second outlet port 606 to control the distribution of species in the process chamber. Can be divided. In other embodiments, etching of the BARC layer 1004 provides 100% flow from the outlet port 604 while covering the entire range of flow rates defined therebetween from the port 604 to the port 606. To a range of 100% flow from the outlet port 606. After BARC layer 1004 is etched as shown in FIG. 10B, opening 1016 is used to etch hard mask layer 1006 as shown in FIG. 10C.

Hard mask layer 1006 may be SiO ₂ , SiO ₃ , SiON or other suitable material. During the etching of the hard mask layer 1006, at least about 50% of the process gas flow entering the process chamber may be provided from the outlet port 606. In other embodiments, the hard mask layer etch may use substantially the same flow distribution between the outlet ports 604, 606, or may use a ratio of about 25:75 between the outlet ports 604, 606. have. In another embodiment, process gas flow is provided preferentially from outlet port 606. When the hard mask layer 1006 is etched, the gate electrode layer 1008 is etched as shown in FIG. 10D.

The gate electrode layer 1008 may include a metal layer or a polysilicon layer disposed on the polysilicon layer. The polysilicon layer may be α-Si or c-Si. Suitable metal layers for use in the gate electrode layer 1008 include tungsten (W), tungsten nitride (WN), tungsten silicide (WSi), tungsten polysilicon (W / poly), tungsten alloy, tantalum (Ta), tantalum nitride (TaN) ), Tantalum silicon nitride (TaSiN), titanium nitride (TiN), each of these or combinations thereof.

The etching of the gate dielectric layer 1008 can be divided into main, soft landing and over etching steps. Each of these steps may have one or more processing parameters set differently in accordance with the present invention. For example, the main and soft landing steps may preferentially flow process gases through the outlet port 604, and the over etch step provides substantially the same flow between the outlet ports 604, 606. In other embodiments, the over etching step may preferentially flow process gases through the outlet port 606. Process gases suitable for etching the gate electrode layer 1008 include, among others, HBr, BCl ₃ , HCl, chlorine gas (Cl ₂ ), nitrogen trifluoride (NF ₃ ), sulfur hexafluoride gas (SF ₆ ), And carbon and fluorine containing gases such as CF ₄ , CHF ₃ , C ₄ F ₈ .

Several processing parameters are adjusted during the etch. In one embodiment, the chamber pressure is adjusted from about 2 mTorr to about 100 mTorr. The RF power source may be applied to maintain a plasma formed from the processing gas in the range of about 100 Watts to about 1500 Watts.

After etching to the gate electrode layer 1008, the gate dielectric layer is etched. Suitable examples of gate dielectric layers include, but are not limited to, oxide layers, nitrogen-containing layers, complexes of oxide and nitrogen-containing layers, at least one or more oxide layers embedded in nitrogen-containing layers, among others. In one embodiment, the gate dielectric layer material is a high-k material (high-k materials have dielectric constants greater than 4.0). Examples of high-k materials are hafnium dioxide (HfO ₂ ), zirconium dioxide (ZrO ₂ ), hafnium silicon oxide (HfSiO ₂ ), zirconium silicon oxide (ZrSiO ₂ ), tantalum dioxide (TaO ₂ ), aluminum oxide, among others. Aluminum doped hafnium dioxide, bismuth strontium titanium (BST), and platinum zirconium titanium (PZT).

In the embodiment shown in FIGS. 10A-10E, the gate dielectric layer is shown as a high-k layer 1010 and a polysilicon layer 1012. Polysilicon layer 1012 may be etched as described above. The high-k layer 1010 may be etched by exposing the layer 1010 to a plasma comprising carbon monooxide and a halogen containing gas. After etching the gate dielectric layer, the photoresist layer 1002 may be removed as shown in FIG. 10F using a stripping process, such as, for example, exposure to an oxygen-containing plasma.

Etching methods 700, 800, 900 may be used to fabricate a shallow trench isolation (STI) structure, as shown in the sequence of FIGS. 11A-11C. Control knobs, species distribution, process gas flow orientation, process gas injection location and temperature profile of the substrate and / or substrate support may be performed between the etching of any one of the layers of the film stack or the etching of the respective layers. Consider.

Referring first to FIG. 11A, a film stack 1100 is provided that includes a photoresist layer 1102 and a polysilicon layer 1104 disposed on a substrate 1106. Substrate 1106 may be any one of semiconductor substrates, silicon substrates, glass substrates, and the like. In the embodiment shown in FIG. 11A, portions of the polysilicon layer 1104 are exposed through one or more openings 1108 formed in the patterned photoresist layer 1102. The film stack is etched through the openings 1108 to define a shallow trench isolation (STI) structure.

The polysilicon layer 1104 is etched using a halogen-containing gas, such as Cl ₂ , BCl ₃ , HCl, HBr, CF _4, and the like, as shown in FIG. 11B. Etching of the polysilicon layer may be performed periodically in passivation deposition steps. Etching the polysilicon layer includes main etching, soft landing and over etching steps, wherein the methods 700, 800, 900 may be performed in at least any one of the etching steps as described above. After etching the polysilicon layer 1104, the photoresist layer 1102 may be removed, as shown in FIG. 11C, using a stripping process, such as exposure to an oxygen-containing plasma.

Thus, an etching process has been provided that allows for control of the distribution of process results laterally to the surface of the substrate. Preferably, the process of the present invention is adapted to achieve a substantially uniform center of edge distribution such as etch depth, CD deviation, microloading, sidewall profile, passivation, etch rate, step coverage, feature taper angles and undercutting, etc. Enable complementary process control that contributes to being adjusted.

While the foregoing detailed description is directed to embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, the scope of which is determined by the claims that follow. .

Claims (33)

As a method for etching a substrate, Determining a substrate temperature target profile corresponding to a uniform deposition rate of etch byproducts on the substrate; Prioritizing the temperature of the first portion of the substrate support relative to the second portion of the substrate support to obtain a substrate temperature target profile on the substrate; And Etching the substrate on the preferentially adjusted substrate support Substrate etching method comprising a. The method of claim 1, Determining the substrate temperature target profile, Determining a distribution of etch byproducts on the surface of the substrate; And Correlating the distribution to the substrate temperature target profile. The method of claim 2, Determining the distribution of etch byproducts further comprises determining a sticking coefficient for the surface of the substrate. The method of claim 2, Determining the distribution of etch byproducts further comprises determining a flux of species to the surface of the substrate. The method of claim 1, Determining the substrate temperature target profile, Modeling a relationship between deposition of etch byproducts and substrate temperature; And Generating the substrate temperature target profile from the modeling. The method of claim 1, Determining the substrate temperature target profile further comprises using experimental data to generate the substrate temperature target profile. As a method for etching a substrate, Providing a first process control knob to affect a first process condition, wherein the first process condition is represented by a first distribution of process results; Providing a second process control knob to affect a second process condition, said second process condition represented by a second distribution of process results; Setting the first and second process control knobs to predetermined settings to form a third distribution of process results, wherein the third distribution of the process results is different from the first and second distributions of the process results; And Etching a substrate disposed on a substrate support of a processing chamber having first and second process control knobs set to the predetermined setting, the first process control knob selecting positions of gas injection into the processing chamber and The second process control knob selects a temperature profile of the substrate support; Substrate etching method comprising a. The method of claim 7, wherein Setting the first process control knob further comprises selecting a ratio of a direct gas injection orientation to an indirect gas injection orientation. The method of claim 7, wherein The step of setting the first process control knob further comprises the step of significantly flowing gas into the processing chamber in an orientation substantially perpendicular to the plane of the substrate. The method of claim 7, wherein Setting the first process control knob further comprises flowing gas significantly into the processing chamber in an orientation substantially parallel to the plane of the substrate. The method of claim 7, wherein Setting the first process control knob comprises controlling a local partial pressure of a passivation species in the processing chamber. The method of claim 7, wherein Setting the first process control knob further comprises flowing gas into the processing chamber in direct and indirect gas injection orientations. The method of claim 7, wherein Setting the second process control knob further comprises preferentially heating the first portion of the substrate support relative to the second portion. The method of claim 7, wherein Setting the second process control knob further comprises preferentially heating a peripheral portion of the substrate support relative to a central portion. The method of claim 7, wherein Setting the second process control knob further comprises preferentially cooling the first portion of the substrate support relative to the second portion. The method of claim 7, wherein Etching the substrate, a) etching the BARC layer; b) etching the hard mask layer; And c) etching the gate electrode layer, wherein at least two of the etching steps a) to c) are performed at different settings for one or more of the first and second process control knobs. Substrate etching method. The method of claim 16, Etching the gate electrode layer further comprises etching a polysilicon layer. The method of claim 17, Etching the gate electrode layer further comprises etching a metal material disposed over the polysilicon layer. The method of claim 7, wherein Etching the substrate further comprises etching polysilicon to form a high aspect ratio feature. The method of claim 19, Setting the first process control knob further includes flowing gas into the processing chamber in direct and indirect gas injection orientations, wherein the ratio of direct gas flow to indirect gas flow is from about 50:50 to about. It is 0: 100, The substrate etching method characterized by the above-mentioned. As a method for etching a substrate, Providing a substrate of a processing chamber having a selectable species of distribution in the processing chamber, and a side temperature controlled substrate support, wherein the temperature profile induced by the selection of the substrate support and species distribution comprises a set of control parameters. ; Etching the first layer of material using the first set of control parameters; And Etching the second layer of material using a second set of control parameters, wherein the first and second set of control parameters are different. Substrate etching method comprising a. The method of claim 21, Etching the first and second material layers, Etching the mask layer; And Etching the polysilicon to form a high aspect ratio feature. The method of claim 22, The set of control parameters for etching the polysilicon further includes flowing gas into the processing chamber in direct and indirect gas injection orientations, wherein the ratio of direct gas flow to indirect gas flow is 50:50. To about 0: 100. The method of claim 21, Etching the first and second material layers, Etching the mask layer; And And etching the gate electrode layer. The method of claim 24, Etching the gate electrode layer further comprises etching a polysilicon layer. The method of claim 25, Etching the gate electrode layer further comprises etching a metal material disposed over the polysilicon layer. The method of claim 21, Varying the gas flow distribution to the processing chamber to provide a difference between the first and second set of control parameters. The method of claim 27, Varying the distribution of species in the processing chamber further comprises flowing gas significantly into the processing chamber in an orientation substantially perpendicular to the plane of the substrate. The method of claim 21, Varying the orientation of the gas entering the processing chamber to provide a difference between the first and second set of control parameters. The method of claim 21, And varying the temperature profile of the substrate support to provide a difference between the first and second set of control parameters. The method of claim 30, Changing the temperature profile further comprises preferentially heating a peripheral portion of the substrate support relative to a central portion. The method of claim 30, Changing the temperature profile further comprises preferentially cooling the first portion of the substrate support relative to the second portion. The method of claim 21, Selecting the first and second set of control parameters to form a substantially uniform center for the edge distribution of the process results, wherein the process results comprise etch depth, CD deviation, microloading, sidewall profile, And at least one of passivation, etch rate, step coverage, feature taper angles, and undercutting.

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