WO2006059376A1

WO2006059376A1 - Semiconductor memory and manufacturing method thereof

Info

Publication number: WO2006059376A1
Application number: PCT/JP2004/017809
Authority: WO
Inventors: Hiroshi Murai; Masahiko Higashi
Original assignee: Spansion Llc; Spansion Japan Limited
Priority date: 2004-11-30
Filing date: 2004-11-30
Publication date: 2006-06-08
Also published as: TWI404173B; CN101091253A; TW200633146A; GB0710456D0; JPWO2006059376A1; GB2434919A; GB2434919B; DE112004003021T5; US20060091422A1; US7736953B2; JP5014802B2

Abstract

A semiconductor memory is provided with a semiconductor substrate (100), and first and second source regions (104) and (109), which are formed in the semiconductor substrate (100) and extend in first and second directions which orthogonally intersect. First and second source regions are diffusion regions and are electrically connected at a part where they cross. The semiconductor memory has a bit line (108) which extends in the same direction as the second source region (109), and a source line (115) formed on the second source region (109). A contact of the source line (115) and the second source region (109) and the contact of the bit line (108) and a drain region formed in the semiconductor substrate (100) are linearly arranged.

Description

Specification

Semiconductor memory and manufacturing method thereof

Technical field

TECHNICAL FIELD [0001] The present invention relates to a semiconductor memory, and more particularly, to a technique that enables simplification of the structure of a nonvolatile semiconductor memory device and simplification of a manufacturing process.

Background art

[0002] Flash memory, which is one of semiconductor memories, is a kind of electrically rewritable ROM, and is a non-volatile semiconductor memory device widely used in mobile phones, digital still cameras, communication network devices, and the like. It is. Flash memory is roughly divided into NOR type and NA ND type. Of these, NOR type flash memory is generally capable of random access and has a higher read speed than NAND type flash memory. In order to further improve the characteristics, various proposals have also been made regarding the wiring structure arranged in the memory cell array (see, for example, Patent Document 1).

FIG. 1 is a schematic diagram for explaining a configuration example of a conventional NOR flash memory. FIG. 1 (a) is a top view of a part of the flash memory, and FIG. 1 (b) is FIG. A sectional view along the A-line in (a), and Fig. 1 (c) are diagrams for explaining the state of the gate line near the source contact.

Referring to FIG. 1B, a plurality of diffusion regions (active regions) 18 extending in the vertical direction (Y direction) are formed on the main surface of the silicon semiconductor substrate 10. In FIGS. 1 (a) and 1 (c), the diffusion region 18 is schematically shown. These diffusion regions 18 are spaced apart in the lateral direction (X direction). In each diffusion region 18, the drain region 11 is periodically formed. The part indicated by reference numeral 18 also indicates a bit line formed of a wiring layer patterned with a metal such as aluminum. The bit line 18 is electrically connected to the drain region 11 through the drain contact 15.

A plurality of word lines (gate lines) 17 extending in the horizontal direction (X direction) are formed on the semiconductor substrate 10. The word line 17 includes a gate electrode 13. Under the gate electrode 13, a floating formed on the tunnel oxide film formed on the semiconductor substrate 10. A gate 20 and an insulating film ONO (oxide-nitride-oxide) 21 formed thereon are formed. The gate electrode 13 is formed on the insulating film ON021.

[0006] Between the word lines 17 adjacent in the vertical direction, a source region 14 extending in the horizontal direction is formed. The source region 14 is formed of a diffusion region 12 formed on the surface of the semiconductor substrate 10 as shown in FIG. Since the source region 12 is set to a reference potential Vss (for example, ground), it is also called a Vss line. A source line 19 extending in the vertical direction of the semiconductor substrate 10 is formed for each of a plurality of (for example, 8 or 16) bit lines 18. The source line 19 is a wiring layer obtained by patterning a metal such as aluminum. The source line 19 is electrically connected to the source region 14 via the source contact 16.

Patent Document 1: JP 2002-100689 A

Disclosure of the invention

Problems to be solved by the invention

However, the conventional NOR type flash memory as shown in FIG. 1 has the following problems.

First, in order to ensure a sufficient space necessary for providing the source contact 16, it is necessary to form the gate line 17 in the vicinity of the source contact 16 by bending it.

Second, in order to secure a space for forming the source contact 16, the geometrical arrangement of the drain contact 15 and the source contact 16 when viewed from the top view (FIG. 1 (a)) is different. Become. When the period in the Y direction of these contacts 15 and 16 is L, the source contact 16 and the drain contact 15 are shifted by 1Z2 period (LZ2).

[0010] Third, as shown in FIG. 1 (c), the wiring layer 18 connecting the drain contact 15 is connected to the interval C, and the wiring layer 19 connecting the source contact 16 and the drain contact 15 are connected. Comparing the distance D with the wiring layer 18 to be used, C <D must be satisfied, and a relatively large dead space is formed in the vicinity of the source contact 16.

[0011] Fourthly, the diameter d of the source contact 16 and the diameter d of the drain contact 15 'adjacent thereto,

1 2 and other drain contacts 15 have different d values (d> d> d)

3 1 3 2

The shape can also be different. For this reason, it is necessary to acquire OPC (Optimum Write Power Control) data for each of these contacts. [0012] The present invention has been made in view of such a problem, and an object thereof is to realize simplification of the structure of a semiconductor memory and simplification of a manufacturing process.

Means for solving the problem

[0013] The present invention is a semiconductor memory having a semiconductor substrate and first and second source regions formed in the semiconductor substrate and extending in first and second directions orthogonal to each other. is there. Since the source region extending in the vertical and horizontal directions on the surface portion of the semiconductor substrate is formed, the degree of freedom in forming the source contact is generated, and the structure of the semiconductor memory and the manufacturing process can be simplified.

In the semiconductor memory, preferably, the first and second source regions are each a diffusion region, and are electrically connected at intersecting portions. Preferably, the first and second source regions each have a linear region. The semiconductor memory includes a drain region formed in the semiconductor substrate, a bit line extending in the same direction as the second source region, and a source formed on the second source region. A contact line between the source line and the second source region and a contact between the bit line and the drain region formed in the semiconductor substrate are preferably arranged in a straight line. . In addition, it is preferable that the bit line is disposed on both sides of the second source region. The distance between the source line and the bit line adjacent to the source line is preferably smaller than the distance between adjacent bit lines. The semiconductor memory preferably has a linear word line extending in the same direction as the first source region, and the first source region is disposed between adjacent word lines. The word line may include a gate electrode formed on the semiconductor substrate. The first and second source regions are diffusion regions formed in separate diffusion steps. Further, the semiconductor memory is, for example, a NOR type flash memory having a floating gate.

The present invention also provides a step of forming a first source region extending in a first direction in a semiconductor substrate, and a second direction extending in a second direction orthogonal to the first direction. And a method of manufacturing a semiconductor memory. In this manufacturing method, the floating gate and the gate electrode are formed after the second source region is formed. It is preferable that the process is included.

The invention's effect

In the present invention, since the source line is formed by two diffusion regions extending in the vertical and horizontal directions (X direction and Y direction when the substrate surface is an XY plane), the gate line (word line) Thus, a technique capable of simplifying the structure of the semiconductor memory device and simplifying the manufacturing process is provided.

Brief Description of Drawings

[0017] [FIG. 1] A schematic diagram for explaining the configuration of a conventional NOR flash memory, (a) is a top view of a part of the flash memory, and (b) is A in (a). — A cross-sectional view along the A ′ line, and (c) is a diagram for explaining the state of the gate line near the source contact.

FIG. 2 is a schematic diagram for explaining the configuration of the NOR type flash memory of the present invention, where (a) is a top view of a part of the flash memory, and (b) is a B-line in (a). FIG. 8C is a cross-sectional view taken along the line, and FIG. 8C is a view for explaining the state of the gate line in the vicinity of the source contact.

FIG. 3 is a diagram for explaining a manufacturing process of a flash memory according to the present invention, illustrating each process from forming STI (Shallow Trench Isolation) to forming a vertical source line and a floating gate.

FIG. 4 is a diagram for explaining the manufacturing process of the flash memory according to the present invention, and shows each process from gate formation to lateral source line formation.

FIG. 5 is a diagram for explaining a manufacturing process of a flash memory according to the present invention, and shows a process for forming a contact layer and forming a wiring layer.

FIG. 6 is a flow chart for explaining the manufacturing process of the flash memory according to the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

[0018] Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

Example 1

In the present invention, the second source line (wiring layer) having the above-described conventional configuration is formed in the diffusion region. In other words, in the semiconductor memory of the present invention, the two extending in the horizontal direction and the vertical direction are By providing a diffusion region, the gate line (word line) can be formed without bending.

FIG. 2 is a diagram for explaining a configuration example of the semiconductor memory device according to the present invention. Here, the semiconductor memory device is assumed to be a NOR flash memory. Fig. 2 (a) is a top view of a part of this flash memory, Fig. 2 (b) is a cross-sectional view taken along line B-B 'in Fig. 2 (a), and Fig. 2 (c) is a source contact. It is a figure for demonstrating the mode of the gate line of the vicinity. The cross-sectional view along the line AA ′ shown in FIG. 1 (b) is the same in this embodiment.

Referring to FIG. 2 (b), a diffusion region (active region) 102 extending in the vertical direction (Y direction) is formed on the main surface of the silicon semiconductor substrate 100. This diffusion region 102 is a source region (second source region) and constitutes a source line 109. This source line 109 replaces 19 formed by the metal wiring layer described above. The source line 109 is provided for each of a plurality of (for example, 8 or 16) bit lines 108. The source line 109 intersects a source line 104 formed by a diffusion region (first source region) extending in the X direction. That is, the diffusion region 102 of the source line 109 intersects with the diffusion region of the lateral source line 104 (corresponding to the diffusion region 12 of FIG. 1B). The source lines 109 and 106 are electrically connected to each other at the intersecting diffusion region portions and have the same potential. The source line 109 is electrically connected to a wiring layer formed of a metal such as aluminum, which will be described later, via the source contact 106.

The bit line 108 is a wiring layer formed of a metal such as aluminum. A diffusion region is formed on the surface of the semiconductor substrate 100 located below the bit line 108. In this diffusion region, drain regions 11 are periodically formed. The bit line 108 is electrically connected to the drain region via the drain contact 105.

A plurality of word lines (gate lines) 107 extending in the horizontal direction (X direction) are formed on the semiconductor substrate 100. The word line 107 includes a gate electrode 103. Under the gate electrode 103, a floating gate 120 formed on the tunnel oxide film on the semiconductor substrate 100 and an insulating film ONO 121 formed thereon are formed. The gate electrode 103 is formed on the insulating film ONO 121.

In the flash memory having such a configuration, the wiring provided on the main surface of the semiconductor substrate 100 Two vertical and horizontal source lines 104 and 109 formed as diffusion regions in the crystal of the semiconductor substrate 100 without using layers are formed. This eliminates the need to provide the source contact 106 on the source line 104 in the X direction, allows the formation of the source contact 106 without bending the gate line (word line) 107, and reduces the area of the memory cell. It becomes possible to do.

In addition, since it is not necessary to provide the source contact 106 on the X-direction source line 104, the same arrangement can be achieved without shifting the arrangement period of the drain contact 105 and the source contact 106. That is, the arrangement interval of the source contacts 106 in the Y direction is equal to the arrangement interval of the drain contacts 105 in the Y direction, and each of the source contacts 106 is arranged on a straight line connecting a plurality of the drain contacts 105 in the X direction. Is possible. Furthermore, the diameter of the source contact 106, the diameter of the drain contact 105 to be provided adjacent thereto, and the diameters (and their shapes) of the other drain contacts 105 can be designed to be equal.

Furthermore, as shown in FIG. 2 (c), the distance B between the source line 109 for connecting the source contact 106 and the bit line (wiring layer) 108 adjacent thereto is connected to the drain contact 105. It is possible to perform layout so that the interval A between successive bit lines 108 is less than or equal to A. In addition, since the s-curved portion of the gate line 107 is eliminated, it is easy to align the mask when forming the source line by ion implantation.

As described above, the structure of the semiconductor memory device according to the present invention in which the source line is formed of two diffusion regions in the vertical and horizontal directions is greatly simplified, and the manufacturing process thereof is also simplified. An example of the method for manufacturing the semiconductor memory of Example 1 will be described in detail in Example 2. Example 2

[0028] FIG. 3-6 is a diagram for explaining the manufacturing process of the flash memory in the present embodiment. FIG. 3 shows from STI (Shallow Trench Isolation) formation to vertical source line 109 and floating gate formation. FIG. 4 shows each process from gate formation force to formation of the source line 104 in the lateral direction, and FIG. 5 illustrates each process from contact formation to wiring layer formation, and FIG. 6 is a flowchart of these processes.

[0029] In each figure of FIGS. 3-5, the left figure is a schematic top view and the upper right figure is an E-line in the left figure. The cross-sectional schematic diagram along the line, and the lower right diagram is the schematic cross-sectional diagram along the F to T line in the left diagram.

Figure 4 (b) also shows a schematic cross-sectional view along the G-line.

First, referring to FIG. 3A, one main surface of a silicon semiconductor substrate 100 is provided with an STI in which the surface of the silicon semiconductor substrate 100 is etched and filled with an insulator 110. A partial area of the surface of 100 is exposed in a striped manner extending in the vertical direction of the left figure. Such STI formation is performed by a known photolithography technique, etching technique, and gap fill technique (step S101). The STI is provided because it is effective for reducing the size of the STI element isolation camera cell.

[0031] Of the surface of the semiconductor substrate 100 exposed in the form of stripes, the region denoted by reference numeral 100a is the region that will later become the source line 109 in the vertical direction (Y direction) (in the left figure). The area indicated by reference numeral 100b later corresponds to the formation area of the bit line 108 in the vertical direction (in the left figure).

[0032] Subsequent to the formation of the STI 110, the region other than the region indicated by 100a on the surface of the semiconductor substrate 100 is covered with a photoresist 111, and a desired implantation depth and dose amount are formed from the mask opening of the photoresist 111. By performing ion implantation, a source line 109 (diffusion layer 102) extending in the Y direction is formed as shown in FIG. 3B (step S102).

[0033] After the ion implantation is completed, the photoresist 111 is removed, and a layer 112 to be a floating gate 120 is formed on the tunnel oxide film using a known photolithography technique, a film forming technique, and an etching technique ( Figure 3 (c), step S103).

Next, after a layer for forming the word line 107 is formed on the entire surface of the wafer, a predetermined patterning is performed by a known photolithography technique and etching technique, and a gate line (word word) extending in the X direction is formed. Line) 107 is formed.

Thereby, a gate portion having a structure formed by the straight gate line 107 having no curved portion is obtained (step S104). At the time of the above etching, the layers 112 other than those located under the gate line 107 are removed, and the aforementioned floating gate 120 is formed (FIG. 4A).

Subsequently, the region shown in the left figure of FIG. 4 (b) is covered with a photoresist 113 to form a mask, and the opening force of this mask is set at a predetermined inclination angle, implantation depth, and dose. Ion implantation To form the source line 104 in the X direction (step S105). In this process, the region where the source line 109 in the Y direction intersects with the source line 104 in the X direction is electrically connected (FIG. 4 (b)).

Further, after the interlayer insulating film 114 is formed on the entire surface of the wafer, a contact hole is provided at a predetermined position by a known photolithography technique and etching technique. Then, the contact hole is filled with metal to form the drain contact 105 and the source contact 106 (FIG. 5 (&), step 3106). Finally, a metal wiring 115 for connecting these contacts to each other is formed (FIG. 5 (b), step S107). The metal wiring 115 formed on the Y-direction source line 109 is connected to the source line 109 via the source contact 106. Also, the metal wiring 115 serving as a bit line is connected to the drain region via the drain contact 105! RU

As described above, when the semiconductor memory device of the present invention is manufactured, first, before forming the gate line 107, a portion other than the diffusion region for forming the source contact 106 is covered with a photoresist, A source line 109 extending in the Y direction is formed in the semiconductor substrate 100 by implantation. Then, a source line 104 extending in the X direction after forming the gate line 107 is formed in the semiconductor substrate 100, and this is connected to the source line 109 in the Y direction. In this way, the source contact 106 can be formed without bending the gate line 107, and the source contact 106 having the same arrangement as the drain contact 105 can be obtained.

As described above, according to the present invention, it is possible to provide a technique capable of simplifying the structure of a semiconductor memory device and simplifying the manufacturing process, and a semiconductor memory device having a conventional structure. Various inconveniences of the device are eliminated.

[0040] The preferred embodiment of the present invention has been described in detail above, but the present invention is not limited to the specific embodiment, and various modifications can be made within the scope of the gist of the present invention described in the claims. Deformation · Change is possible.

Claims

The scope of the claims

[I] A semiconductor memory having a semiconductor substrate and first and second source regions formed in the semiconductor substrate and extending in first and second directions orthogonal to each other.

2. The semiconductor memory according to claim 1, wherein each of the first and second source regions is a diffusion region, and is electrically connected at a crossing portion.

[3] The semiconductor memory according to [1] or [2], wherein each of the first and second source regions has a linear region.

[4] The semiconductor memory is formed on the drain region formed in the semiconductor substrate, a bit line extending in the same direction as the second source region, and the second source region. A contact between the source line and the second source region and a contact between the bit line and a drain region formed in the semiconductor substrate are arranged in a straight line. The semiconductor memory according to any one of 1 to 3 above.

5. The semiconductor memory according to claim 4, wherein the bit lines are arranged on both sides of the second source region.

6. The semiconductor memory according to claim 4, wherein a distance between the source line and the bit line adjacent to the source line is smaller than a distance between adjacent bit lines.

7. The semiconductor memory has a linear word line extending in the same direction as the first source region, and the first source region is disposed between adjacent word lines. 6. The semiconductor memory according to any one of 6.

8. The semiconductor memory according to claim 7, wherein the word line includes a gate electrode formed on the semiconductor substrate.

[9] The semiconductor memory according to any one of [1] to [8], wherein each of the first and second source regions is a diffusion region formed in a separate diffusion step.

10. The semiconductor memory according to claim 1, wherein the semiconductor memory is a NOR type flash memory having a floating gate.

[II] forming a first source region extending in the first direction in the semiconductor substrate;

Forming a second source region extending in a second direction orthogonal to the first direction. A method of manufacturing a semiconductor memory. 12. The method of manufacturing a semiconductor memory according to claim 11, wherein the manufacturing method includes a step of forming a floating gate and a gate electrode after forming the second source region.