WO2006059267A2 - Electronic device having multi operand arithmetic circuitry - Google Patents
Electronic device having multi operand arithmetic circuitry Download PDFInfo
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- WO2006059267A2 WO2006059267A2 PCT/IB2005/053929 IB2005053929W WO2006059267A2 WO 2006059267 A2 WO2006059267 A2 WO 2006059267A2 IB 2005053929 W IB2005053929 W IB 2005053929W WO 2006059267 A2 WO2006059267 A2 WO 2006059267A2
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- overflow
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- binary input
- arithmetic
- binl
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49994—Sign extension
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49905—Exception handling
- G06F7/4991—Overflow or underflow
- G06F7/49921—Saturation, i.e. clipping the result to a minimum or maximum value
Definitions
- the invention relates to an electronic device with an arithmetic circuitry for performing at least one of an addition or a subtraction of more than two binary input numbers. At least two of the binary input numbers differ in their bit-width.
- the invention is also related to a method for addition or subtraction of more than two binary input numbers. Further, the invention relates to a method for designing an arithmetic circuitry.
- the invention relates also to a data processing system with an electronic device with an arithmetic circuitry for performing at least one of an addition or a subtraction of more than two binary input numbers with different bit-widths.
- Arithmetic units used in digital signal processors (DSPs), other kinds of processors or microcontrollers, as well as in application specific integrated circuits (ASICs), comprise binary input numbers with a predefined number of bits.
- the number of bits representing a binary input number is the bit-width.
- a finite bit-width entails a finite range of representable numbers. Due to the finite range of representable numbers, the binary input numbers in a logic unit are confined to a maximum representable value, a minimum representable value and a finite quantization. In order to avoid excess of the minimum and maximum values during calculation the calculation result has an enlarged bit-width to cover all possible results.
- overflow (or underflow) indicator is generated to signal a violation of the predetermined bit-width.
- overflow or underflow flags are used to indicate whether a calculation result extends the allowable value range or not.
- the binary input number representing the calculation result is set to a predefined value, that is the maximum or minimum representable value. This step is called saturation.
- Overflow detection and saturation arithmetic are widely used features of arithmetic processing units employed in DSP, microcontrollers, and microprocessors. Saturation is necessary to reduce errors occurring due to quantization and due to the finite range of representable numbers in computer arithmetic.
- Binary input numbers are used in signed and unsigned formats. A common format for signed binary input numbers is the 2's complement. According to the 2's complement, a negative value has leading 1.
- Most processor architectures are based on a two-operand model. Accordingly, always two binary input numbers having the same binary representation and the same bit- width are computed. If the same arithmetic operation has to be applied to more than two numbers, the operation can be performed serially, i.e.
- processors In particular, today's application-specific processors often require more than a two-operand based arithmetic. Additionally, the bit- width of the binary input numbers to be computed may vary, even for the same arithmetic unit.
- processors two scenarios might be considered: processors or controllers having an algorithmic logic unit for usually multiplying and adding two digital numbers retrieved from a memory as well as ASICs including dedicated logic to perform calculation steps in a more efficient way.
- Hierarchical circuit design strategies start at a rather behavioral description of a circuitry.
- either the designer or the design software synthesizes logic gates and transistors to meet the behavioral definition.
- a schematic and a layout of the circuitry exist, on the basis of which the circuitry is finally manufactured.
- various steps of the design process are carried out automatically.
- the resulting arithmetic circuitry is often not completely optimized after the automatic synthesizing steps. Therefore, a lot of effort is put in the finding of effective concepts and rules to design optimized algorithmic circuitry.
- the overflow detection for addition or subtraction is widely known.
- the bit-width of the calculation result is one bit greater than the bit-widths of the binary input number.
- a carry flag (or bit) is provided.
- the overflow flag is the carry flag for unsigned integers or the logical AND of the negated carry flag and the highest bit position of the result for the signed case.
- An underflow flag can be obtained by use of the same logic. As soon as an overflow or an underflow is detected, a saturation is to be applied. When saturated, the obtained result is replaced by the maximum (in case of overflow) or minimum (in case of underflow) representable value.
- US 2003/0140072 relates to two-input addition. Both inputs have the same bit- widths.
- US 6,321,248 discloses an overflow detection for a two-input operation. A particular case for two operands having different bit-widths is mentioned for the two-operand operation.
- Pai and Tran disclose an algorithm to detect overflow in multi-operand addition.
- the algorithm is extended to support generic commercial arithmetic adder chips. This is used in conjunction with a multi-operand carry-save adder and a multi-operand bit-serial adder to detect overflow. Provision is also made in these circuits to incorporate subtraction of operands.
- CAD tools are used to simulate the logic in hardware for the verification of the algorithm. According to Pai and Tran, all inputs have the same bit- width. They propose to count the required number of carry-out bits depending on the number of inputs.
- overflow includes “underflow”. Accordingly, any reference made to “overflow detection” and a corresponding saturation (maximum) should be understood as comprising the case of “underflow detection” and a corresponding saturation (minimum).
- the object is solved by a an electronic device according to claim 1, a data processing system according to claim 6, a method for calculating a sum or difference of N binary input numbers according to claim 7, and a method for designing an arithmetic circuitry according to claim 8.
- an electronic device comprising an arithmetic circuitry for performing at least one of an addition or a subtraction of more than two binary input numbers, wherein at least two of the binary input numbers differ in their bit- widths.
- the arithmetic circuitry comprises an extension means for performing a sign and/or a zero extension of at least one of the binary input numbers.
- the arithmetic circuitry comprises at least two two-operand arithmetic units, each for calculating an addition and/or a subtraction of two operands being a first and a second binary number, and overflow and saturation means for detecting a calculation overflow of at least one two-operand arithmetic unit and for saturating the calculation result of the arithmetic unit in accordance with the detected overflow result.
- an extension means is disposed, where necessary, to extend the binary input numbers to have the same bit-widths during calculation.
- An extension means might be arranged at the input to the arithmetic circuitry in order to extend all the binary input numbers to the same bit-width.
- an extension means can be located between two two-operand arithmetic units for extending the output of a presiding two-operand arithmetic unit before it is input to the next two-operand arithmetic unit.
- the overflow and saturation means controls the calculation results of the two- operand arithmetic units, detect calculation overflows and set the calculation results to a maximum or minimum value according to the detected overflow result.
- the overflow and saturation means may control the outputs of all the two-operand arithmetic units or just some of them, if it is predetermined that overflow will not occur in a particular stage of the circuitry.
- Sign extension is used in case of signed operation and zero extension is used in case of unsigned operation.
- the proposed arithmetic unit can have more than two inputs with different bit-widths and still detect overflow or underflow and saturate the result correctly.
- the extension means detect whether an input operand needs sign or zero extension and extend the operand accordingly.
- the arithmetic circuitry comprises an input means for inputting at least one binary input number to the extension means. If an input means is provided for more than one binary input number, the numbers can be input in a parallel manner. For numerous applications, a rather parallel approach of inputting numbers is advantageous over a serial manner, allowing only to input numbers one after the other or bit by bit.
- a plurality of extension units is provided in the arithmetic circuitry for performing a sign and/or zero extension of at least one of the binary input numbers for each binary input number having a smaller bit- width than the binary input number having the greatest bit-width.
- a very effective approach is the use of a plurality of extension units instead of a more or less centralized extension means. It is preferred to dispose each extension unit close to an input unit to the arithmetic circuitry. This way, each extension unit might be dedicated to extend one binary input number with a smaller bit-width than the one with the largest bit-width.
- bit-width of the binary input number with the greatest bit-width is determined and the other binary input numbers having smaller bit-widths are extended to have the greatest bit-width.
- the extension units are not necessarily disposed at the input of the arithmetic circuitry, but might also be located somewhere within the arithmetic circuitry.
- all the extension units provide an input for inputting a control signal that indicates whether the binary input number that is passed to the extension unit is of a signed or unsigned format. Accordingly, the extension unit is controlled by the input, which is typically a single bit control input, to sign or zero extend the binary number in response to the indicated binary input number format.
- the electronic device comprises a plurality of overflow and saturation units, each for detecting a calculation overflow of a single two-operand arithmetic unit and for saturating the calculation result of the two-operand arithmetic unit in accordance with the detected overflow result.
- the use of a plurality of overflow and saturation units gives rise to a rather independent operation that can attribute to calculation speed and effectiveness of the whole arithmetic circuitry.
- each of the two-operand arithmetic units is followed by a dedicated overflow and saturation unit
- the respective logic circuitry, to realize the overflow and saturation procedure can be less sophisticated than in the case of one overflow and saturation means used for a plurality of two-operand arithmetic units.
- the invention is also related to a method for calculating a sum and/or a difference of N binary input numbers, if N is greater than two and at least two of the binary input numbers differ in their bit-widths.
- the method includes the step of extending at least one binary input number having a shorter bit-width to have the same bit-width as a second binary input number.
- a sum and/or a difference of two binary input numbers is calculated.
- the calculation step is performed by using N-I two-operand arithmetic units, each for calculating an addition and/or a subtraction of two operands being a first and a second binary number.
- the invention is further related to a method for designing arithmetic circuitry for performing an addition and/or a subtraction of N binary input numbers, wherein N is greater than two and at least two of the binary input numbers differ in their bit-width.
- Input means to input the N binary input numbers to the arithmetic circuitry Input means to input the N binary input numbers to the arithmetic circuitry, extension means for performing a sign and/or zero extension of at least one of the binary input numbers, N-I two-operand arithmetic units, each for calculating an addition and/or subtraction of two operands being a first and a second binary number, overflow and saturation means for detecting a calculation overflow of at least one two- operand arithmetic unit and for saturating the calculation result of the arithmetic unit in accordance with the detected overflow result, and connections between the input means, extension means, the arithmetic units and the overflow and saturation means.
- An arithmetic circuitry, designed with respect to the above design steps, is less complex and more effective than conventional circuitry.
- the method for designing the arithmetic circuitry comprises a step of connecting the arithmetic circuitry such that each output of the N-I two-operand arithmetic units is connected to the overflow and saturation means.
- Fig.1 shows a block diagram of a three-operand arithmetic circuitry according to a first embodiment of the invention
- Fig. 2 shows a block diagram of a multi-operand arrangement according to a second embodiment of the invention
- Fig. 3 shows a block diagram of a multi-operand arithmetic circuitry according to a third embodiment of the invention.
- Fig. 1 shows a block diagram of a three-operand arithmetic circuitry according to the first embodiment of the invention.
- Three binary input numbers BINl, BIN2 and BIN3 are input to the arithmetic circuitry AC.
- the first and second binary input numbers BESf 1, BIN2 have smaller bit-widths bwl, bw2 than the third binary number BIN3.
- the first and second binary input numbers BINl, BIN2 are input to a first and a second extension unit EUl, EU2.
- the binary input numbers BINl, BIN2 are sign or zero extended respectively, to have the same bit -width as the bit-width bw3 of the third binary input number BIN3.
- the two sign extension units EUl, EU2 are connected to the inputs of a first two-operand arithmetic unit AUl.
- the arithmetic unit AUl performs a calculation step on its two inputs. This calculation step can be a subtraction or an addition or any similar operation on the two input operands.
- the output of the first two-operand arithmetic unit AUl is controlled by a first overflow and saturation unit OSUl .
- the overflow and saturation unit OSUl checks the output of the first two-operand arithmetic unit AUl, detects a possible overflow and saturates the calculation result according to the detected overflow.
- bit-width bw3 of the third binary input number BIN3 is 8 bit
- bit-widths bw4, bw5 of the extended binary input numbers BINl and BIN2 have also a bit- width of 8 bit.
- the output of AUl is then 9 bit or 10 bit wide.
- the overflow and saturation unit OSUl restricts the result to 8 bit.
- the output of OSUl has the bit-width bw7, which is equal to the bit-width bw3 of the binary input number BIN3.
- the output of the first overflow and saturation unit OSUl is input to a second two-operand arithmetic unit AU2.
- the second input to the second two-operand arithmetic unit AU2 is the third binary input number BESf 3, on which an arithmetic operation is to be performed. Both inputs have the same bit-widths, since bw7 equals bw3. This is due to the first and second extension units EUl, EU2, which extend the first and second binary input numbers BINl, BIN2 to the same bit-width as the third binary input number BIN3 and due to OSUl.
- the output of the second two-operand arithmetic unit AU2 is overflow controlled and saturated according to a detected overflow by a second overflow and saturation unit OSU2.
- the bit- width bw8 of the output of AU2 is 9 bit or 10 bit.
- the result is again restricted to a bit-width of 8 bit. If subsequent calculation or processing stages can handle more than 8 bit, OSU2 can be omitted.
- the output of the second overflow and saturation unit OSU2 is the correct sum of the three binary input numbers BINl, BIN2 and BIN3.
- the output of the second overflow and saturation unit OSU2 is the correct difference of the three binary input numbers BINl, BIN2 and BIN3.
- Fig. 2 shows a block diagram of a second embodiment of the invention.
- Four binary input numbers BINl - BIN4 are input to the arithmetic circuitry AC.
- Four input units IUl - IU4 are provided for inputting the four binary input numbers BINl - BIN4, respectively.
- the input units IUl - IU4 are input pins or equivalent connections or even latches or the like, to input the binary input numbers BIN1-BIN4 to the arithmetic circuitry AC.
- the four input units IUl - IU4 may be arranged separately on the same or on different sides of the arithmetic circuitry AC.
- the four input units IUl - IU4 can be realized as one block, wherein input pins or connections or latches are reused for inputting two or more binary input numbers BINl - BIN4.
- the binary input numbers BINl - BIN3 have smaller bit-widths bwl, bw2, bw3 than the bit-width bw4 of the fourth binary input number BIN4.
- the outputs of the input units IUl, IU2, IU3 have bit-widths bw5, bw6, bw7, respectively which are typically equal to bwl, bw2, bw3. This does not exclude that the binary input signals are made symmetric in the input units.
- Extension units EUl to EU3 are provided for the binary input numbers BINl - BIN3 having bit-widths bw5, bw6 and bw7, respectively.
- the extended binary input numbers BINl and BIN2 have the same bit- width bw8, bw9, and are added or subtracted in a first two-operand arithmetic unit AUl.
- the output of the first arithmetic unit AUl has a bit-width bwl2 and is overflow and saturation controlled by a first overflow and saturation unit OSUl .
- the third binary input number BIN3 is combined with the output of the first overflow and saturation unit OSUl.
- the output of the second arithmetic unit AU2 is overflow and saturation controlled by a second overflow and saturation unit OSU2.
- the overflow and saturation controlled output is passed to a third two-operand arithmetic unit AU3.
- This unit performs an operation on the output of the second overflow and saturation unit OSU2 and the fourth binary input number BIN4.
- the output of the third two-operand arithmetic unit AU3 is overflow and saturation controlled by a third overflow and saturation unit OSU3.
- the output of the third overflow and saturation unit OSU3 is the correct sum of the three binary input numbers BINl - BIN4.
- the outputs of the first algorithmic unit AUl has a bit width bwl2, that is one or two bit wider than the bit-width bw8, bw9 of the two input operands to the algorithmic unit AUl.
- the bit-width bwl2 is restricted in OSUl to the bit-width bwl3, that is equal to bwlO.
- the output of the second algorithmic unit AU2 has a bit- width bwl4 that is restricted in OSU2 to the bit-width bwl5.
- bwl5 is equal to bwl 1.
- bwl 1 is equal to bw4.
- the two binary numbers having the bit- width bwl 5 and bwl 1 are fed to the algorithmic unit AU3.
- the output has a bit- width bwl 6, being one or two bit greater than the bit- width bwl 5 and bwl 1 of the inputs to AU3.
- the output of AU3 is fed to OSU3, where it is restricted to the bit- width bwl7.
- bwl7 is equal to bw4. It is also possible that bwl7 is one or two bits greater than bw4.
- Fig. 3 shows a block diagram of a third embodiment of the invention which constitutes an alternative embodiment to the second embodiment.
- Four binary input numbers BINl - BIN4 are input to the arithmetic circuitry AC.
- Four input units IUl - IU4 are provided for inputting the four binary input numbers BINl - BIN4, respectively.
- the input units IUl - IU4 are input pins or equivalent connections or even latches, buffers or the like, to input the binary input numbers BINl - BIN4 to the arithmetic circuitry AC.
- the four input units IUl - IU4 may be arranged separately on the same or on different sides of the arithmetic circuitry AC.
- the four input units IUl - IU4 can be realized as one block, wherein input pins or connections or latches are reused for inputting two or more binary input numbers BINl - BIN4.
- the binary input numbers BINl to BIN3 have a smaller bit- width bwl, bw2, bw3 than the bid- width bw4 of the fourth binary input number BIN4.
- extension units EUl to EU3 are provided for the binary input numbers BINl - BIN3.
- the extension units EUl - EU3 are optionally provided with a single-bit control input. If the single-bit control input is "HIGH", the sign extension unit EUl, EU2, or EU3 performs a sign-extension.
- the sign-extension unit EUl, EU2, or EU3 performs a zero extension. If such a sign-extension control is used, all extension units EU1-EU3 must be controlled by the same sign signal, indicating if signed or unsigned operation has to be performed.
- the extended binary input numbers BINl and BIN2 are added or subtracted in a first two-operand arithmetic unit AUl.
- the output of AUl has a bit-width bwl2.
- the third and fourth binary input numbers BIN3 and BIN4 are added or subtracted in a second two-operand arithmetic unit AU2.
- the outputs of the first and second arithmetic units AUl, AU2 having the bit-widths bwl2, bwl3 are overflow and saturation controlled by a first and a second overflow and saturation unit OSUl and OSU2 and restricted to bit-widths bwl4, bwl5, respectively.
- the overflow and saturation controlled outputs have equal bit- widths bwl5, bwl ⁇ , and they are passed to a third two-operand arithmetic unit AU3. This unit calculates the sum or difference of the two overflow and saturation controlled outputs of the first and second two-operand arithmetic units AUl and AU2.
- the output of the third two- operand arithmetic unit AU3 has the bit- width bwl ⁇ and is overflow and saturation controlled by a third overflow and saturation unit OSU3.
- the bit-width of the output of OSU3 is bwl7.
- bwl7 is equal to bw4 or 1 or 2 bits greater, in case subsequent calculation or processing units can handle greater bit-widths.
- the output of the third overflow and saturation unit OSU3 is the correct sum of the three binary input numbers BINl - BIN4.
- a designing method for designing an arithmetic circuitry AC is provided.
- the respective algorithmic circuitry AC of the first, second and third embodiments shown in Figs. 1, 2 and 3 can be the result of an automatic or semi-automatic design synthesis process.
- the rules for the design procedure for 4 binary input numbers with varying bit-widths can be defined as follows. First, input units IUl, IU2, IU3, IU4 for inputting the 4 binary input numbers BINl- BIN4 to the arithmetic circuitry are provided.
- three extension units EUl, EU2, EU3 for performing a sign or zero extension of the binary input numbers BINl, BIN2, BIN3 is provided.
- Three two-operand arithmetic units AUl, AU2, AU3 are provided in a further design step.
- the arithmetic units AUl - AU3 three overflow and saturation units OSUl, OSU2, OSU3 for detecting a calculation overflow the three two-operand arithmetic units AUl, AU2, AU3 are provided, wherein the overflow and saturation units OSUl, OSU2, OSU3 saturate the calculation result of the arithmetic units AUl, AU2, AU3 in accordance with the detected overflow result.
- connections between the input units IUl, IU2, IU3, the extension units EUl, EU2, EU3, the arithmetic units AUl, AU2, AU3 and the overflow and saturation units OSUl, OSU2, OSU3 are provided. All the mentioned steps are performed such that based on the resulting schematic or layout a circuitry as exemplarily shown in Figures 2 or 3 can be manufactured.
- two-operand arithmetic units AUl - AU3 for calculating a sum or a difference of four binary input numbers BINl, BIN2, BIN3, BIN4 is provided.
- the binary input numbers BINl, BIN2, BIN3 differ in their bit-widths.
- the binary numbers BINl - BIN3 are extended to have the same bit-width as the fourth binary input number BIN4.
- Three two- operand arithmetic units AUl, AU2, AU3 are used, each for calculating an addition or a subtraction of two operands.
- an overflow of the calculation result of the algorithmic units AUl- AU3 is detected and the calculation result is saturated in accordance with the detected overflow result.
- All mentioned embodiments of the present invention may comprise input units for inputting binary input numbers. However, input units are not necessarily part of the embodiments. Each input unit may provide a single-bit control input to switch between sign and zero extension in response to the control input's value.
Abstract
Description
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Priority Applications (2)
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EP05825414A EP1820092A2 (en) | 2004-12-01 | 2005-11-28 | Electronic device having multi operand arithmetic circuitry |
JP2007543953A JP2008522304A (en) | 2004-12-01 | 2005-11-28 | Electronic device having multi-operand arithmetic circuit |
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EP04106211 | 2004-12-01 | ||
EP04106211.8 | 2004-12-01 |
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JP (1) | JP2008522304A (en) |
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Cited By (1)
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US8316071B2 (en) | 2009-05-27 | 2012-11-20 | Advanced Micro Devices, Inc. | Arithmetic processing unit that performs multiply and multiply-add operations with saturation and method therefor |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999021078A2 (en) * | 1997-10-23 | 1999-04-29 | Advanced Micro Devices, Inc. | A method and apparatus for multi-function arithmetic |
GB2367659A (en) * | 2000-10-04 | 2002-04-10 | Advanced Risc Mach Ltd | SIMD saturation instruction with variable bit length |
US20030169077A1 (en) * | 2002-02-08 | 2003-09-11 | Stmicroelectronics S.A. | High-efficiency saturating operator |
-
2005
- 2005-11-28 JP JP2007543953A patent/JP2008522304A/en active Pending
- 2005-11-28 CN CNA2005800411258A patent/CN101069152A/en active Pending
- 2005-11-28 EP EP05825414A patent/EP1820092A2/en not_active Withdrawn
- 2005-11-28 WO PCT/IB2005/053929 patent/WO2006059267A2/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999021078A2 (en) * | 1997-10-23 | 1999-04-29 | Advanced Micro Devices, Inc. | A method and apparatus for multi-function arithmetic |
GB2367659A (en) * | 2000-10-04 | 2002-04-10 | Advanced Risc Mach Ltd | SIMD saturation instruction with variable bit length |
US20030169077A1 (en) * | 2002-02-08 | 2003-09-11 | Stmicroelectronics S.A. | High-efficiency saturating operator |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8316071B2 (en) | 2009-05-27 | 2012-11-20 | Advanced Micro Devices, Inc. | Arithmetic processing unit that performs multiply and multiply-add operations with saturation and method therefor |
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WO2006059267A3 (en) | 2006-09-08 |
JP2008522304A (en) | 2008-06-26 |
CN101069152A (en) | 2007-11-07 |
EP1820092A2 (en) | 2007-08-22 |
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